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`Case 6:22-cv-00466-ADA-DTG Document 50-8 Filed 12/19/22 Page 1 of 23
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`
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicants: Leatheret al.
`
`Serial No.:
`
`Examiner:
`
`Art Group:
`
`Filing Date:
`
`June 12, 2003
`
`Docket No.: 00100.02.0053
`
`Title: DIVIDING WORK AMONG MULTIPLE GRAPHICSPIPELINES USING A
`SUPER-TILING TECHNIQUE
`
`Certificate ofExpress Mail
`T hereby certify that this paper is being deposited with the
`United States Postal Service “Express Mail Post Office to
`Addressee”service under 37 CFR 1.10, on the date
`indicated and is addressed to Mail Stop Patent
`Application, Commissionerfor Patents, P.O. Box 1450,
`hte. AN 9313-1450
`
`Alexandria,VA22313-145 Alexandria, VA 22313-1450,
`Express Mail No. EV 063310627 US.
`
`Mail Stop Patent Application
`Commissioner for Patents
`
`
`
`Date
`
`Winona K. Jackson
`
`PRELIMINARY AMENDMENT
`
`Dear Sir:
`
`Prior to examination, Applicants respectfully request that the above-identitied application
`
`be amendedas follows:
`
`In The Specification:
`
`Please add the following new paragraph directly below the inventiontitle on page 1 of
`
`the specification as follows:
`
`This application claims the benefit of U.S. Provisional Application Ser. No. 60/429,641
`
`filed November 27, 2002, entitled “Dividing Work Among Multiple Graphics Pipelines Using a
`
`Super-Tiling Technique”, having as inventors Mark M.Leather and Eric Demers, and owned by
`
`instant assignee.
`
`CHICAGO/# 1083968. 1
`
`
`
`Ex. 8, p. 1
`
`Ex. 8, p. 1
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-8 Filed 12/19/22 Page 2 of 23
`onggems omy
`BY ott
`oe ay
`RB
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`REMARKS
`
`Applicants submit that the specification is fully supported by the original provisional
`
`application, and the claimsare fully supported by the originally filed provisional application.
`
`Respectfully submitted,
`
`By:
`
`ffay
`ec
`Chrisfopher J. Reckamp
`Reg. No. 34,414
`
`Dated: June 12, 2003
`
`Vedder, Price, Kaufman & Kammholz
`222 North LaSalle Street
`Chicago,Illinois 60601
`Telephone: (312) 609-7500
`Facsimile: (312) 609-5005
`
`CHICAGO/#1083968.1
`
`Ex. 8, p.2
`
`
`
`Ex. 8, p. 2
`
`

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`
`
`020053
`
`PATENT APPLICATION
`ATTY. DOCKET NO. 00100.02.0053
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`FILING OF A UNITED STATES PATENT APPLICATION
`
`DIVIDING WORK AMONG MULTIPLE GRAPHICSPIPELINES
`USING A SUPER-TILING TECHNIQUE
`
`INVENTORS:
`
`
`
`
`
`Eric Demers
`Mark M. Leather
`
`
`901 Sycamore Drive
`12187 Woodside Drive
`Palo Alto, California 94303
`
`Saratoga, California 95070
`
`
`
`ATTORNEY OF RECORD:
`CHRISTOPHERJ. RECKAMP
`REGISTRATIONNO.34,414
`VEDDER PRICE KAUFMAN & KAMMHOLZ
`222 NORTH LASALLE STREET,SUITE 2600
`CHICAGO,ILLINOIS 60601
`PHONE(312) 609-7500
`FAX (312) 609-5005
`
`Express Mail Label No.: EV 063310627 US
`Date of Deposit: June 12, 2003
`I hereby certify that this paper is being deposited with the
`U.S. Postal Service “Express Mail Post Office to
`Addressee” service under 37 C.F.R. Section 1.10 on the
`‘Date of Deposit’, indicated above, and is addressed
`to: Mail Stop Patent Application, Commissioner of Patents,
`P. O. Box 1450, Alexandria, VA, 22313-1450.
`
`Nameof Depositor: Winona K. Jackson
`
`Signature:
`
`
`
`Ex. 8, p. 3
`
`Ex. 8, p. 3
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-8 Filed 12/19/22 Page 4 of 23
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`eeeby Fil
`wal
`020053
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`DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING A
`SUPER-TILING TECHNIQUE
`
`RELATED CO-PENDING APPLICATION
`
`Thisis a related application to a co-pending applicationentitled “Parallel
`[0001]
`Pipeline Graphics System” having docket number 010025, having serial number
`, having Leatheret al. as the inventors, filed on even date,
`ownedby the sameassignee andhereby incorporated by referenceinits entirety.
`
`FIELD OF THE INVENTION
`
`Thepresent invention generally relates to graphics processingcircuitry
`[0001]
`and, moreparticularly, to dividing graphics processing operations among multiple
`
`pipelines.
`
`BACKGROUNDOF THE INVENTION
`
`Computer graphics systems, set top box systemsor other graphics
`[0002]
`processing systemstypically include a host processor, graphics (including video)
`processing circuitry, memory (e.g. frame buffer), and one or more display devices. The
`host processor may have a graphics application running thereon, which provides vertex
`data for a primitive(e.g. triangle) to be rendered on the one or more display devices to
`the graphics processing circuitry. The display device, for example, a CRT display
`includes a plurality of scan lines comprisedofa series of pixels. When appearance
`attributes (e.g. color, brightness, texture) are applied to the pixels, an object or scene is
`presented on the display device. The graphics processing circuitry receives the vertex
`data and generates pixel data including the appearanceattributes which may be presented
`on the display device according to a particular protocol. The pixel data is typically
`stored in the frame buffer in a mannerthat correspondsto the pixels location on the
`
`display device.
`FIG.1 illustrates a conventional display device 10, having a screen 12
`[0003]
`partitioned into a series of vertical strips 13-18. The strips 13-18 are typically 1-4 pixels
`in width. In like manner, the frame buffer of conventional graphics processing systemsis
`partitionedinto a series of vertical strips having the same screen space width.
`
`1
`
`
`
`Ex. 8, p. 4
`
`Ex. 8, p. 4
`
`

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`020053
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`Alternatively, the frame buffer and the display device may be partitioned into a series of
`horizontal strips. Graphics calculations, for example,lighting, color, texture and user
`viewing information are performedby the graphics processing circuitry on each ofthe
`primitives provided by the host. Onceall calculations have been performed onthe
`primitives, the pixel data representing the objcct to be displayed is written into the frame
`buffer. Once the graphicscalculations have been repeated forall primitives associated
`with a specific frame, the data stored in the frame buffer is rendered to create a video
`signal that is providedto the display device.
`[0004]
`The amount oftime taken for an entire frame of information to be
`calculated and providedto the frame buffer becomesa bottleneck in graphics systemsas
`the calculations associated with the graphics become more complicated. Contributing to
`the increased complexity of the graphics calculation is the increased needfor higher
`resolution video, as well as the need for more complicated video, such as 3-D video. The
`video image observed by the human eye becomesdistorted or choppy when the amount
`of time taken to render an entire frame of video exceeds the amountof time in which the
`
`display device must be refreshed with a new graphic or frame in order to avoid
`perception by the human eye. To decrease processing time, graphics processing systems
`typically divide primilive processing among several graphics processing circuits where,
`for example, one graphics processing circuit is responsible for one verticalstrip (e.g. 13)
`of the frame while another graphics processing circuit is responsible for another vertical
`strip (e.g. 14) of the frame. In this manner,the pixel data is provided to the frame buffer
`within the required refresh time.
`[0005]
`Load balancing is a significant drawback associated with the partitioning
`systems as described above. Load balancing problems occur, for example, whenall of
`the primitives 20-23 ofa particular object or scene are located in onestrip (e.g.strip 13)
`as illustrated in FIG. 1. When this occurs, only the graphics processing circuit
`responsiblestrip 13 is actively processing primitives; the remaining graphics processing
`circuits are idle. This results in a significant waste of computing resources as at most
`only half of the graphics processing circuits are operating. Consequently, graphics
`processing system performanceis decreased as the system is only opcrating at a
`
`maximum offifty percent capacity.
`
`
`
`Ex. 8, p.5
`
`Ex. 8, p. 5
`
`

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`020053
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`Changing the width ofthe strips has been employed to counter the system
`[0006]
`performance problems. However, when the width ofa strip is increased, the load
`balancing problem is enhanced as more primitives are located within a singlestrip;
`thereby, increasing the processing required of the graphics processing circuit responsible
`for that strip, while the remaining graphics processing circuits remain idle. Whenthe
`width ofthe strip is decreased (e.g. four bits to two bits), cache (e.g. texture cache)
`efficiency is decreased as the number of cachelines employedin transferring data is
`reduced in proportion to the decreased widthof the strip. In either case, graphics
`processing system performanceisstill decreased dueto the idle graphics processing
`
`circuits.
`
`Frame based subdivision has been used to overcomethe performance
`[0007]
`problems associated with conventional partitioning systems. In frame based subdivision,
`each graphics processoris responsible for processing an entire frame, not strips within the
`same frame. The graphics processorsthen alternate frames. However, frame subdivision
`introduces one or more framesof latency between the user and the screen, whichis
`unacceptablein real-time interactive environments, for example, providing graphics for a
`flight simulator application.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Thepresent invention and the related advantages andbenefits provided
`[0008]
`thereby, will be best appreciated and understood upon reviewofthe following detailed
`description of a preferred embodiment, taken in conjunction with the following drawings,
`where like numerals represent like elements, in which:
`[0009]
`FIG. 1 is a schematic block diagram of a conventionaldisplay partitioned
`
`into several vertical strips:
`[0010]
`FIG. 2 is a schematic block diagram of a graphics processing system
`employing an exemplary multi-pipeline graphics processing circuit according to one
`embodimentof the present invention;
`(0011)
`FIG.3 is a schematic block diagram of a memory partitioned into an
`exemplary super-tile pattern according to the present invention;
`
`
`
`Ex. 8, p. 6
`
`Ex. 8, p. 6
`
`

`

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`
`
`[0012]
`
`FIG.4 is a schematic block diagram of a memory partitioned into a super-
`
`tile pattern according to an alternate embodimentof the present invention;
`
`[0013]
`
`FIG. 5 is a schematic block diagram of an exemplary multi-pipcline
`
`graphics processingcircuit used in a multi processor configuration according to an
`
`alternate embodimentof the present invention;
`
`FIG.6 is a flow chart of the operations performed by the graphics
`{0014]
`processing circuit according to the present invention;
`)
`[0015]
`FIG.7 is a diagram illustrating a polygon bounding box to determine
`
`which,if a polygonfits in a tile or super tile; and
`
`{0016}
`
`FIG.8 is a schematic block diagram of an exemplary multi-pipcline
`
`graphics processingcircuit used in a multi processor configuration according to an
`
`alternate embodimentof the present invention.
`
`
`
`Ex. 8, p. 7
`
`Ex. 8, p. 7
`
`

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`
`she DBBo af
`020053
`
`DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
`
`A multi-pipeline graphics processing circuit includesat least two pipelines
`[0017]
`operative to process data in a correspondingtile of a repeatingtile pattern, a respective
`oneofthe at least two pipelines is operative to process data in a dedicated tile, wherein
`the repeating tile pattern includes a horizontally and vertically repeating pattern of square
`regions. The multi-pipeline graphics processing circuit may be coupledto a frame buffer
`that is subdivided into a replicating pattern of square regions(e.g.tiles), where each
`region is processed by a corresponding one of the at least two pipelines such that load
`
`balancing and texture cacheutilization is enhanced.
`[0018]
`A multi-pipeline graphics processing method includes receiving vertex
`data for a primitive to be rendered, generating pixel data in responseto the vertex data,
`determining the pixels withinaset oftiles of a repeating tile pattern to be processed bya
`correspondingoneofat least two graphics pipelines in response to the pixel data, the
`repeatingtile pattern including a horizontally and vertically repeating pattern of square
`regions, and performingpixel operations on the pixels within the determinedset oftiles
`by the corresponding oneofthe at least two graphics pipelines. An exemplary
`embodimentof the present invention will now be described with reference to Figures 2-6.
`[0019]
`FIG. 2 is a schematic block diagram of an exemplary graphics processing
`system 30 employing an example of a multi-pipeline graphics processing circuit 34
`according to one embodimentofthe present invention. The graphics processing system
`30 can be implemented with a single graphics processing circuit 34 or with two or more
`graphics processing circuits 34, 54. The components and corresponding functionality of
`the graphics processing circuits 34, 54 are substantially the same. Therefore, only the
`structure and operation of graphics processingcircuit 34 will be describedin detail. An
`alternate embodiment, employing both graphics processingcircuits 34 and 54 will be
`
`discussed in greater detail below with reference to FIGS. 4-5.
`[0020]
`Graphicsdata 31, for example, vertex data of a primitive (e.g. triangle) 80
`(FIG.3) is transmitted asa series ofstrips to the graphics processing circuit 34. As used
`herein, graphics data 31 can also include video data or a combination ofvideo data and
`graphics data. The graphicsprocessing circuit 34 is preferably a portion of a stand-alone
`graphics processorchip or may also be integrated with a host processor or other circuit, if
`
`
`
`Ex. 8, p. 8
`
`Ex. 8, p. 8
`
`

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`020053
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`desired, or part of a larger system. The graphics data 31 is provided by a host (not
`
`shown). The host may be a system processor (not shown) or a graphics application
`
`running on the system processor. In an alternate embodiment, an Accelerated Graphics
`Port (AGP) 32 or other suitable port receives the graphics data 31 from thehost and
`provides the graphics data 31 to the graphics processing circuit 34 for further processing.
`
`[0021] ‘The graphics processing circuit 34 includesafirst graphics pipeline 101
`
`operative to process graphics data inafirst set of tiles as discussed in greaterdetail
`
`below. Thefirst pipeline 101 includes front end circuitry 35, a scan converter 37, and
`
`back endcircuitry 39. The graphics processing circuit 34 also includes a second graphics
`
`pipeline 102, operative to process graphics data in a secondset of tiles as discussed in
`
`greater detail below. The first graphics pipeline 101 and the second graphics pipeline
`
`102 operate independently of one another. The second graphics pipeline 102 includes the
`
`front end circuitry 35, a scan converter 40, and back end circuitry 42. Thus, the graphics
`
`processing circuit 34 of the present invention is configured as a multi-pipeline circuit,
`
`where the back endcircuitry 39 of the first graphics pipeline 101 and the back end
`
`circuitry 42 of the second graphics pipeline 102 share the front end circuitry 35, in that
`
`the first and second graphics pipelines 101 and 102 receive the same pixel data 36
`
`provided by the front end circuitry 35. Alternatively, the back end circuitry 39 ofthefirst
`
`graphics pipeline 101 and the back end circuitry 42 of the second pipeline 102 may be
`
`coupled to separate front end circuits. Additionally, it will be appreciated that a single
`
`graphics processing circuit can be configured in similar fashion to include more than two
`
`graphics pipelines. Theillustrated graphics processing circuit 34 has thefirst and,second
`
`pipelines 101-102 present on the same chip. However, in alternate embodiments, thefirst
`
`and second graphics pipelines 101-102 may be present on multiple chips interconnected
`
`by suitable communication circuitry or a communication path, for example, a
`
`synchronization signal or data bus interconnecting the respective memory controllers.
`
`[0022]
`
`The front end circuitry 35 may include, for example, a vertex shader, set
`
`up circuitry, rasterizer or other suitable circuitry operative to receive the primitive data 31
`
`and generate pixel data 36 to be further processed by the back endcircuitry 39 and 42,
`
`respectively. The front end circuitry 35 generates the pixel data 36 by performing, for
`
`example,clipping, lighting, spatial transformations, matrix operations and rasterizing
`
`
`
`Ex. 8, p. 9
`
`Ex. 8, p. 9
`
`

`

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`\
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`
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`operations on the primitive data 31. The pixel data 36 is then transmitted to the
`
`respective scan converters 37 and 40of the two graphics pipelines 101-102.
`
`[0023]
`
`The scan converter 37 ofthe first graphics pipeline 101 receives the pixel
`
`data 36 and sequentially provides the position (e.g. x, y) coordinates 60 in screen space of
`the pixels to be processed by the back end circuitry 39 by determining or identifying
`those pixels of the primitive, for example, the pixels within portions 81-82 of the triangle
`
`80 (FIG.3) that intersect the tile or set of tiles that the back end circuitry 39 is
`
`responsible for processing. The particular tile(s) that the back end circuitry 39 is
`responsible for is determined based onthetile identification data present on the pixel
`identification line 38 of the scan converter 37. The pixel identification line 38 is
`
`illustrated as being hard wired to ground. Thus,the tile identification data corresponds to
`
`a logical zero. This correspondsto the back endcircuitry 39 being responsible for
`
`processingthetiles labeled “A”(e.g. 72 and 75) in FIG. 3. Although the pixel
`
`identification line 38 is illustrated as being hard wiredto a fixed value,it is to be
`
`understood and appreciatedthat the tile identification data can be programmable data,for
`
`example, from a suitable driver and such a configuration is contemplated by the present
`
`invention and is within the spirit and scopeofthe instant disclosure.
`
`[0024]
`
`Back endcircuitry 39 may include, for example, pixel shaders, blending
`
`circuits, z-buffers or any othercircuitry for performing pixel appearance attribute
`
`operations (e.g. color, texture blending, z-buffering) on those pixels located, for example,
`
`in tiles 72, 75 (FIG. 3) corresponding to the position coordinates 60 provided by the scan
`
`converter 37. The processed pixel data 43 is then transmitted to graphics memory 48 via
`memory controller 46 for storage therein at locations corresponding to the position
`coordinates 60.
`
`[0025]
`
`The scan converter 40 of the second graphics pipeline 102, receives the
`
`pixel data 36 and sequentially provides position (e.g. x, y) coordinates 61 in screen space
`of the pixels to be processed by the back endcircuitry 42 by determining those pixels of
`the primitive, for example,the pixels within portions 83-84 ofthe triangle 80 (FIG.3)
`that intersect the tiles that the back end circuitry 42 is responsible for processing. Back
`
`end circuitry 42 tile responsibility is determined basedon thetile identification data
`
`present on the pixel identification line 41 of the scan converter 41. The pixel
`
`
`
`Ex. 8, p. 10
`
`Ex. 8, p. 10
`
`

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`020053
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`identification line 41 is illustrated as being hard wired to Vcc; thus, the tile identification
`
`data correspondsto a logical one. This correspondsto the back end circuitry 42 being
`responsible for processing thetiles labeled “B”(e.g. 73-74) in FIG. 3. Although thepixel
`identification line 41 is illustrated as being hard wired to a fixed value,it is to be
`understood and appreciated that the tile identification data can be programmable data, for
`example, from a suitable driver and such configuration is contemplated by the present
`
`invention and is within the spirit and scope of the instant disclosure.
`[0026}
`Back endcircuitry 42 mayinclude, for example, pixel shaders, blending
`circuits, z-buffers or any suitable circuitry for performing pixel appearanceattribute
`operations on those pixels located, for example,in tiles 73 and 74 (FIG. 3) corresponding
`to the position coordinates 61 provided by the scan converter 40. ‘he processed pixel
`data 44 is then transmitted to the graphics memory 48, via memory controller 46, for
`
`storage therein at locations corresponding to the position coordinates 61.
`[0027]
`The memory controller 46 is operative to transmit and receive the
`processed pixel data 43-44 from the back endcircuitry 39 and 42; transmit and retrieve
`pixel data 49 from the graphics memory 48; and in a single circuit implementation,
`transmit pixel data 50 for presentation on a suitable display 51. The display 51 may be a
`monitor, a CRT, a high definition television (HDTV)or any other device or combination
`
`thereof.
`
`Graphics memory 48 mayinclude, for example, a frame buffer that also
`[0023]
`stores one or more texture maps. Referring to FIG.3, the frame buffer portion of the
`graphics memory 48 is partitioned in a repeatingtile pattern of horizontal and vertical
`square regionsortiles 72-75, where the regions 72-75 provide a two dimensional
`partitioning of the framebuffer portion of the memory 48. Eachtile is implemented as a
`16 x 16 pixel array. The repeatingtile pattern of the frame buffer 48 correspondsto the
`partitioning of the corresponding display 51 (FIG. 2). When rendering a primitive(e.g.
`triangle) 80, the first graphics pipeline 101 processes only those pixels in portions 81, 82
`of the primitive 80 that intersects tiles labeled “A”, for example, 72 and 75, as the back
`end circuitry 39 is responsible for the processing oftiles correspondingtotile
`identification 0 present on pixelidentification line 38 (FIG. 2). In corresponding fashion,
`the secondgraphics pipeline 102 processes only those pixels in portions 83, 84 ofthe
`
`
`
`Ex. 8, p. 11
`
`Ex. 8, p. 11
`
`

`

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`
`
`primitive 80 thatintersects tiles labeled “B”, for example 73-74,as the back end circuitry
`42 (FIG.2) is responsible for the processingoftiles correspondingtotile identification |
`
`present on pixel identification line 41 (FIG. 2).
`
`[0029]
`By configuring the frame buffer 48 according to the present invention,as
`the primitive data 31 is typically written instrips, the tiles (e.g. 72 and 75) being
`processed by the first graphics pipeline 101 and the tiles (e.g. 73 and 74) being processed
`
`by the second graphics pipeline 102 will be substantially equal in size, notwithstanding
`the primitive 80 orientation. Thus, the amount ofprocessing performed by the first
`graphics pipeline 101 and the second graphics pipeline 102, respectively, are
`substantially equal; thereby, effectively eliminating the load balance problems exhibited
`
`by conventional techniques.
`
`[0030]
`
`FIG.4 is a schematic block diagram of a frame buffer 68 partitioned into a
`
`super-tile pattern according to an alternate embodimentof the present invention. Sucha
`
`partitioning would be used, for example, in conjunction with a multi-processor
`
`implementation to be discussed below with reference to FIG. 5. Asillustrated, the frame
`buffer 68 is partitioned into a repeatingtile pattern where thetiles, for example, 92-99
`
`that form the repeatingtile pattern are the responsibility of and processed by a
`
`corresponding one of the graphics pipelines provided by the multi-processor
`
`implementation.
`
`[0031]
`FIG. 5 is a schematic block diagram of a graphics processing circuit 54
`which may be coupled with the graphics processing circuit 34 (FIG. 2), for example, by
`the AGP 32 orothersuitable port, to form one embodiment of a multi-processor
`
`implementation. The graphics processing circuit 54 is preferably a portion of a stand-
`alone graphics processor chip or may also be integrated with a host processor or other
`circuit, if desired, or port of a larger system. The multi-processor implementation
`exhibits an increasedfill rate of, for example, 9.6 billion pixels/sec with a triangle rate of
`
`300 million triangles/sec. This represents a tremendous performanceincrease as
`compared to conventional graphics processing systems. The triangle rate is defined as
`the numberoftriangles the graphics processing circuit can generate per second. Thefill
`rate is defined as the numberofpixels the graphics processing circuit can render per
`
`second.
`
`
`
`Ex. 8, p. 12
`
`Ex. 8, p. 12
`
`

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`020053
`
`Referring briefly to FIG. 2, in the multi-processor implementation,
`[0032]
`processed pixel data 52 from the graphics processing circuit 34 is provided asa first of
`twoinputs to a high speed switch 70. The second input to the high speed switch 70 is the
`processedpixel data 55 from the graphics processing circuit 54. The high speed switch
`70 has a switching frequency(f) sufficient to provide the pixel information 71 to a
`suitable display device without any detectable latency.
`[0033]
`Returning to FIG.5, the graphics processingcircuit 54 includes a third
`graphics pipeline 201 operative to process graphics data in a third set oftiles. The third
`graphics pipeline 201 includes front end circuitry 135, which maybethe front end
`circuitry 35 discussed with reference to FIG. 2, a scan converter 137 and back end
`circuitry 139. The graphics processing circuit 54 also includes a fourth graphics pipeline
`202, operative to process graphics data in a fourth setoftiles. Thefourth graphics
`pipeline 202 includes the front end circuitry 135, a scan converter 140 and back end
`circuitry 142. The third graphics pipeline 201 and the fourth graphics pipeline 202 also
`operate independently of one another. Thus, the graphics processing circuit 54 is
`configured as a multi-pipeline circuit, where the back end circuitry 139 ofthe third
`graphics pipeline 201 and the back end circuitry 142 of the fourth graphicspipeline 202
`share the front end circuitry 135, in that the respective back endcircuitry 139 and 142
`receives the samepixel data from thefront end circuitry 135. Asillustrated, the
`components ofthe third and fourth graphics pipclines are present on a single chip.
`Additionally, the back end circuitry 139 and the back endcircuitry 142 may be
`configured to share the front end circuitry 35 of the graphics processing circuit 34.
`Alternatively, the third and fourth graphics pipelines may be configured to be on multiple
`chips interconnected by a communication path, for example, a synchronization signal or
`
`data bus.
`Thefront end circuitry 135 may include, for example, a vertex shader,set
`[0034]
`up circuitry, rasterizer or other suitable circuitry operative to receive the primitive data 31
`from the AGP 32 andgenerate pixel data 136 to be processed bythe third graphics
`pipeline 201 and fourth graphicspipeline 202, respectively. The front end circuitry 135
`generatesthe pixel data 136 by performing, for example, clipping,lighting, spatial
`transformations, matrix operations, rasterization or any suitable primitive operations or
`
`10
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`Ex. 8, p. 13
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`Ex. 8, p. 13
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`020053
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`combination thereof on the primitive data 31. The pixel data 136 is then transmitted to
`the respective scan converters 137 and 140ofthe two graphics pipelines 201-202.
`[0035]
`The scan converter 137 ofthe third graphics pipeline 201 receives the
`pixel data 136 and sequentially provides the position(e.g. x, y) coordinates 160 in screen
`space ofthe pixels to be processed by the back endcircuitry 139, based onthetile
`identification data present on pixelidentification line 138. In corresponding fashion, scan
`converter 140 of the fourth graphics pipeline 202 receives the pixel data 136 and
`sequentially provides the position (e.g. x, y) coordinates 161 in screen space of the pixels
`to be processedby the back end circuitry 143, based onthetile identification data present
`
`on pixel identification line 141.
`
`[0036] Referring to FIG.4, in the multi-processor implementation, whenalogical
`zero or other suitable value is present on pixel identification line 138 (e.g. corresponding
`to the pixel identification line 138 being tied to ground), the back endcircuitry 139 is
`responsible for processing, for example,tiles labeled “AO” (e.g. 92 and 95). In
`corresponding manner, whena logical one or other suitable value is present on pixel
`identification line 141 (e.g. corresponding to pixel identification line 142 beingtied to
`Vcc), the back end circuitry 142 will be responsible for processingthetiles labeled “BO”
`(e.g. 93 and 94). Whena logicalzero or other suitable value is present on pixel
`identification line 38 (FIG. 2), the back endcircuitry 39 is responsible for processing, for
`example, the tiles labeled “A1”(c.g. 96 and 99). Whenalogical one or othersuitable
`value is present on pixel identification line 41 (FIG. 2), the back end circuitry 42 is
`responsible for processing, for example,thetiles labeled “B1” (e.g. 97 and 98). Thetile
`pattern illustrated in FIG.4 is referred to as a super-tile pattern 68.
`[0037]
`Asillustrated, the super-tile pattern 68 is formed of a horizontally and
`vertically repeating pattern of regionsor tiles 92-99, where eachtile is a 16 x 16 pixel
`array. With this frame buffer configuration,as the primitive data 31 is typically written
`in strips, at least onetile (e.g. 92) being processedbythe third graphics pipeline 201 and
`at least onetile (e.g. 93) being processed by the fourth graphics pipeline 202 will be
`intersected or contain at least a portion ofthe primitive data 31, notwithstanding the
`primitive orientation; thereby achieving substantially equal load balancing between the
`pipelines.
`
`11
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`Ex. 8, p.14
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`Ex. 8, p. 14
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`Case 6:22-cv-00466-ADA-DTG Document 50-8 Filed 12/19/22 Page 15 of 23
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`Thus, in the multi-processor implementation, each of the graphics
`[0033]
`pipelines is responsible for processing 1/(MxN)ofthetiles presentin the partitioned
`graphics memory 68, where M represents the number ofpipelines per circuit and N
`represents the numberofgraphics processing circuits being used. Thus, in an
`embodiment where graphicsprocessing circuit 34 and graphics processing circuit 54 are
`combined, for example, through AGP 32 (FIG.2), each graphicspipeline 101, 102, 201
`and 202 will be responsible for processing one-fourth of the tiles 92-99 ofthe repeating
`tile pattern. This results in increased graphics processing performance aseach graphics
`pipeline is responsible for processing one-quarter of total pixels maintainedin the frame
`
`buffer 68.
`
`FIG.6 is a flow chart of the operations performed by the graphics
`[0039]
`processing circuit 34 according to the present invention.
`In the multi-processor
`implementation, graphics processing circuits 34 and 54 perform substantially the same
`operations. In step 100, the front end circuitry 35 receives the graphics data 31 (FIG.2),
`for example, vertex data of an object to be rendered and generates corresponding pixel
`data 36 (FIG. 2) in response to the primitive data 31 in step 102. The pixel data may be
`generated by performing, for example, clipping, lighting, spatial transformations. matrix
`transformations and rasterizing operations on the graphicsdata 31.
`[0040]
`In step 104, the pixels within a setof tiles of the repeating tile pattern to be
`processed by a correspondingoneofthe at least two graphicspipelines in res