`
`(12) United States Patent
`Wang et al.
`
`USOO6184906B1
`(10) Patent No.:
`US 6,184,906 B1
`(45) Date of Patent:
`Feb. 6, 2001
`
`(54)
`
`(75)
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`(73)
`(*)
`
`(21)
`(22)
`(51)
`(52)
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`(58)
`
`MULTIPLE PIPELINE MEMORY
`CONTROLLER FOR SERVICING REAL
`TIME DATA
`
`Inventors: Chun Wang, Toronto; Raymond Li,
`Markham; Adrian Hartog, Toronto;
`Daniel Gudmundson, Newmarket, all
`of (CA)
`Assignee: ATI Technologies, Inc., Thornhill (CA)
`Notice:
`Under 35 U.S.C. 154(b), the term of this
`patent shall be extended for 0 days.
`
`Appl. No.: 08/885,335
`Filed:
`Jun. 30, 1997
`Int. Cl. ............................................... G06F 13/16
`U.S. Cl. .......................... 345/521; 34.5/506; 711/151;
`711/158
`Field of Search ..................................... 34.5/521, 506,
`34.5/512, 302; 711/147, 151,158, 169;
`395/729, 731, 732; 710/241, 243, 244
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`7/1997 Allen .................................... 711/151
`5,649,206
`5,752,010 * 5/1998 Herbert ...
`... 34.5/521
`5,822,758 * 10/1998 Loper et al. ......................... 711/151
`* cited by examiner
`Primary Examiner Raymond J. Bayerl
`Assistant Examiner Sy D. Lulu
`(74) Attorney, Agent, or Firm- Markison & Reckamp, P.C.
`(57)
`ABSTRACT
`A multiple pipeline memory controller has a plurality of two
`Stage pipeline processors dedicated to Separately process
`real time Video capture and display refresh input request
`Signals. A separate pipeline processor processes non-real
`time input Signals. The multiple pipeline design reduces
`memory access latency and improves throughput of data in
`display FIFO memory to effect improved resolution. The
`multiple pipeline memory controller can be integrated in a
`video graphics controller (VGC).
`21 Claims, 4 Drawing Sheets
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`32
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`26
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`52
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`W .
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`VIDEO
`OVERLAY
`
`GU
`ENGINE
`2D & 3D
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`51
`N)
`
`50
`
`SCREEN
`
`VIDEO SOURCE
`
`WDEO
`CAPTURE
`CONTROLLER
`
`MULT-PPELINE
`MEMORY
`CONTROLLER
`
`
`
`
`
`MEMORY INTERFACE
`
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`MEMORIES
`(FRAME BUFFER)
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`60
`
`Ex. 6, p. 1
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`U.S. Patent
`
`Feb. 6, 2001
`
`Sheet 1 of 4
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`US 6,184,906 B1
`
`VIDEO
`CAPTURE
`HOST DISPLAY
`24
`22
`
`20
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`18
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`10 N
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`n
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`12
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`14
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`16
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`STAGE 1
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`STAGE 2
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`STAGE 3
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`ARBITOR
`
`BEST 1 CYCLEf WORST
`7 CYCLES
`
`ADDRESS
`DETERMINATOR
`(RAS CAS)
`
`BEST 1 CYCLE/ WORST
`7 CYCLES
`
`OUTPUT
`
`BEST 1 CYCLE/WORST
`7 CYCLES
`
`TO MEMORY
`
`F.G. 1
`PRIOR ART
`
`Ex. 6, p. 2
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`Case 6:22-cv-00466-ADA-DTG Document 50-6 Filed 12/19/22 Page 3 of 9
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`U.S. Patent
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`US 6,184,906 B1
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`Ex. 6, p. 3
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`Case 6:22-cv-00466-ADA-DTG Document 50-6 Filed 12/19/22 Page 4 of 9
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`U.S. Patent
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`Feb. 6, 2001
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`Sheet 3 of 4
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`US 6,184,906 B1
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`Case 6:22-cv-00466-ADA-DTG Document 50-6 Filed 12/19/22 Page 5 of 9
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`U.S. Patent
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`Feb. 6, 2001
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`Sheet 4 of 4
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`US 6,184,906 B1
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`Case 6:22-cv-00466-ADA-DTG Document 50-6 Filed 12/19/22 Page 6 of 9
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`US 6,184,906 B1
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`1
`MULTIPLE PIPELINE MEMORY
`CONTROLLER FOR SERVICING REAL
`TIME DATA
`
`The invention relates generally to memory controllers for
`Servicing real time data and more particularly to memory
`controllers for use in Video graphic control cards or tele
`communication units that require real time data capture and
`processing.
`BACKGROUND OF THE INVENTION
`Video graphics controllers (VGC's) are continually being
`required to manage and control more complex and addi
`tional information for display on computer Screens. The type
`of additional bandwidth of information can significantly
`reduce image resolution due to the inability of the VGC to
`obtain and route the information in a high Speed and efficient
`manner. The problem is compounded when computers, in
`Some cases, are also required to Service both computer
`graphics information and television Signaling information,
`Such as in the case when the computer is required to display
`Video signals.
`Real time video information Such as Video signals from a
`cable television (CATV) broadcaster must be captured in
`real time or the information is lost. When a live television
`show is being Sent to the computer, the VGC must capture
`and display the Video in real time while also displaying
`overlaid graphics and Servicing other requests from the
`central processing unit relating to other graphic display
`requirements Such as the displaying of text. VGC's typically
`generate real time signal requests to Store the incoming real
`time video image and data information in frame buffer
`memory Such as
`Also, the display Screen must be refreshed constantly to
`avoid flickering and other problems that limit resolution.
`Since the frame buffer memories are accessed through the
`Same memory interface, a read/write request for graphics
`information competes with a read/write request for capturing
`the real time video information. When these requests occur
`at the same time, one of the real time requests must wait to
`be serviced. This can result in a loSS of data or an unac
`ceptable slow down in processing.
`These problems become compounded where the display
`Screens are higher resolution displays and when other
`graphic information Such as graphical user interfaces and
`other graphics are overlaid with the Video image information
`and the information is requested to be displayed at the same
`time. The more the VGC has to Switch between the real time
`requests, the lower the resolution quality and the lower the
`System performance.
`To help alleviate Some of these problems, memory con
`trollers in VGCS have employed a single multi-stage pipe
`line processing approach. Such memory controllers achieve
`relatively high Speeds and allow for a single memory clock
`cycle read/write operation. However, these memory control
`lers typically have memory access latencies that can dra
`matically degrade the performance of real time requesters in
`the VGCS. Extrinsic memory access latencies in Such
`VGC's can be a large number greater than 10 clock cycles
`and can be 21 clock cycles. With the increasing real time
`requirements and additional non-real time requirements,
`these memory controllers with a great number of memory
`access latencies can not offer the high Speed and high
`performance control necessary to adequately accommodate
`the increasing real time processing demands and complexity.
`Consequently, there exists a need for a memory controller
`for Servicing real time data that can more effectively accom
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`modate multiple real time memory requests. It would also be
`advantageous to have an integrated VGC chip that includes
`a memory controller that has improved memory access
`latency for handling both real time Video capture requests
`and real time display requests while also effectively accom
`modating non-real time requests. It would also be advanta
`geous if the memory controller allowed for use of the same
`size CRT controller FIFO to help reduce costs of the VGC..
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The features of the present invention together with the
`advantages thereof, may be understood by reference to the
`following description taken in conjunction with the accom
`panying drawings wherein:
`FIG. 1 is a block diagram generally depicting a prior art
`Single pipeline processing System used in a memory con
`troller;
`FIG. 2 is block diagram generally depicting one embodi
`ment of a VGC chip incorporating a multiple pipeline
`memory controller in accordance with the invention;
`FIG. 3 is a block diagram generally depicting one embodi
`ment of a multiple pipeline memory controller in accordance
`with the invention; and
`FIG. 4 is a block diagram generally depicting another
`embodiment of a multiple pipeline memory controller in
`accordance with the invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 shows a block diagram of an example of a single
`pipeline processing System 10 having three stages that are
`used in conventional memory controllers for VGC's. The
`first Stage is an arbitration Stage 12 having an arbitor. The
`Second Stage is an addressing unit or address determination
`Stage 14, Such as a RAS CAS separation (row access and
`column access) stage. The third stage is a conventional
`output Stage 16. The arbitration Stage 12 receives multiple
`input request signals generally shown as 18. Two of the input
`request signals are real time request Signals. These are the
`Video capture request Signal 20 and a display refresh request
`Signal 22. Some of the input signals are non-real time
`Signals. One non-real time request signal 24, may be a host
`request Such as a peripheral component interconnect (PCI)
`request to write text to the display. Other non-real time input
`Signals (not shown) are also input into the arbitration stage
`12.
`The arbitration Stage 12 is a well known Stage containing
`an arbitor with priority Selection logic and multiplexing
`logic. The arbitor processes one of the input request signals
`20–24 in one memory clock cycle. Once Selected, the input
`Signal is passed to the address determination Stage 14 where
`the row and column address of memory is determined along
`with the data to be written or read. The address and data are
`then passed to the output stage where the memory access
`timing cycles are generated and data are output to memory.
`In the case of a page fault, a memory access takes Seven
`clock cycles to complete. In a pipeline process, a new
`request for data to the pipeline processing System 10 from a
`requester, Such as a video capture controller, has to wait for
`a previous request to be fully processed through the pipeline
`before it has access to memory. The whole pipeline Stalls for
`Seven cycles when a page fault occurs, because the output
`Stage must wait the Seven cycles before outputting the
`address and data information. If every request in the pipeline
`has a page fault, the whole pipeline can Stall for a maximum
`
`Ex. 6, p. 6
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`3
`of twenty-one cycles before a new request to the pipeline
`processing System 10 can access memory. This results in an
`extrinsic memory access latency period of twenty-one
`cycles. In other words, a worst case condition assumes each
`access request has a page fault with respect to one another.
`With Such Systems, the total memory access latency
`period can be 28 memory clock cycles. The total memory
`access latency period includes an extrinsic latency period of
`twenty-one memory clock cycles (maximum) resulting from
`clearing all of the pipeline Stages. The total memory acceSS
`latency period also includes an intrinsic latency period of
`Seven memory clock cycles (maximum).
`Although conventional memory controllers can accom
`modate multiple real time signals and multiple non-real time
`Signals, a real time request Signal may be prevented from
`being processed for a maximum of twenty eight clock
`cycles. With real time video information, this delay can be
`too long and data can be lost. Although each real time
`requestor usually has Some FIFO memory associated with it,
`and the FIFO memory can relieve Some pressure on the
`latency problem, additional FIFO memory is costly and
`integrated circuit real estate is at a premium.
`Referring to FIG. 2, there is generally shown an embodi
`ment of an improved VGC 26 with a multiple pipeline
`memory controller 28 in accordance with one embodiment
`of the invention. The VGC 26 may be an integrated circuit
`on a graphics card for insertion into a slot in a personal
`computer. It will be recognized that although the invention
`will be described for use in a VGC, it is contemplated that
`the invention may used in other Suitable applications. The
`VGC 26 includes a host bus interface unit (HBIU) 30 as
`known in the art, coupled to a CPU 32, such as an Intel
`Pentium type processor, through PCI bus 34. The HBIU 30
`communicates non-real time host input request Signal 24,
`Such as display text requests, to the multiple pipeline
`memory controller 28.
`The VGC 26 also has a video capture controller 38 as
`known in the art, that receives Video information from a
`video source 40 through video bus 42. The video source 40
`may be a CATV signal. The video capture controller 38
`generates real time Video capture input request Signals 20 for
`processing by the multiple pipeline memory controller 28. A
`CRT controller 46 generates a real time display refresh input
`request signal 22 and outputs the received display data on
`screen 50 through display bus 51. A video overlay engine 52
`generates a non-real time input request Signal 54 to the
`multiple pipeline memory controller 28 to request Video
`information to overlay on graphics on the screen 50. The
`Video overlay engine 52 Scales a Video image that is dis
`played and overlaid on graphics. In this way, movies or
`television programs can be viewed simultaneously with
`computer graphics.
`Another non-real time input signal 56 is generated by a
`GUI engine 58. The multiple pipeline memory controller 28
`receives the real time and non-real input signals and
`accesses memories 60 (frame buffer) containing graphic and
`Video image data through a shared memory interface buS 62.
`FIG. 3 shows a more detailed view of an embodiment of
`the multiple pipeline memory controller 28. Generally
`Stated, the multiple pipeline memory controller 28 for Ser
`vicing real time data has a plurality of dual Stage pipeline
`processors as generally indicated. An input port 64 receives
`a real time input Signal, Such as Video capture signal 20 or
`display refresh Signal 22, in a pipeline fashion. AS used
`herein, an input Signal whether a real time or non-real time
`Signal, may be a request Signal with data, control informa
`
`4
`tion and address information or any combination thereof or
`Singular component. Another input port 66 receives a non
`real time input Signal, Such as a PCI request Signal 24 or a
`Video overlay request Signal 54, also in a pipeline fashion.
`One of the dual Stage pipeline processors 68 receives a
`Single real time input signal through the input port 64. The
`dual Stage pipeline processor 68 Separately processes the
`real time input Signal in a pipeline fashion and is dedicated
`to the real time input signal. Like the dual Stage pipeline
`processor 68, the other dual Stage pipeline processor 70
`receives the non-real time input Signal through correspond
`ing input port 66. The dual Stage pipeline processor 70 also
`Separately processes the non-real time input Signal in a
`pipeline fashion.
`A first Stage of the dual Stage pipeline processor 68 has
`first Stage addressing logic with memory row/column
`address determination logic (R/C ADL) and memory page
`fault detection logic referred to as an addressing unit 72. AS
`used herein, each memory row is a page. The addressing unit
`72 is Substantially the same as the addressing unit of the
`determinator stage 14 (FIG. 1), namely RAS CAS with fault
`detection provision. Similarly, the dual Stage pipeline pro
`cessing Stage 70 has a first stage of addressing logic with
`memory row/column address determination logic (R/C
`ADL) and memory page fault detection logic referred to as
`addressing unit 74. The addressing unit 74 is the same as the
`addressing unit 72.
`The Second Stage of the dual pipeline processors 68 and
`70 is an output Stage and has priority based arbitration logic
`76 for selectively determining which of the real time and
`non-real time input Signals output from each of the respec
`tive addressing unit 74 and the addressing unit 72 is to be
`output to memory 60 through an output port 78. Preferably,
`the arbitration logic 76 is common to both pipeline proces
`Sors 68 and 70.
`The arbitration logic 76 is substantially similar to the
`arbitor 12 of FIG.1. The arbitration logic 76 has a memory
`clock cycle generator 80 for generating clock cycles to be
`used for accessing memories 60 and for timing of the
`arbitration control logic 82.
`The arbitration control logic 82 receives control Signal
`information output from each of the respective addressing
`unit 74 and the addressing unit 72. Data and address
`information from the addressing unit 74 and the addressing
`unit 72 is received by a multiplexer (MUX) 84 and serve as
`inputs to the MUX84. The data and address information is
`multiplexed as output to the memory 60 through output port
`78. The arbitration control logic 82 controls the MUX84 by
`control Signal 86 to output the higher priority signal between
`either the addressing unit 72 and the addressing unit 74. The
`real time request Signal processed by the addressing unit 72
`is given priority over the processed non-real time request
`Signal from addressing unit 74 to avoid loSS of real time
`information. Therefore a conflict between a read/write
`request between a real time request and a non-real time
`request will be resolved in favor of the real time request.
`FIG. 4 shows a preferred embodiment of a multiple
`pipeline memory controller 88 having three pipeline pro
`cessors 90, 92 and 94 for separately processing a number of
`input Signals. Each real time input signal is Sent through a
`dedicated dual stage pipeline processor 90 and 92 that
`Separately processes a Single real time input signal to effect
`rapid processing of real time request Signals. All non-real
`time input Signals are passed through a three Stage pipeline
`processor 94 having dual arbitration logic by virtue of
`priority arbitor 96 and common arbitor 98.
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`S
`A real time Video capture request input Signal 20 is
`received by the multiple pipeline memory controller 88
`through a dedicated input port 100 in a pipeline fashion. The
`pipeline processor 90 receives the real time Video capture
`request input Signal 20 in dedicated first Stage addressing
`unit 102. The first stage addressing unit 102 is the same logic
`as the first Stage addressing unit 72.
`Similarly, a real time display refresh request Signal 22 is
`received by another dedicated pipeline processor 92 through
`a dedicated input port 104 in a pipeline fashion. The pipeline
`processor 92 receives the real time display refresh request
`input Signal 22 in Separate first Stage addressing unit 106.
`The first Stage addressing logic 106 is the same logic as the
`first stage addressing unit 102. Each pipeline processor 90
`and 92 has a Second Stage that is an output Stage. The output
`stage is the common arbitor 98. The common arbitor 98 is
`priority based arbitration logic like that of arbitration logic
`76 (FIG.3) but includes an additional real time input that is
`prioritized.
`It will be recognized by those of ordinary skill in the art,
`that if additional real time input signals are used, additional
`dedicated input ports 108 and additional dedicated pipeline
`processors can be used in the Same way as pipeline proces
`sors 90 and 92 and that the arbitration logic 98 can be
`Suitably expanded to accommodate Some additional inputs.
`The multiple pipeline memory controller 88 also includes
`a plurality of input ports 110, 112, and 114 for receiving a
`plurality of non-real time input Signals in a pipeline fashion
`through a dedicated three Stage pipeline processor 94. A first
`Stage of the pipeline processor 94 is priority based arbitra
`tion logic 96 connected to receive the plurality of non-real
`time input signals from the plurality of input ports 110, 112
`and 114. The priority arbitor 96 selects one of the non-real
`time input signals based on a priority determination and
`outputs the Selected non-real time input Signal to Second
`Stage addressing unit 116. The Second Stage addressing unit
`116 is the same logic as the first Stage addressing unit 102
`and 106 of pipeline processors 90 and 92. Therefore, each of
`the dedicated pipeline processors 90,92 and 94 has separate
`addressing units in the form of addressing logic with
`memory row/column address determination logic and
`memory page fault detection logic.
`As with the first stage addressing units 102 and 106, the
`Second Stage addressing unit 116 outputs a signal to the
`common arbitor 98 which is the third stage of pipeline
`processor 94. Therefore, the priority based common arbitor
`98 is a final Stage for all three dedicated pipeline processors
`90, 92 and 94. The priority based common arbitor 98
`Selectively determines which of the real time and non-real
`time input signals is to be output to memory 60 through
`output port 118, by giving the real time display refresh
`request Signal 22 first priority, giving the real time video
`capture request Signal 20 Second priority and giving the
`non-real time inputs 110, 112 and 114 last priority.
`The multiple pipeline memory controller 88 is preferably
`manufactured as integrated circuitry incorporated in a video
`graphics controller chip for computers. It is preferable that
`any real time input signal be processed by a dedicated two
`Stage pipeline processor as disclosed, however, it will be
`recognized that if desired, pipeline processors having more
`than two stages may be Suitable.
`By having multiple pipeline processors each dedicated to
`Separately process a respective real time input Signals, the
`real time request Signal will always be quickly processed
`irrespective of the number of real and non-real input signal
`requests that the memory controllers 28 and 88 must process
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`Since the need for a first stage arbitor of real time signal
`inputS is Substantially eliminated. This improves memory
`access latency for real time signals. Moreover, the architec
`ture of the memory controllers 28 and 88 has an improved
`real time Signal memory access latency due to the preferred
`dual Stage pipeline for real time input signals. Memory
`acceSS conflicts can be significantly reduced. Also the non
`real time Signals are economically processed using a third
`and shared pipeline processor having first Stage arbitration
`logic. Priority non-real time requests are processed prior to
`other leSS important non-real time requests.
`The reduction in memory access latency from the Separate
`multiple pipelines provides more effective use of display
`FIFO memory that can Support higher resolution display.
`Consequently, additional costs and manufacturing complex
`ity are reduced since additional FIFO memory need not be
`added even through additional real time inputs are added to
`the graphic control System.
`Also, it will be recognized that the use of a dual Stage
`multiple pipeline processing System as described above
`reduces the memory access latency period. With the dis
`closed configuration, extrinsic memory access latency can
`be reduced from twenty-one clock cycles to Seven clock
`cycles to more efficiently Service the real time request input
`signals. This reduction allows the same FIFO memory to
`receive nearly three times the information than previous
`memory controllers. It will be apparent that other advan
`tages are also facilitated by the disclosed memory controller.
`It should also be understood that the implementation of
`other variations and modifications of the invention in its
`various aspects will be apparent to those of ordinary skill in
`the art, and that the invention is not limited by the Specific
`embodiments described. For example, each of the pipeline
`processing circuits can be independent Such that each circuit
`has a Separate RAS CAS circuit and Separate output circuit.
`Also, the memory controller can have more than three
`pipeline processing circuits if additional input Signals are
`used. Moreover, one or more of the pipeline processors may
`have more than two Stages. It is therefore contemplated to
`cover by the present invention, any and all modifications,
`variations, or equivalents that fall within the Spirit and Scope
`of the basic underlying principles disclosed and claimed
`herein.
`What is claimed is:
`1. A memory controller for Servicing real time data
`comprising:
`at least a first input port for receiving a real time request
`Signal in a pipeline fashion;
`at least a Second input port for receiving a non-real time
`request Signal in a pipe line fashion;
`first pipeline processor, operatively coupled to the first
`input port, to Separately process the real time request
`Signal in a pipeline fashion wherein the first pipeline
`processor is a dual Stage pipeline processor with a first
`Stage addressing unit having addressing logic with first
`memory row/column address determination logic and
`first memory page fault detection logic,
`Second pipeline processor, operatively coupled to the
`Second input port, to Separately process the non-real
`time request Signal in a pipeline fashion; and
`wherein the first and Second pipeline processors include
`an arbitrator to selectively determine which of the real
`time and non-real time request signals is to be output to
`memory.
`2. The memory controller of claim 1 wherein the second
`pipeline processor includes a dual Stage pipeline processor
`
`Ex. 6, p. 8
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`7
`with first Stage addressing unit having addressing logic
`having Second memory row/column address determination
`logic and Second memory page fault detection logic.
`3. The memory controller of claim 1 wherein the arbitra
`tor Serves as a common final Stage for the first and Second
`pipeline processors.
`4. The memory controller of claim 3 wherein the arbitra
`tor includes memory cycle generation circuitry for control
`ling timing to access the memory.
`5. The memory controller of claim 1 having a plurality of
`Second input ports for receiving non-real time data, and
`further comprising priority based arbitration logic, opera
`tively coupled between the plurality of Second input ports
`and the Second pipeline processor, for receiving a plurality
`of non-real time input data Signals and for determining
`which of the non real time data Signals is processed next by
`the Second pipeline processor.
`6. The memory controller of claim 5 wherein the arbitra
`tor includes priority based arbitration logic, operatively
`coupled to a multiplexer, for controlling the multiplexer to
`output a Selected Signal to be output to memory.
`7. The memory controller of claim 1 wherein the control
`ler is integrated circuitry operatively used as a Section of a
`Video graphics controller for computers.
`8. The memory controller of claim 1 wherein the real time
`request Signal is a Video request Signal.
`9. The memory controller of claim 8 wherein the real time
`request Signal is a computer display control Signal.
`10. The memory controller of claim 1 wherein the non
`real time request Signal is a request Signal from a central
`processing unit.
`11. The memory controller of claim 1 wherein each of the
`first and Second pipeline processors has a two Stage pipeline
`proceSS comprised of an address determination Stage and an
`Output Stage.
`12. The memory controller of claim 11 wherein the first
`pipeline processor facilitates an extrinsic memory acceSS
`latency period of Seven memory clock cycles for the real
`time input Signal.
`13. A memory controller for Servicing real time data
`comprising:
`at least a first and Second input port for receiving first and
`Second real time input signals in a pipeline fashion;
`a plurality of input ports for receiving a plurality of
`non-real time input Signals in a pipeline fashion;
`first pipeline processor, operatively coupled to the first
`input port, to Separately process the real time request
`Signal in a pipeline fashion;
`Second pipeline processor, operatively coupled to the
`Second input port, to Separately process the non-real
`time request Signal in a pipeline fashion;
`
`1O
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`8
`first priority based arbitration logic, connected to receive
`the plurality of non-real time input signals from the
`plurality of input ports, for Selecting one of the non-real
`time input Signals based on a priority determination and
`outputting a Selected non-real time input signal;
`third pipeline processor, operatively coupled to receive
`the Selected non-real time input signal from the priority
`based arbitration logic, to Separately process the
`Selected non-real time input Signal in a pipeline fash
`ion; and
`wherein the first, Second and third pipeline processors
`include Second priority based arbitration logic as a final
`Stage for Selectively determining which of the real time
`and non-real time input signals is to be output to
`memory.
`14. The memory controller of claim 13 wherein the
`controller is integrated circuitry incorporated in a video
`graphics controller chip for computers.
`15. The memory controller of claim 13 wherein each of
`the first, Second and third pipeline processors are comprised
`of dedicated addressing units having first memory row/
`column address determination logic and first memory page
`fault detection logic.
`16. The memory controller of claim 15 wherein the
`Second priority based arbitration means is comprised of
`priority based arbitration logic, operatively coupled between
`the addressing logic of the first, Second and third processors
`and the output port, for receiving at least one non-real time
`input data Signal and a plurality of real time input data
`Signals and for Selectively determining a priority between
`the real time and non-real time input signals to be output to
`memory via the output port.
`17. The memory controller of claim 14 wherein the
`controller is used in a Video graphics card insertable into a
`computer slot.
`18. The memory controller of claim 13 wherein the
`Second priority based arbitration logic Serves as a final Stage
`for the first, Second and third pipeline processors.
`19. The memory controller of claim 18 wherein the
`Second priority based arbitration means includes memory
`cycle generation circuitry for controlling timing to access
`the memory.
`20. The memory controller of claim 13 wherein one of the
`real time input signals is a Video request signal and another
`is a display request Signal.
`21. The memory controller of claim 13 wherein the first
`and Second pipeline processors each facilitate an extrinsic
`memory access latency period of Seven memory clock
`cycles for respective real time input signals.
`
`k
`
`k
`
`k
`
`k
`
`k
`
`Ex. 6, p. 9
`
`