Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 1 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 1 of 17
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`
`
`UNITED STATES PATENT AND TRADEMARKOFFICE
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`10/459,797
`
`FILING DATE
`
`06/12/2003
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`Mark M.Leather
`
`00100.02.0053
`
`4148
`
`7590
`
`12/14/2004
`
`Christopher J. Reckamp
`Vedder, Price, Kaufman & Kammholz
`222 North LaSalle Street
`Chicago, IL 60601
`
`EXAMINER
`
`HSU, JONI
`
`2676
`DATE MAILED:12/14/2004
`
`Please find below and/orattached an Office communication concerning this application or proceeding.
`
`PTO-90C (Rev.10/03)
`
`Ex. 5, p.1
`
`Ex. 5, p. 1
`
`

`

`
`
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`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 2 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 2 of 17
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`
`
`Application No.
`
`Applicant(s)
`
`
`
`Office Action Summary
`
`10/459,797
`Examiner
`Joni Hsu
`
`LEATHER ETAL.
`Art Unit
`2676
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address--
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTH(S) FROM
`THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a).
`after SIX (6) MONTHSfrom the mailing date of this communication,
`If the period for reply specified aboveis less thanthirty (30) days, a reply within the statutory minimum ofthirty (30) dayswill be consideredtimely.
`-
`IfNO period for reply is specified above, the maximum statutory period will apply andwill expire SIX (6) MONTHSfrom the mailing date of this communicatian.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three monthsafter the mailing date of this communication, evenif timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`In no event, however, may a reply be timelyfiled
`
`Status
`
`1) Responsive to communication(s) filed on
`2a)C This action is FINAL.
`2b)X] This action is non-final.
`3)L] Since this application is in condition for allowance exceptfor formal matters, prosecution as to the merits is
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`4)X] Claim(s) 1-24 is/are pending in the application.
`
`4a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`5)C] Claim(s)
`is/are allowed.
`6) Claim(s) 1-24 is/are rejected.
`7) Claim(s) 9 and 24is/are objected to.
`8)L] Claim(s)___ are subjectto restriction and/or election requirement.
`
`Application Papers
`
`9)_] The specification is objected to by the Examiner.
`
`10)(_] The drawing(s)filed on
`is/are: a)L_] accepted or b)[_] objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(q).
`11){_] The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
`
`Priority under 35 U.S.C. § 119
`
`12) Acknowledgmentis madeof a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or(f).
`a)L] All
`b)LJ Some * c)L] Noneof:
`1.L] Certified copies of the priority documents have been received.
`2.01 Certified copies of the priority documents have beenreceivedin Application No.
`3.1] Copiesof the certified copies of the priority documents have beenreceivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`1) BX) Notice of References Cited (PTO-892)
`2) L_] Notice of Draftsperson’s Patent Drawing Review (PTO-948)
`3) [ Information Disclosure Statement(s) (PTO-1449 or PTO/SB/08)
`Paper No(s)/Mail Date
`.
`U.S. Patent and Trademark Office
`
`4) (JJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date.
`5) L] Notice ofinformal Patent Application (PTO-152)
`6) oO Other:
`
`PTOL-326 (Rev. 1-04)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 61203
`
`Ex. 5, p.2
`
`Ex. 5, p. 2
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 3 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 3 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
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`Page 2
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`DETAILED ACTION
`
`Claim Objections
`
`1.
`
`Claim 9 objected to becauseof the following informalities: In line 6 on page 17, the
`
`claim states “two graphics pipeline” where it should state “two graphics pipelines”. Appropriate
`
`correction is required.
`
`2.
`
`Claim 24 objected to because of the following informalities:
`
`In lines 14-15 on page 20,
`
`the claim states “set of tiles or the repeating tile pattern” where it should state “set of tiles ofthe
`
`repeatingtile pattern”. In line 18 on page 20, the claim states “receive transmit and receive”
`
`whereit should state “transmit and receive”. Appropriate correction is required.
`
`Claim Rejections - 35 USC § 112
`
`3.
`
`The following is a quotation of the second paragraph of 35 U.S.C. 112:
`
`The specification shall conclude with one or more claimsparticularly pointing out and
`distinctly claiming the subject matter which the applicant regards as his invention.
`
`4.
`
`Claims 9, 12, and 13 are rejected under 35 U.S.C. 112, second paragraph, as being -
`
`indefinite for failing to particularly point out and distinctly claim the subject matter which
`
`applicant regards as the invention.
`
`Claim 9 recites the limitation "the first pipeline" and “the second pipeline”. Thereis
`
`insufficient antecedent basis for this limitation in the claim.
`
`Ex. 5, p. 3
`
`Ex. 5, p. 3
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 4 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 4 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
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`Page 3
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`Claim 12 recites the limitation "the pixel data". There is insufficient antecedentbasis for
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`this limitation in the claim.
`
`Claim 13 recites the limitation "the front end circuitry" and “the back endcircuitry”.
`
`There is insufficient antecedentbasis for this limitation in the claim.
`
`Claim Rejections - 35 USC § 103
`
`5.
`
`The following is a quotation of 35 U.S.C. 103(a) which formsthebasisfor all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained thoughthe inventionis notidentically disclosed or
`describedas set forth in section 102ofthistitle, if the differences between the subject
`matter soughtto be patented andthe prior art are suchthat the subject matter as a whole
`would have been obviousat the time the invention was madeto a person having ordinary
`skill in the art to which said subject matter pertains. Patentability shall not be negatived
`by the mannerin which the invention was made.
`
`6.
`
`The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459
`
`(1966), that are applied for establishing a background for determining obviousness under 35
`
`U.S.C. 103(a) are summarized as follows:
`
`PWNS
`
`Determining the scope and contentsof the priorart.
`Ascertaining the differences between the prior art and the claimsat issue.
`Resolving the level of ordinary skill in the pertinent art.
`Considering objective evidence present in the application indicating obviousness
`or nonobviousness.
`
`7.
`
`Claims 1-8, 10-18, and 20-23 are rejected under 35 U.S.C. 103(a) as being unpatentable
`
`over Migdal (US006762763B1) in view of Heirich (US006753878B1), further in view of Duffy
`
`(US005179640A).
`
`Ex. 5, p.4
`
`Ex. 5, p. 4
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 5 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 5 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
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`Page 4
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`8.
`
`With regard to Claim 1, Migdal describes a graphics processing circuit, comprising a
`
`graphics pipeline (Col. 1, line 66-Col. 2, line 17) operative to process data in a corresponding set
`
`oftiles, the graphics pipeline operative to process data in a dedicated tile (Col. 8, lines 20-23).
`
`However, Migdal does notteach that there are at least two graphics pipelines and each
`
`graphics pipeline processes data in a dedicatedtile. However, Heirich describes multiple
`
`graphicspipelines (22, 24, Figure 1; Col. 5, lines 31-33) and each graphicspipeline processes
`
`data in a dedicated part of the image (PI, Col. 6, lines 1-6).
`
`It would have been obviousto oneofordinary skill in this art at the time of invention by
`
`applicant to modify the device of Migdalso that there are at least two graphics pipelines and
`each graphics pipeline processes data in a dedicated tile as suggested by Heirich. Heirich
`
`suggests that it is advantageous to use multiple graphics pipelines because each pipeline can
`
`work on a different process or part of the image without waiting for the other processes to finish
`
`first (Col. 2, lines 24-39), so using multiple graphics pipelines speeds up the processing
`
`operation.
`
`However, Migdal and Heirich do not teach a repeating tile pattern, wherein the repeating
`
`tile pattern includes a horizontally and vertically repeating pattern of square regions. However,
`
`Duffy describesa repeating tile pattern, wherein the repeating tile pattern includes a horizontally
`
`and vertically repeating pattern of square regions (Col. 3, line 67-Col.4, line 4; Col. 4, lines 31-
`32; Col.5, lines 17-20).
`
`It would have been obviousto one of ordinaryskill in this art at the time of invention by
`
`applicant to modify the devices of Migdal and Heirich to includea repeatingtile pattern, wherein
`
`the repeatingtile pattern includesa horizontally and vertically repeating pattern of square regions
`
`Ex. 5, p. 5
`
`Ex. 5, p. 5
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 6 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 6 of 17
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`Application/Contro! Number: 10/459,797
`Art Unit: 2676
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`Page 5
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`as suggested by Duffy because Duffy suggests that rather than generating an entire simulated
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`halftone screen for each process color of an image, which takes up substantial additional
`
`computing power, a set of rectangular repeating patterns can bestored andretrieved for use in
`
`filling incremental regions of the image (Col. 3, line 63-Col. 4, line 4).
`
`9,
`
`With regard to Claim 2, Migdal describes that the square regions comprise a two
`
`dimensionalpartitioning of memory (Col. 7, lines 63-65).
`
`10. With regard to Claim 3, Migdal describes that the memory is a frame buffer (Col. 5, lines
`
`63-67).
`
`11. With regard to Claim 4, Migdal describesthat the graphics pipeline further includesfront
`
`end circuitry (105, Figure 1) operative to receive vertex data and generate pixel data
`
`correspondingto a primitive to be rendered (Col. 4,lines 46-51; Col. 5, lines 39-41; Col. 8, lines
`
`17-19), and back endcircuitry (108), coupled to the front end circuitry, operative to receive and
`
`process a portion ofthe pixel data (Col. 4, lines 46-51).
`
`However Migdal does not teach that there are two graphics pipelines operative to receive
`
`and process a portion of the pixel data. However, Heirich describes multiple graphicspipelines
`
`(22, 24, Figure 1; Col. 5, lines 31-33) operative to receive and process a portion ofthe pixel data
`
`(PI, Col. 6, lines 1-6), as discussed in the rejection for Claim 1.
`
`Ex. 5, p. 6
`
`Ex. 5, p. 6
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 7 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 7 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
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`Page 6
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`12. With regard to Claim 5, Migdal describes that the graphics pipeline further includes a
`scan converter (602, Figure 6), coupled to the back end circuitry (603-615), operative to
`determine the portion ofthe pixel data to be processed by the back endcircuitry (Col. 8, lines 7-
`
`19).
`
`However Migdal doesnot teach that there are two graphics pipelines. However, Heirich
`
`describes multiple graphics pipelines (22, 24, Figure 1; Col. 5, lines 31-33), as discussed in the
`
`rejection for Claim 1.
`
`13.
`
`With regard to Claim 6, Migdal describes that eachtile of the setof tiles further
`
`comprises a 16x16 pixel array (Col. 7, lines 63-65).
`
`14. With regard to Claim 7, Migdal doesnotteach that the at least two graphicspipelines
`
`separately receive the pixel data from the front end circuitry. However, Heirich describes that
`
`the at least two graphicspipelines (22, 24, Figure 1) separately receive the pixel data (PI) from
`
`the front end circuitry (22) (Col. 6, lines 1-6).
`It would have been obviousat the time of invention by applicant to modify the device of
`
`Migdalso thatthe at least two graphics pipelines separately receive the pixel data from the front
`
`end circuitry as suggested by Heirich. Since Heirich describes using multiple graphics pipelines,
`
`each graphics pipeline must inherently separately receive the pixel data from the front end
`
`circuitry. The advantages of using multiple graphics pipelines were discussedin the rejection for
`
`Claim 1.
`
`Ex. 5, p.7
`
`Ex. 5, p. 7
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 8 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 8 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
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`Page 7
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`15. With regard to Claim 8, Migdal does not teach that the at least two graphics pipelines are
`
`on multiple chips. However, Heirich describes multiple graphics pipelines and that each
`
`graphics pipeline can be on a separate workstation (Figure 4; Col. 16, lines 53-59). Since the
`
`graphicspipelines are on separate workstations, the graphics pipelines mustinherently be on
`
`multiple chips.
`
`It would have been obviousat the time of invention by applicant to modify the device of
`
`Migdalso that the at least two graphicspipelines are on multiple chips as suggested by Heirich
`
`because Heirich suggests the advantageof beingable to put the different chips on different
`
`workstations. In this configuration, off-the-shelf workstations and graphics accelerator cards can
`
`be used for image generation, which greatly reduces the cost of the’system. The marginal costs
`
`of the image generation process might be reduced even further if the workstations and graphics
`
`accelerators are used for other purposes (Col. 16, lines 41-46).
`
`16. With regard to Claim 10, Migdal does notteach thata first of the at least two graphics
`
`pipelines processes the pixel data only in a first set oftiles in the repeating tile pattern. However,
`
`Heirich describes multiple graphics pipelines (22, 24, Figure 1), and each graphicspipeline
`processesonlyapart ofan image PL Col. 6, lines 1-6). Therefore, Heirich describes thata first
`
`of the at least two graphics pipelines processes the pixel data onlyinafirstsetof tiles.
`
`However, Migdal and Heirich do notteach a repeatingtile pattern. However, Duffy
`
`describes a repeating tile pattern (Col. 4, lines 26-53; Col. 5, lines 17-20), as discussed in the
`
`rejection for Claim 1.
`
`Ex. 5, p. 8
`
`Ex. 5, p. 8
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 9 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 9 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
`
`Page 8
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`17. With regard to Claim 11, Migdal describes that the graphics pipeline further includes a
`
`scan converter (602, Figure 6), coupled to the front end circuitry (105, Figure 1) and the back
`
`end circuitry (603-615, Figure 6), operative to provide position coordinates of the pixels within
`
`the first set of tiles to be processed by the back endcircuitry (Col. 8, lines 17-19). The scan
`
`converter provides position coordinates to the texture request generator (603). From these
`
`position coordinates, the texture request generator knows whichofthesetoftiles is to be
`
`processed by the back endcircuitry and generates the required tile addresses for theses tiles (Col.
`
`8, lines 17-23). Therefore, the scan converter must inherently includea pixelidentification line
`
`for receiving tile identification data indicating which of the set oftiles is to be processed by the
`
`back end circuitry.
`
`However Migdal does not teach that there are two graphics pipelines. However, Heirich
`
`describes multiple graphics pipelines (22, 24, Figure 1; Col. 5, lines 31-33), as discussed in the
`
`rejection for Claim 1.
`
`18. With regard to Claim 12, Claim 12 is similar in scope to Claim 10, and thereforeis
`
`rejected under the samerationale.
`
`19. With regard to Claim 13, Claim 13 is similar in scope to Claim 11, and thereforeis
`
`rejected under the samerationale.
`
`20. With regard to Claim 14, Migdal describes a graphics pipeline (Col. 1, line 66-Col. 2, line
`
`17) including front end circuitry (105, Figure 1) operative to receive vertex data and generate
`
`Ex. 5, p. 9
`
`Ex. 5, p. 9
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 10 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 10 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
`
`Page 9
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`pixel data corresponding to a primitive to be rendered (Col. 4, lines 46-51; Col. 5, lines 39-41;
`
`Col. 8, lines 17-19), and back end circuitry (108), coupled to the front endcircuitry, operative to
`
`receive and process the pixel data in a set oftiles in the repeating tile pattern (Col. 4, lines 46-
`
`51).
`
`However, Migdal does notteachathird graphics pipeline and a fourth graphicspipeline.
`
`However, Heirich describes multiple graphics pipelines (22, 24, Figure 1; Col. 5, lines 31-33), as
`
`discussed in the rejection for Claim 1. Heirich also describes that each pipeline processes the
`
`pixel data only in onesetoftiles in the repeating tile pattern, as discussed in the rejection for
`
`Claim 10.
`
`However, Migdal and Heirich do not teach a repeating tile pattern. However, Duffy
`
`describes a repeating tile pattern (Col. 4, lines 26-53; Col. 5, lines 17-20), as discussed in the
`
`rejection for Claim 1.
`
`21. With regard to Claim 15, Claim 15 is similar in scope to Claim 11, and thereforeis
`
`rejected under the samerationale.
`
`22.
`
`With regard to Claim 16, Claim 16 is similar in scope to Claim 11, and therefore is
`
`rejected under the samerationale.
`
`23.
`
`With regard to Claim 17, Claim 17 is similar in scope to Claim 8, andtherefore is
`
`rejected under the samerationale.
`
`Ex. 5, p. 10
`
`Ex. 5, p. 10
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 11 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 11 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
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`Page 10
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`24. With regard to Claim 18, Miedal does not teach a bridge operative to transmit vertex data
`
`to eachofthefirst, second, third and fourth graphics pipelines. However, Heirich describes a
`
`bridge (20, Figure 1) operative to transmit vertex data to eachofthe first, second, third and
`
`fourth graphics pipelines (22) (Col. 5, lines 45-50).
`It would have been obviousto one ofordinary skill in this art at the time ofinvention by
`
`applicant to modify the device of Migdal to include a bridge operative to transmit vertex data to
`
`each ofthe first, second, third and fourth graphics pipelines as suggested by Heirich because
`
`Heirich suggests the advantage of being able to distribute all of the vertex data at once (Col. 5,
`
`lines 53-58). The advantages of having multiple graphics pipelines were discussed in the
`
`rejection for Claim 1.
`
`25. With regard to Claim 20, Migdal describes a graphics processing method, comprising
`
`receiving vertex data for a primitive to be rendered; generating pixel data in response to the
`
`vertex data (Col. 4, lines 46-51); determining the pixels within a set of tiles to be processed by a
`
`the graphics pipeline in responseto the pixel data; and performing pixel operations on the pixels
`
`within the determinedsetoftiles by the graphics pipeline (Col. 8, lines 6-23).
`
`However, Migdal does not teach a repeatingtile pattern including a horizontally and
`
`vertically repeating pattern of square regions. However, Duffy describes a repeatingtile pattern
`
`including a horizontally and vertically repeating pattern of square regions (Col. 4,lines 26-53;
`
`Col. 5, lines 17-20) as discussed in the rejection for Claim 1.
`
`Ex. 5, p.11
`
`Ex. 5, p. 11
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 12 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 12 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
`
`Page 11
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`However, Migdal and Duffy do not teach twographicspipelines. However, Heirich
`
`describes multiple graphics pipelines (22, 24, Figure 1; Col. 5, lines 31-33), as discussed in the
`
`rejection for Claim 1.
`
`26. With regard to Claim 21, Migdal does not teach that determiningthe pixels within a set
`
`of tiles of the repeatingtile pattern to be processed further comprises determiningthesetoftiles
`
`that the corresponding graphics pipeline is responsible for. However, Heirich describes multiple
`
`graphics pipelines (22, 24, Figure 1), and each graphics pipeline processes only a part of an
`
`image (PI, Col. 6, lines 1-6), as discussed in the rejection for Claim 10. Therefore, Heirich
`
`inherently teaches determining the pixels within a set oftiles to be processed further comprises
`
`determiningthesetof tiles that the corresponding graphics pipeline is responsible for.
`
`However, Migdal and Heirich do not teach a repeating tile pattern. However, Duffy
`
`describes a repeatingtile pattern (Col. 4, lines 26-53; Col. 5, lines 17-20), as discussed in the
`
`rejection for Claim 1.
`
`27. With regard to Claim 22, Migdal describes determining the pixels within a set oftiles to
`
`be processed further comprises providing position coordinates of the pixels within the
`
`determinedset of tiles to be processed to the graphics pipeline (Col. 8, lines 17-23).
`
`However, Migdal does not teach a repeatingtile pattern. However, Duffy describes a
`
`repeatingtile pattern (Col. 4, lines 26-53; Col. 5, lines 17-20), as discussed in the rejection for
`
`Claim 1.
`
`Ex. 5, p. 12
`
`Ex. 5, p. 12
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 13 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 13 of 17
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`Application/Control Number: 10/459, 797
`Art Unit: 2676
`
`Page 12
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`However, Migdal and Duffy do not teach two graphics pipelines. However, Heirich
`
`describes multiple graphics pipelines (22, 24, Figure 1; Col. 5, lines 31-33), as discussed in the
`
`rejection for Claim 1.
`
`28. With regard to Claim 23, Migdal describes transmitting the processed pixels to memory
`
`(109, Figure 1; Col. 8, line 48-Col. 9, line 3).
`
`29.
`
`Claim 9 rejected under 35 U.S.C. 103(a) as being unpatentable over Migdal
`
`(US006762763B1) in view of Heirich (US006753878B1), further in view of Duffy
`
`(US005179640A), further in view of Wang (US006184906B1).
`
`Migdal, Heirich, and Duffy are relied upon for the teachings as discussed aboverelative
`
`to Claim 1.
`
`However, Migdal, Heirich, and Duffy do not teach a memory controller coupledto the at
`
`least two graphics pipelines, operative to transfer pixel data between eachofthe first pipeline
`
`and the second pipeline and a memory. However, Wang describes a memory controller (28,
`
`Figure 2) coupled to the at least two graphics pipelines, operative to transfer pixel data between
`
`each ofthe first pipeline and the second pipeline and a memory (60) (Col. 3, lines 55-58).
`
`It would have been obviousto oneof ordinary skill in this art at the time of invention by
`
`applicant to modify the devices of Migdal, Heirich, and Duffy to include a memory controller
`coupled to the at least two graphics pipelines, operative to transfer pixel data between each ofthe
`
`first pipeline and the second pipeline and a memory as suggested by Wang because Wang
`
`Ex. 5, p.13
`
`Ex. 5, p. 13
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 14 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 14 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
`
`Page 13
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`suggests the advantage of improving the speed of operation and allowing for a single memory
`
`clock cycle read/write operation (Col. 1, lines 51-55).
`
`30.
`
`Claim 19 rejected under 35 U.S.C. 103(a) as being unpatentable over Migdal
`
`(US006762763B 1) in view of Heirich (US006753878B1), further in view of Duffy
`
`(US005179640A), further in view of Kent (US 20030164830A1).
`
`Migdal, Heirich, and Duffy are relied upon for the teachingsas discussed aboverelative
`
`to Claim 17.
`
`However, Migdal, Heirich, and Duffy do not teach that the data includes a polygon and .
`
`wherein each separate chip creates a bounding box around the polygon and wherein each corner
`
`of the bounding box is checked against a super tile that belongs to each separate chip [0010,
`
`0012] and wherein if the bounding box does not overlap anyof the supertiles associated with a
`separate chip, then the processing circuit rejects the whole polygon and processes a next one.
`
`However, Kent describes the data includes a polygon [0006] and wherein each separate chip
`
`creates a bounding box around the polygon and wherein each corner of the bounding box is
`
`checked against a supertile that belongs to each separate chip and wherein if the bounding box
`
`does not overlap any of the supertiles associated with a separate chip, then the processingcircuit
`
`rejects the whole polygon and processes a next one [0129, 0144].
`
`It would have been obviousto one ofordinary skill in this art at the time of invention by
`
`applicant to modify the devices of Migdal, Heirich, and Duffy so that the data includes a polygon
`
`and wherein each separate chip creates a bounding box around the polygon and wherein each
`
`corner of the bounding box is checked against a supertile that belongs to each separate chip and
`
`Ex. 5, p. 14
`
`Ex. 5, p. 14
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 15 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 15 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
`.
`
`Page 14
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`wherein if the bounding box does not overlap anyof the supertiles associated with a separate
`
`chip, then the processing circuit rejects the whole polygon and processes a next one as suggested
`
`by Kent because Kent suggests the advantage of being able to determine if a polygon is within
`
`the supertiles associated with a separate chip [0129, 0144]. This is needed in order for each
`
`separate chip to only process the pixel data in onesetoftiles, as discussed in the rejections for
`
`Claims 8 and 10.
`
`31.
`
`Claim 24 rejected under 35 U.S.C. 103(a) as being unpatentable over Migdal
`
`(US006762763B1) in view of Duffy (US005179640A), further in view of Morgan
`
`(US006714203B1), further in view of Wang (US006184906B1).
`
`Migdal describes a graphics processingcircuit, comprising front end circuitry (105,
`
`Figure 1) operative to generate pixel data in response to primitive data for a primitive to be
`
`rendered (Col. 4, lines 46-51; Col. 5, lines 39-41; Col. 8, lines 17-19); first back end circuitry
`
`(108), coupledto the front end circuitry, operative to processafirst portion ofthe pixel data in
`responseto position coordinates (Col.8, lines 20-23); a first scan converter (602, Figure 6),
`
`coupled between the front end circuitry and the first back endcircuitry, operative to determine
`
`whichset oftiles are to be processed bythe first back end circuitry, and operative to provide the
`
`position coordinatesof the first back end circuitry in response to the pixel data (Col. 8, lines 7-
`
`23).
`
`However, Migdal does notteach a repeating tile pattern including a horizontally and
`
`vertically repeating pattern of square regions. However, Duffy describes a repeatingtile pattern
`
`(Col. 4, lines 26-53; Col. 5, lines 17-20), as discussed in the rejection for Claim 1.
`
`Ex. 5, p.15
`
`Ex. 5, p. 15
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 16 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 16 of 17
`
`Application/Control Number: 10/459,797
`Art Unit: 2676
`
`Page 15
`
`However, Migdal and Duffy do not teach a second back end circuitry. However, Morgan
`
`describes a front end circuitry (202, Figure 2) coupled to multiple back end circuitries (208, 210)
`
`(Col. 3, lines 41-42),
`
`It would have been obviousto one of ordinary skill in this art at the time of invention by
`
`applicant to modify the devices of Migdal and Duffy to include a second back endcircuitry as
`
`suggested by Morgan because Morgan suggeststhatit is simpler to have one front-end circuitry
`
`as a data communicationsinterface for the image generation system (Col. 3, lines 32-34) and
`
`couple the one front-end circuitry to multiple back end circuitries. The multiple back-end
`
`circuitries are for multiple graphics pipelines. The advantagesof having multiple graphics
`
`pipelines were discussed in the rejection for Claim 1.
`
`However, Migdal, Duffy, and Morgan do not teach a memory controller, coupled to the
`
`first and second back endcircuitry, operative to transmit and receive the processed pixel data.
`
`However, Wang describes a memory controller (28, Figure 2), coupled to multiple pipelines or
`
`the first and second back endcircuitry, operative to transmit’and receivethe processed pixel data
`
`(Col. 3, lines 55-58), as discussed in the rejection for Claim 9.
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to Joni Hsu whosetelephone numberis 703-305-4418. The
`
`examiner can normally be reached on M-F 8am-5pm.
`
`Ex. 5, p. 16
`
`Ex. 5, p. 16
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 17 of 17
`Case 6:22-cv-00466-ADA-DTG Document 50-5 Filed 12/19/22 Page 17 of 17
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`Application/Control Number: 10/459,797
`Art Unit: 2676
`
`Page 16
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`If attempts to reach the examinerby telephone are unsuccessful, the examiner’s
`
`supervisor, Matthew C.Bella can be reached on 703-308-6829. The fax phone numberfor the
`
`organization wherethis application or proceeding is assigned is 703-872-9306.
`
`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished
`
`applicationsis available through Private PAIR only. For more information about the PAIR
`system, see http://pair-directuspto.gov. Should you have questions on access to the Private PAIR
`
`system, contact the Electronic Business Center (EBC) at 866-217-9197(toll-free).
`
`MATTHEW 0. BELLA
`SUPERV! ~:~. SENT EXAMINE:
`TECHi.ui CENTER 2600
`
`Ex. 5, p.17
`
`Ex. 5, p. 17
`
`