Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 1 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 1 of 21
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` UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`
`
`
` FILING DATE
`
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`CONFIRMATIONNO.
`
`
`10/459,797
`
`06/12/2003
`
`Mark M.Leather
`
`00100.02.0053
`
`4148
`
`29153
`
`7590
`
`04/22/2010
`
`ADVANCED MICRO DEVICES, INC.
`C/O VEDDERPRICEP.C.
`222 N.LASALLE STREET
`CHICAGO, IL 60601
`
`HSU, JONI
`
`2628
`
`MAIL DATE
`
`04/22/2010
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL-90A (Rev. 04/07)
`
`Ex. 3, p.1
`
`Ex. 3, p. 1
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 2 of 21
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`Application No.
`Applicant(s)
`
`Office Action Summary
`
`10/459,797
`Examiner
`
`LEATHER ETAL.
`Art Unit
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address--
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a).
`In no event, however, may a reply be timelyfiled
`after SIX (6) MONTHSfrom the mailing date of this communication.
`If NO period forreply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for replywill, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three monthsafter the mailing date of this communication, even if timely filed, may reduce any
`eamed patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1)X] Responsive to communication(s) filed on 25 January 2010.
`2a)X] This action is FINAL.
`2b)L] This action is non-final.
`3)L] Sincethis application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`4)X] Claim(s) 1-7,10-22,24 and 25 is/are pending in the application.
`
`4a) Of the above claim(s)
`is/are withdrawn from consideration.
`5)L] Claim(s)____ is/are allowed.
`
`6)X] Claim(s) 1-7,10-22,24 and 25 is/are rejected.
`7)L] Claim(s)__ is/are objectedto.
`8)L] Claim(s)____ are subject to restriction and/or election requirement.
`
`Application Papers
`
`9)L] The specification is objected to by the Examiner.
`
`10)L] The drawing(s) filed on
`is/are: a)[_] accepted or b)[_] objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`11)] The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
`
`Priority under 35 U.S.C. § 119
`
`12)L] Acknowledgmentis made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or(f).
`a)LJAll b)L_] Some*c)L] Noneof:
`
`1.L] Certified copies of the priority documents have been received.
`2.L] Certified copies of the priority documents have been received in Application No.
`3.L] Copies ofthe certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action foralist of the certified copies not received.
`
`Attachment(s)
`4) C] Interview Summary (PTO-413)
`1) C] Notice of References Cited (PTO-892)
`Paper No(s)/Mail Date. _
`2) [1] Notice of Draftsperson’s Patent Drawing Review (PTO-948)
`5) L] Noticeof Informal Patent Application
`3) IX] Information Disclosure Statement(s) (PTO/SB/08)
`
`6) C] Other: U.S. Patent and Trademark OfficePaper No(s)/Mail Date 1/25/10.
`PTOL-326 (Rev. 08-06)
`Office Action Summary
`Part of Paper noFRR BarPafoo12s
`
`Ex. 3, p. 2
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 3 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 2
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`DETAILED ACTION
`
`Information Disclosure Statement
`
`1.
`
`The information disclosure statement (IDS) submitted on January 25, 2010 wasfiled after
`
`the mailing date of the application on June 12, 2003. The submission is in compliance with the
`
`provisions of 37 CFR 1.97. Accordingly, the information disclosure statementis being
`
`considered by the examiner.
`
`Response to Arguments
`
`2.
`
`Applicant's arguments filed January 25, 2010 have been fully considered but they are not
`
`persuasive.
`
`3.
`
`Applicant arguesthat it is improper to use hindsight reconstruction and ignore the
`
`teachings of the reference as a whole in an effort to render a claim obvious(p. 9).
`
`In response to applicant's argument that the examiner's conclusion of obviousness is
`
`based upon improperhindsight reasoning, it must be recognized that any judgment on
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`obviousnessis in a sense necessarily a reconstruction based upon hindsight reasoning. But so
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`long as it takes into account only knowledge which was within the level of ordinary skill at the
`
`time the claimed invention was made, and doesnot include knowledge gleaned only from the
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`applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392,
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`170 USPQ 209 (CCPA 1971).
`
`4.
`
`Asper Claim 1, Applicant argues that the separate modules from the memory controller
`
`310 provide the specific scalability provided by the architecture of Perego (US006864896B2).
`
`Perego requires the separate memory controller 310 to be off chip and separate from the memory
`
`Ex. 3, p. 3
`
`Ex. 3, p. 3
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 4 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 3
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`modules. As such, combining the graphic pipeline teachings of Perego with those of MacInnis
`
`(US006570579B1) would render the Perego system inoperable (p. 10).
`
`In reply, the Examinerrespectfully points out that the main reference MacInnisis used to
`
`teach that the graphics pipeline (58, Fig. 2) and the memory controller (54) are on the same chip
`
`(10) (Fig. 2; col. 4, lines 65-67; col. 5, lines 36-41). Perego is used for its teaching of two
`
`graphics pipelines on the same chip to processdata inaset of tiles of a repeating tile pattern
`
`corresponding to screen locations, a respective one of the two graphics pipelines operative to
`
`process data in a dedicated tile; wherein the repeating tile pattern includes a horizontally and
`
`vertically repeating pattern of square regions. Perego is used as a secondary reference to modify
`
`the device of the main reference MacInnis. Thus, these teachings from the secondary reference
`
`Perego are being implemented into the device of the main reference MacInnis. Perego is not
`
`being used as the main reference, and so the teaching that the graphics pipeline and the memory
`
`controller are on the same chip from MacInnis is not being implementedinto the device of
`
`Perego to render the device of Perego inoperable. Since these teachings from the secondary
`
`reference Perego are being implemented into the device of the main reference MacInnis, and the
`
`device of the main reference MacInnisis still operable after this implementation, the
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`combination is proper.
`
`5.
`
`Applicant argues that the shared memories 314 of Perego are dedicated memoriesthat are
`
`each dedicated to a dedicated graphics pipeline and in no embodimentare these dedicated
`
`memories that are on separate modules ever described as storing data from more than one
`
`rendering engine. This is because this would eliminate the advantages of Perego's scalable
`
`unified memory architecture (p. 10). As shown in Fig. 8, memory devices 804 are only in
`
`Ex. 3, p.4
`
`Ex. 3, p. 4
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page5of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 4
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`communication with rendering engine 8012 whereas memory devices 812 are only in
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`communication with rendering engine 810. These memories are dedicated and are separate and
`
`are not shared amonggraphics pipelines or rendering engines 802 and 810 (p. 11).
`
`In reply, the Examinerpoints out that Perego describes “The shared memory 314
`
`typically includes multiple memory devices coupled together to form a block of storage space”
`
`(col. 4, lines 8-10). Thus, the block of storage space is considered to be a memory shared among
`
`the two graphics pipelines. Claim 1 recites “at least two graphics pipelines on a same chip
`
`operative to process data in a correspondingsetoftiles of a repeating tile pattern corresponding
`
`to screen locations, a respective one of the at least two graphics pipelines operative to process
`
`data in a dedicatedtile...wherein the repeating tile pattern includes a horizontally and vertically
`
`repeating pattern of square regions”, and Claim 2 recites "wherein the square regions comprise a
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`two dimensional partitioning of memory". Since each graphics pipeline processes a dedicated
`
`tile that is a square region, and each square regionis a partition of memory,this means that each
`
`graphics pipelines stores data to a partition of memory. Since Perego teaches that each graphics
`
`pipeline stores data to a partition of the block of storage space, and the block of storage space is
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`shared among the two graphicspipelines (col. 1, lines 44-54; col. 3, lines 3-6, 65-67; col. 4, lines
`
`1-10, 48-65; col. 5, lines 42-44), Perego reads on the limitations as recited in the claim.
`
`6.
`
`Asper Claim 24, Applicant argues that Fig. 8 of Perego showsseparate front end
`
`circuitry being employed since separate rendering engines 802 and 810 are employed and each of
`
`these are identical in structure. Thus, Perego does not teach that there is one front end circuitry
`
`that sends pixel data to both the first back end circuitry and the second back endcircuitry (p. 11).
`
`Ex. 3, p.5
`
`Ex. 3, p. 5
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 6 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 6 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 5
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`In reply, the Examiner points out that MacInnisis used to teach that the front end
`
`circuitry (90), the back endcircuitry (98) and the memory controller (54) are on the same chip
`
`(10) (col. 7, lines 55-63; col. 4, lines 65-67; col. 5, lines 36-39). Perego teaches one front end
`
`circuitry (308, Fig. 3) that sends pixel data to both the first back end circuitry (first rendering
`
`engine 312) and the second back end circuitry (second rendering engine 312) (col. 3, line 63-col.
`
`4, line 2; col. 5, lines 19-44). Thefirst back end circuitry (802, Fig. 8) and the second back end
`
`circuitry (810) are on the same chip (800) (Fig. 8; col. 6, lines 61-62). Since MacInnis teaches
`
`that the front end circuitry, the back end circuitry and the memory controller are on the same
`
`chip, this teaching from Perego can be implemented into the device of MacInnis so that the front
`
`end circuitry sends pixel data to both the first back end circuitry and the second back end
`
`circuitry, and the front end circuitry, the first back end circuitry, the second back endcircuitry,
`
`and the memory controller are on the same chip.
`
`Claim Objections
`
`7.
`
`Claim 20 is objected to because of the following informalities: Claim 20 recites “...the
`
`memory controller wherein the memory controller...” where it should recite “...the memory
`
`controller, wherein the memory controller...”. Appropriate correction is required.
`
`Claim Rejections - 35 USC § 103
`
`8.
`
`The following is a quotation of 35 U.S.C. 103(a) which formsthe basis forall
`
`obviousnessrejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in
`section 102 ofthistitle, if the differences between the subject matter sought to be patented and theprior art are
`such that the subject matter as a whole would have been obviousat the time the invention was madeto a person
`having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the
`manner in which the invention was made.
`
`Ex. 3, p. 6
`
`Ex. 3, p. 6
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page7of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 6
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`9.
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`The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459
`
`(1966), that are applied for establishing a background for determining obviousness under 35
`
`U.S.C. 103(a) are summarized as follows:
`
`BYwNP
`
`Determining the scope and contentsofthe priorart.
`Ascertaining the differences between the prior art and the claimsat issue.
`Resolving the level of ordinary skill in the pertinent art.
`Considering objective evidence presentin the application indicating obviousness
`or nonobviousness.
`
`10.
`
`Claims 1-4, 7, 10, 12, 14, and 25 are rejected under 35 U.S.C. 103(a) as being
`
`unpatentable over MacInnis (US006570579B 1) in view of Perego (US006864896B2).
`
`11.
`
`Asper Claim 1, MacInnis teaches a graphics processing circuit, comprising: a graphics
`
`pipeline (58, Fig. 2) on a chip (10); a memory controller (54) on the chip (10), as shownin Fig. 2
`
`(col. 4, lines 65-67; col. 5, lines 36-41), in communication with the graphics pipeline (58),
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`operative to transfer pixel data between the pipeline (58) and a memory (col. 6, lines 10-13, 59-
`
`66).
`
`However, MacInnis does not teach at least two graphics pipelines on the same chip
`
`operative to process data in a correspondingsetoftiles of a repeating tile pattern corresponding
`
`to screen locations, a respective one of the at least two graphics pipelines operative to process
`
`data in a dedicated tile; wherein the repeating tile pattern includes a horizontally and vertically
`
`repeating pattern of square regions. However, Perego teaches graphics processing circuit (300,
`
`Fig. 3; col. 3, lines 61-63) having at least 2 graphics pipelines (312) operative to process data in
`
`correspondingsetoftiles of repeating tile pattern corresponding to screen locations, respective
`
`one ofat least 2 graphics pipelines operative to process data in dedicatedtile (col. 5, lines 19-27,
`
`38-44); and memory controller (310, Fig. 3) in communication with at least 2 graphics pipelines
`
`Ex. 3, p. 7
`
`Ex. 3, p. 7
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 8 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 8 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 7
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`312, operative to transfer pixel data between each of 1* pipeline and am pipeline and shared
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`memories 314 (col. 3, lines 65-67; col. 4, lines 1-10, 48-65). Shared memories 314 are each part
`
`of main memory (col. 1, lines 44-54; col. 3, lines 3-6), and so are considered to be one memory
`
`that is shared amongtheat least two graphics pipelines. Repeating tile pattern includes
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`horizontally and vertically repeating pattern of regions of square regions, as shownin Fig. 5 (col.
`
`5, lines 19-27, 38-44). Perego describes “Improvements in integrated circuit design and
`
`manufacturing technologies allow higher levels of integration, thereby allowing an increasing
`
`numberof subsystemsto be integrated into a single device. This increased integration reduces
`
`the total number of components in a system, such as a computer system. As subsystems with
`
`high memory performance requirements (such as graphics subsystems) are combined with the
`
`traditional main memory controller, the resulting architecture may provide a single high-
`
`performance main memory interface” (col. 1, lines 34-43). Perego showsin Fig. 8 that in one
`
`embodiment, a memory module 800 contains two different rendering engines 802 and 810 (Fig.
`
`8; col. 6, lines 61-62), and therefore at least two graphics pipelines (802, 810) are on a same
`
`memory module 800. From Fig. 8 and from the description in Perego, one of ordinary skill in
`
`the art would understand that a memory module is equivalent to a chip. Therefore, Perego
`
`teaches that two graphics pipelines are on the same chip.
`
`It would have been obviousto one ofordinary skill in the art at the time of invention by
`
`applicant to modify MacInnis to include at least two graphics pipelines on the same chip
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`operative to process data in a correspondingsetoftiles of a repeating tile pattern corresponding
`
`to screen locations, a respective one of the at least two graphics pipelines operative to process
`
`data in a dedicated tile; wherein the repeating tile pattern includes a horizontally and vertically
`
`Ex. 3, p. 8
`
`Ex. 3, p. 8
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 9 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 9 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 8
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`repeating pattern of square regions because Perego suggests that this parallel processing
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`significantly reduces the processing burden on the memory controller/graphics controller (col. 5,
`
`lines 38-46).
`
`12.
`
`Asper Claim 2, MacInnis does not teaches that the square regions comprise a two
`
`dimensional partitioning of memory. However, Perego teaches square regions have two
`
`dimensionalpartitioning of memory (col. 5, lines 19-33). This would be obviousfor the reasons
`
`given in the rejection for Claim 1.
`
`13.
`
`As per Claim 3, MacInnis teaches wherein the memory is a frame buffer (col. 6, line 66-
`
`col. 7, line 2).
`
`14.
`
`As per Claim 4, MacInnis does not teach that each ofthe at least two graphics pipelines
`
`further includes front end circuitry operative to receive vertex data and generate pixel data
`
`corresponding to a primitive to be rendered, and back endcircuitry, coupled to the front end
`
`circuitry, operative to receive and process a portion of the pixel data. However, Perego teaches
`
`each of at least 2 graphics pipelines includes front end circuitry (308, Fig. 3) operative to
`
`generate pixel data correspondingto primitive to be rendered, and back endcircuitry (312),
`
`coupled to front end circuitry, operative to receive and processportion of pixel data (col. 3, line
`
`64-col. 4, line 2; col. 5, lines 19-44). In order for front end circuitry (308) to generate pixel data,
`
`it must receive vertex data. Perego teaches that the CPU sorts the primitive data according to the
`
`spatial region of the rendering surface (e.g., the x and y coordinates) covered by that primitive,
`
`and the rendering surface is divided into multiple rectangular regions ofpixels (col. 5, lines 19-
`
`27). One ofordinary skill in the art would understand that data pertaining to the x and y
`
`coordinates covered by the primitive would include vertex data. The main memory is used to
`
`Ex. 3, p. 9
`
`Ex. 3, p. 9
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 10 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 9
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`store data which are referenced during the execution of the programs(col. 1, lines 18-21).
`
`Therefore, the CPU is operative to receive vertex data (data pertaining to the x and y coordinates
`
`covered by the primitive) from the main memory and generate pixel data corresponding to a
`
`primitive to be rendered (col. 5, lines 19-27; col. 1, lines 18-21). Perego teaches that rendering
`
`engine 312 is coupled to the CPU,andis operative to receive and process a rectangular region of
`
`pixel data (col. 3, line 64-col. 4, line 2; col. 5, lines 19-44). Since the CPU is coupled to the
`
`rendering engine 312, and the CPU and the rendering engine 312 both perform graphics
`
`processing, and, the CPU performsthe operations ofthe front end circuitry, and the rendering
`
`engine 312 performsthe operations of the back end circuitry, the CPU andthe rendering engine
`
`312 are considered to be part of a graphics pipeline, and the CPU is consideredto be the front
`
`end circuitry included in the graphics pipeline. This would be obvious for the reasons given in
`
`the rejection for Claim 1.
`
`15.|As per Claim 7, MacInnis does not teach that the at least two graphics pipelines
`
`separately receive the pixel data from the front end circuitry. However, Perego teachesat least
`
`two graphics pipelines (312) separately receive pixel data from front end circuitry (308) (col. 3,
`
`line 64-col. 4, line 2; col. 5, lines 19-44). This would be obvious for the reasons given in the
`
`rejection for Claim 1.
`
`16.
`
`Asper Claim 10, MacInnis doesnot teach that a first of the at least two graphics pipelines
`
`processesthe pixel data only in thefirst set of tiles in the repeating tile pattern. However, Perego
`
`teachesfirst of at least two graphics pipelines(first rendering engine of 312, Fig. 3) processes
`
`pixel data only infirst set of tiles (tiles labeled “REO” in Fig. 5) in repeatingtile pattern (col. 5,
`
`lines 23-44). This would be obviousfor the reasons given in the rejection for Claim 1.
`
`Ex. 3, p. 10
`
`Ex. 3, p. 10
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 11 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 10
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`17.
`
`Asper Claim 12, MacInnis does not teach that a second ofthe at least two graphics
`
`pipelines processes the data only in a secondsetoftiles in the repeating tile pattern. However,
`
`Perego teaches second ofat least two graphics pipelines (second rendering engine of 312, Fig. 3)
`
`processespixel data only in secondset oftiles (tiles labeled “RE1” in Fig. 5) in repeatingtile
`
`pattern (col. 5, lines 23-44). This would be obviousfor the reasons given in the rejection for
`
`Claim 1.
`
`18.
`
`As per Claim 14, Claim 14 is similar to Claims 4 and 10, except that Claim 14 is for a
`
`third and fourth graphics pipeline. Perego teaches four graphics pipelines(col. 5, lines 41-44).
`
`So Claim 14 is rejected under the samerationale as Claims 4 and 10.
`
`19.=As per Claim 25, Claim 25 is similar in scope to Claim 1, and therefore is rejected under
`
`the samerationale.
`
`20.
`
`Claims 5, 18, and 24 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`MacInnis (US006570579B1) in view of Perego (US006864896B2), further in view of Kelleher
`
`(US005794016A).
`
`21.
`
`As per Claim 5, MacInnis and Peregoare relied on for teachings for Claim 4.
`
`But, MacInnis and Perego do not explicitly teach at each of 2 graphics pipelines includes
`
`scan converter, coupled to back end circuitry, operative to determine portion of pixel data to be
`
`processed by back endcircuitry. But, Kelleher teaches each ofat least 2 graphics pipelines (20A,
`
`20B, Fig. 3; col. 3, lines 22-23; col. 4, lines 9-14) includes scan converter (update stage, Fig. 7),
`
`coupled to back end circuitry, operative to determine portion of pixel data to be processed by
`
`back end circuitry (col. 8, lines 52-61; col. 9, lines 1-23; col. 6, lines 26-28).
`
`Ex. 3, p. 11
`
`Ex. 3, p. 11
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 12 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 12 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 11
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`It would have been obviousto one ofordinary skill in the art at the time of invention by
`
`applicant to modify MacInnis and Peregoso at each ofat least two graphics pipelines includes a
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`scan converter, coupled to the back end circuitry, operative to determine the portion of the pixel
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`data to be processed by the back endcircuitry because Kelleher suggests scan converters are
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`needed in order to define image data as array of pixels by calculating pixel addresses (col. 9,
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`lines 1-23), as is well-knownintheart.
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`22.
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`As per Claim 18, MacInnis does not teach a bridge operable to transmit vertex data to
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`each of the 1“, 2", 3“ and 4" graphics pipelines. But, Kelleher teachesa bridge (38,Fig. 3)
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`operative to transmit vertex data to each ofthe 1‘ (20A), 2"! (20B), 3" (20C) and 4" (20N)
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`graphics pipelines (col. 3, lines 22-23; col. 4, lines 9-14; col. 8, lines 56-65; col. 3, lines 46-50).
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`It would have been obviousto one of ordinary skill in the art at the time of invention by
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`applicant to modify MacInnis to include a bridge operable to transmit vertex data to each of the
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`first, second, third and fourth graphics pipelines because Kelleher suggests being able to convert
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`the vertex data to pixel data in parallel, which increasesthe efficiency of the graphics system
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`(col. 2, lines 31-35; col. 8, lines 56-65; col. 9, lines 1-23).
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`23.
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`As per Claim 24, MacInnis teaches a graphics processing circuit, comprising: front end
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`circuitry (90, Fig. 4) operative to generate pixel data in responseto primitive data for a primitive
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`to be rendered (col. 8, lines 49-59); back end circuitry (98), coupled to the front end circuitry
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`(90) (col. 9, lines 15-34), operative to process the pixel data in responseto position coordinates
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`(col. 9, lines 35-54). The front end circuitry (90) and the back end circuitry (98) are in the
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`graphics display pipeline (80) (col. 7, lines 55-63), and the graphics display pipeline (80)is
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`equivalent to display engine (58, Fig. 2), which is on graphics chip (10) (col. 4, lines 65-67; col.
`
`Ex. 3, p. 12
`
`Ex. 3, p. 12
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 13 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 13 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 12
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`5, lines 36-39). A memory controller (54) is also on graphics chip (10) (col. 4, lines 65-67; col.
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`5, lines 36-39). Therefore, the front end circuitry (90), the back end circuitry (98), and the
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`memory controller (54) are on the chip (10). The memory controller (54) is coupled to the
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`display engine (58) andis operative to transmit and receive the processed pixel data (col. 6, lines
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`10-13, 59-67; col. 7, lines 1-2). Since the display engine (58) is equivalent to the graphics
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`display pipeline (80) which contains the back endcircuitry (98) (col. 6, lines 59-67; col. 7, lines
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`55-63), the memory controller (54) is coupled to the back end circuitry (98) and is operative to
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`transmit and receive the processed pixel data.
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`However, MacInnis doesnotteach first back end circuitry operative to processa first
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`portion of the pixel data; set of tiles of a repeating tile pattern are to be processed bythe first
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`back end circuitry, the repeating tile pattern including a horizontally and vertically repeating
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`pattern of square regions; second back endcircuitry operative to process a second portion of the
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`pixel data; set of tiles of the repeating tile pattern are to be processed by the second back end
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`circuitry. However, Perego teaches graphics processing circuit (300, Fig. 3; col. 3, lines 61-63),
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`having front end circuitry (308) operative to generate pixel data in response to primitive data for
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`primitive to be rendered (col. 5, lines. 19-23); 1“ back endcircuitry (1“ rendering engine 312),
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`coupledto front end circuitry 308, operative to process 1* portion of pixel data (labeled “REO”in
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`Fig. 5) in response to position coordinates; set of tiles of repeating tile pattern are to be processed
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`by 1* backendcircuitry, repeating tile pattern including horizontally andvertically repeating
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`pattern of square regions, as shownin Fig. 5; 2" back end circuitry (second rendering engine
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`312), coupled to front end circuitry 308, operative to process 2™ portion ofpixel data (labeled
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`“REI” in Fig. 5) in response to position coordinates; set of tiles of repeating tile pattern are to be
`
`Ex. 3, p. 13
`
`Ex. 3, p. 13
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 14 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 14 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 13
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`processed by 2"! back endcircuitry (col. 3, line 63-col. 4, line 2; col. 5, lines 19-44); and
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`memory controller (310), coupled to 1“ and 2" back endcircuitry (312) operative to transmit and
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`receive processed pixel data (col. 3, lines 65-67; col. 4, lines 1-53; col. 5, lines 32-44). Perego
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`describes “Improvements in integrated circuit design and manufacturing technologies allow
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`higher levels of integration, thereby allowing an increasing numberof subsystems to be
`
`integrated into a single device. This increased integration reducesthe total number of
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`components in a system, such as a computer system. As subsystems with high memory
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`performance requirements (such as graphics subsystems) are combined with the traditional main
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`memory controller, the resulting architecture may provide a single high-performance main
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`memory interface” (col. 1, lines 34-43). Perego showsin Fig. 8 that in one embodiment, a
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`memory module 800 contains two different rendering engines 802 and 810 (Fig. 8; col. 6, lines
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`61-62), and therefore at least two graphics pipelines (802, 810) are on a same memory module
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`800. From Fig. 8 and from the description in Perego, one of ordinary skill in the art would
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`understand that a memory module is equivalent to a chip. Therefore, Perego teaches that two
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`graphics pipelines are on the same chip, andso the first back end circuitry and second back end
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`circuitry are on the same chip. Since MacInnis teachesthat the front end circuitry, the back end
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`circuitry and the memory controller are on the samechip, this teaching from Perego can be
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`implemented into the device of MacInnis so that the front end circuitry sends pixel data to both
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`the first back end circuitry and the second back endcircuitry, and the front end circuitry, thefirst
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`back end circuitry, the second back end circuitry, and the memory controller are on the same
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`chip. This would be obviousfor the reasons given in the rejection for Claim 1.
`
`Ex. 3, p.14
`
`Ex. 3, p. 14
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 15 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 15 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 14
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`However, MacInnis and Perego do not explicitly teach first scan converter and second
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`scan converter. However, Kelleher teaches first scan converter, coupled between front end
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`circuitry (14, Fig. 3) and first back end circuitry (update stage, Fig. 7 in 20A, Fig. 3), operative to
`
`determine whichsetoftiles of repeating tile pattern are to be processed by first back end
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`circuitry (col. 3, lines 22-23; col. 8, line 33-col. 9, line 23), and operative to provide position
`
`coordinates to first back end circuitry in responseto pixel data (col. 4, lines 60-62; col. 8, lines
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`52-65; col. 6, lines 36-38); second scan converter, coupled between front end circuitry and
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`second back end circuitry (update stage, Fig. 7 in 20B, Fig. 3), operative to determine whichset
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`of tiles of repeating tile pattern are to be processed by second back endcircuitry, and operative to
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`provide position coordinates to second back endcircuitry in response to pixel data (col. 3, lines
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`22-23; col. 8, line 33-col. 9, line 23; col. 4, lines 60-62; col. 8, lines 52-65; col. 6, lines 36-38).
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`Therefore, by implement this teaching into the device of Perego, front end circuitry, first back
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`end circuitry, and first scan converter of Perego-Kelleher combination make up one graphics
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`pipeline, and front end circuitry, second back end circuitry, and second scan converter of Perego-
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`Kelleher combination make up another graphics pipeline. Since Perego teaches graphics
`
`pipelines are on the samechip, the teaching from Kelleher can be applied to Perego so that the
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`first scan converter and the second scan converter are also on the same chip. This would be
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`obvious for reasons given in the rejection for Claim 5.
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`24.
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`Claims 6 and 17 are rejected under 35 U.S.C. 103(a) as being unpatentable over MacInnis
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`(US006570579B 1) in view of Perego (US006864896B2), further in view of Furtner
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`(US006778177B1).
`
`Ex. 3, p. 15
`
`Ex. 3, p. 15
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 16 of 21
`Case 6:22-cv-00466-ADA-DTG Document 50-3 Filed 12/19/22 Page 16 of 21
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 15
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`25.
`
`As per Claim 6, MacInnis and Peregoare