`
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 1 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 1 of 14
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`.
`
`FILING DATE
`
`FIRST NAMED INVENTOR
`
`:
`
`ATTORNEY DOCKET NO,
`
`CONFIRMATION NO.
`
`10/459,797
`
`06/12/2003
`
`_ Mark M. Leather
`
`00100.02.0053
`
`4148
`
`29153
`7590
`02/04/2008
`ADVANCEDMICRO DEVICES, INC.
`C/O VEDDERPRICE P.C.
`222 N.LASALLE STREET
`
`.
`
`HSU, JONI
`
`2628
`
`MAIL DATE
`
`02/04/2008
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL-90A (Rev. 04/07)
`
`Ex. 13, p. 1
`
`Ex. 13, p. 1
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 2 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 2 of 14
`Application No.
`
`Office Action Summary
`
`Examiner
`
`LEATHER ET AL.
`Art Unit
`
`2628
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address--
`Period for Reply
`A SHORTENEDSTATUTORYPERIOD FOR REPLYIS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`
`Extensionsof time may be available under the provisions of 37 CFR 1.136(a).
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended periodforreply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Anyreply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`In no event, however, may a reply be timelyfiled
`
`Status
`
`1)] Responsive to communication(s)filed on 28 November 2007.
`2a) This action is FINAL.
`2b)C] This action is non-final.
`3)L) Sincethis application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordancewith the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`4) Claim(s) 1-7,10-22,24 and 25 is/are pending in the application.
`4a) Of the above claim(s)
`_
`is/are withdrawn from consideration.
`5)L] Claim(s)__ is/are allowed.
`6)X] Claim(s) 1-7,10-22,24 and 25is/are rejected.
`7)L) Claim(s)___ is/are objected to.
`8)L] Claim(s)___ are subject to restriction and/or election requirement.
`
`Application Papers
`
`9)LJ The specification is objected to by the Examiner.
`10)L] The drawing(s)filed on
`is/are: a)[_] accepted or by objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is requiredif the drawing(s) is objected to. See 37 CFR 1.121(d).
`11)L] The oath ordeclaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
`
`Priority under 35 U.S.C. § 119
`
`12)(_] Acknowledgmentis madeof a claim for foreignpriority under 35 U.S.C. § 119(a)-«or (f).
`
`Applicant(s) .10/459,797
`
`a)L]All )(] Some * c)J Noneof:
`‘4.1 Certified copies of the priority documents have been received.
`2.L] Certified copies of the priority documents have been received in Application No.
`3.L] Copies ofthe certified copies of the priority documents have beenreceivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`1) EX) Notice of References Cited (PTO-892)
`2) (_] Notice of Draftsperson's Patent Drawing Review (PTO-948)
`3) JX] information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mail Date 11/28/07.
`U.S. Patent and Trademark Office
`PTOL-326 (Rev. 08-06)
`
`4) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date.__.
`5) L] Notice of Informal Patent Application
`6) C] Other:
`
`Office Action Summary
`
`,
`Part of Paper,No./Mail Date
`412807
`PeMBPB2
`
`Ex. 13, p. 2
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 3 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 3 of 14
`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`|
`
`Page 2
`
`DETAILED ACTION
`
`| Information Disclosure Statement
`
`1.
`
`Information disclosure statement (IDS) submitted on November 28, 2007 wasfiled after
`
`mailing date ofapplication on June 12, 2003. Submission is in compliance withprovisions of37
`CFR 1.97. Accordingly, information disclosure statement is being considered by the examiner.
`Response to Arguments
`
`2.
`Applicant’s arguments, see pages 9-11, filed November 28, 2007, with respectto the
`rejection(s) ofclaim(s) 1-4, 7, 10, 12, 14, 20-22, and 25 under 35 U.S.C. 102(e)and claims5,6,
`
`11, 13, 15-19, and 24 under 35 U.S.C. 103(a) have been fully considered and are persuasive. So,
`
`the rejection has been withdrawn. However, upon further consideration, a new ground(s) of
`
`rejection is made in view of Furtner (US006778177B1) and MacInnis (US006570579B1).
`
`3.
`~ Applicant argues Perego (US006864896B2) does not teach multi-graphics pipeline
`circuitry on same chip nor memorycontroller on the same chip but instead teaches discrete
`memory modules having separate and single graphics engines thereon. The memory controller
`taught in Perego is not ona same chip noris it part ofthe memory module (page 10).
`
`' In reply, new groundsofrejection are made in view of Furtner and MacInnis.
`
`Claim Rejections - 35 USC § 103
`
`-4,-
`
`The following is a quotation of 35 U.S.C. 103(a) which formsthe basisforall
`
`obviousnessrejections set forth in this Office action:
`
`(a) A patent may not be obtained thoughthe invention is not identically disclosed or described as set forth in
`section 102 ofthis title, if the differences between the subject matter sought to be patented andtheprior art are
`such that the subject matter as a whole would have been obviousat the time the invention was made to a person
`having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the
`mannerin which the invention was made.
`
`Ex. 13, p. 3
`
`Ex. 13, p. 3
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 4 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 4 of 14
`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 3
`
`- The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459
`
`(1966), that are applied for establishing a background for determining obviousness under 35
`
`U.S.C. 103(a) are summarizedas follows:
`
`PwWNPS
`
`Determining the scope and contents ofthepriorart.
`Ascertaining the differences between the priorart and the claims.atissue.
`Resolving the level of ordinary skill in the pertinent art.
`Considering objective evidence present in the application indicating obviousness .
`or nonobviousness.
`
`5.
`
`Claims 1-4, 6, 7, 10, 12, 14, and 17 are rejected under 35 U.S.C. 103(a) as being
`
`unpatentable over Perego (US006864896B2) in view of Furtner (US006778177B1), further in
`view ofMacInnis (US006570579B1).
`|
`
`6.
`
`As per Claim 1, Perego teaches graphics processing circuit (300, Fig. 3; c. 3, Il. 61-63).
`
`having at least 2 graphics pipelines (312) operative to process data in correspondingsetoftiles
`ofrepeating tile pattern correspondingto screen locations, respective one of at least two graphics
`
`pipelines operative to process data in dedicatedtile (c. 5, ll. 19-27, 38-44); and memory
`
`controller (310, Fig. 3) in communication with at least 2 graphics pipelines (312), operative to
`
`transfer pixel data between each of 1“ pipeline and gnd pipeline and shared memories (314)(c. 3,
`
`ll. 65-67; c. 4, Il. 1-10, 48-65). Shared memories (314) are each part ofmain memory (c. 1, Il. 44-
`54; c. 3, ll. 3-6), and so are considered to be one memory. Repeatingtile pattern includes
`horizontally and vertically repeating pattern of regions of square regions, as shown inFig.5 (c.
`
`5, ll. 19-27, 38-44).
`
`However, Perego does not teach that the graphics pipelines are on a same chip. However,
`
`Furtnerteachesthat the graphics pipelines are on a samechip (c.6, Il. 30-32).
`
`Ex. 13, p. 4
`
`Ex. 13, p. 4
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 5 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 5 of 14
`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 4
`
`It would have been obviousto one of ordinary skill in the art at the time of invention by
`
`applicant to modify device ofPerego so graphics pipelines are on same chip as Suggested by
`
`Furtner, Placing plurality of modules on single chip takes up less space as comparedto using
`multiple chips, and this is well-known in theart.
`However, Perego and Furtner do not teach memory controller is also on the same chip.
`However, MacInnis teaches memory controller (54) is on same chip (10) as graphics pipeline
`(58), as shown in Fig.2 (c. 4,ll. 65-67; c. 5, Il. 36-41; c. 6, Il. 10-13). This would be obvious for
`
`same reasons given above.
`7.
`As per Claim 2, Perego teaches square regions have two dimensional partitioning of
`memory (c.5,I. 19-33).
`|
`8.
`Asper Claim 3, Perego discloses that the memoryis a frame buffer (c.5, Il. 32-33).
`
`9.
`
`As per Claim 4, Perego teaches each ofat least two graphics pipelines includes front end
`
`circuitry (308, Fig. 3) operative to generate pixel data corresponding to primitive to be rendered,
`
`and back endcircuitry (312), coupled to front end circuitry, operative to receive and process
`
`portion ofpixel data (c.3, ll. 64-c. 4, Il. 2; c. 5, ll. 19-44). In order for front end circuitry (308) to
`
`generate pixel data, it must inherently receive vertex data.
`
`10.
`
`As per Claim 6, Perego does not explicitly teach eachtile of set of tiles has 16x16 pixel
`
`array. But, Furtner teaches eachtile of set of tiles has 16x16 pixel array (c. 11, ll. 45-48, 64-65).
`
`It would have been obviousto one of ordinary skill in the art at the time of invention by
`
`applicant to modify Perego so each tile ofset of tiles further has 16x16 pixel array because
`
`Furtner suggests depending on numberofparallel image-rendering pipelines and depending on
`memory organization, optimum tile size and shape can beselected (c. 11, Il. 45-48, 64-65), and
`
`Ex. 13, p. 5
`
`Ex. 13, p. 5
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 6 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 6 of 14
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`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 5
`
`so it would be obvious to modify tile size to be 16x16 pixels if that would be optimum tile size
`
`for particular numberofparallel image-rendering pipelines and particular memory organization.
`
`11.
`
`. As per Claim 7, Perego teachestheat least two graphics pipelines (312, Fig. 3) separately
`
`receive the pixel data from the front end circuitry (308) (c.3, Il. 64-c. 4,Il. 2; c. 5, Il. 19-44).
`
`12.
`Asper Claim 10, Perego teaches first of at least two graphics pipelines (first rendering
`engine of312, Fig. 3) processes pixel data only infirst set oftiles (tiles labeled “REO” in Fig. 5)
`
`in repeatingtile pattern (c. 5, ll. 23-44),
`
`13.
`
`As per Claim 12, Perego teaches second ofat least two graphics pipelines (second |
`
`rendering engine of 312, Fig. 3) processes pixel data only in second setoftiles (tiles labeled
`“REI” in Fig. 5) in repeatingtile pattern (c. 5, Il. 23-44).
`
`14. As per Claim 14, Claim 14 is similar to Claims4 and 10, except that Claim 14is for a
`
`third and fourth graphics pipeline. Perego teaches four graphics pipelines (c. 5, ll. 41-44). So
`
`Claim 14 is rejected under the same rationale as Claims 4 and 10.
`
`15.|As per Claim 17, Perego does not teach 3° and 4% graphics pipelines are on separate
`
`chips. However, Furtner teaches 3" and 4"pipelines are on separate chips(c.6, Il. 47-51).
`It would have been obviousto oneof ordinary skill in the art at the time ofinvention by
`
`applicant to modify Perego so pipelines are on separate chips because Furtner teaches this makes
`
`system more configurable by being able to easily add more graphics pipelines to increase
`
`performance(c.6,ll. 29-30, 42-51).
`
`16.
`
`Claims 5, 18, and 24 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Perego (US006864896B2), Furtner (US006778177B1), and MacInnis (US006570579B1) in view
`
`of Kelleher (US005794016A).
`
`Ex. 13, p. 6
`
`Ex. 13, p. 6
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 7 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 7 of 14
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`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 6
`
`17.
`
`Asper Claim 5, Perego, Furtner, and MacInnis are relied upon for teachings for Claim 4.
`
`But, Perego, Furtner, and MacInnis do not explicitly teach at each of at least two graphics
`
`pipelines further includes scan converter, coupled to back end circuitry, operative to determine
`
`portion of pixel data to be processed by back end circuitry. But, Kelleher teaches each ofat least
`
`two graphicspipelines (20A, 20B,Fig.3; c. 3, ll. 22-23; c. 4, ll. 9-14) further includes scan
`
`converter (update stage, Fig. 7), coupled to back end circuitry, operative to determine portion of
`
`pixel data to be processed by back endcircuitry (c. 8, ll. 52-61; c. 9, Il. 1-23; c. 6, Il. 26-28).
`It would have been obviousto one ofordinary skill in the art at the time of invention by
`
`applicant to modify devices of Perego, Furtner, and MacInnisso at each ofat least two graphics
`pipelines further includes a scan converter, coupled to the back end circuitry, operative to
`
`- determine the portion of the pixel data to be processed by the back endcircuitry, because
`
`Kelleher suggests scan converters are neededin order to define image data as array of pixels by
`
`calculating pixel addresses(c.9,Il. 1-23), as is well-known intheart.
`
`18.
`
`Asper Claim 18, Perego does not teach a bridge operable to transmit vertex data to each
`
`of the first, second, third and fourth graphics pipelines. However, Kelleher discloses a bridge
`(38, Fig. 3) operative to transmit vertex data to each ofthefirst (20A), second (20B), third (20C) |
`and fourth (20N) graphics pipelines (c. 3, Il. 22-23; c. 4, Il. 9-14; c. 8, Il. 56-65; c. 3, Il. 46-50).
`
`It would have been obviousto one of ordinary skill in the art at the time of invention by
`
`applicant to modify Perego to include a bridge operable to transmit vertex data to each ofthe
`first, second, third and fourth graphics pipelines as suggested by Kelleher because Kelleher
`
`suggests the advantage of being able to convert the vertex data to pixel data in parallel, which
`
`increasesthe efficiency of the graphics system (c. 2, ll. 31-35; c. 8, ll. 56-65; c. 9, Il. 1-23).
`
`
`
`Ex. 13, p. 7
`
`Ex. 13, p. 7
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 8 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 8 of 14
`
`Application/Control Number:
`10/459 797
`Art Unit: 2628
`
`Page 7
`
`19.
`
`As per Claim 24, Perego teaches graphics processing circuit (300, Fig. 3; c. 3, ll. 61-63),
`
`having front endcircuitry (308) operative to generate pixel data in response to primitive data for
`primitive to be rendered(c.5,ll. 19-23); first back end circuitry (first rendering engine 312),
`
`coupled to front end circuitry 308, operative to process first portion of pixel data (labeled “REO”
`
`in Fig. 5) in responseto position coordinates;setoftiles of repeating tile pattern are to be
`
`processed byfirst back endcircuitry, repeating tile pattern including horizontally and vertically
`
`repeating pattern of square regions, as shown in Fig. 5; second back endcircuitry (second
`rendering engine 312), coupled to front end circuitry 308, operative to process secondportion of
`
`pixel data (labeled “RE1”in Fig. 5) in responseto position coordinates; setoftiles of repeating
`tile pattern are to be processed by second back endcircuitry (c.3, ll. 63-c. 4, ll. 2; c. 5, Il. 19-44);
`
`and memorycontroller (310), coupled to first and second back end circuitry (312) operative to
`
`transmit and receive processed pixel data (c. 3,Il. 65-67; c. 4, IL. 1-53; ¢. 5, IL. 32-44),
`
`However, Perego doesnot explicitly teach first scan converter and second scan converter.
`
`However, Kelleher teachesfirst scan converter, coupled betweenfront end circuitry (14, Fig. 3)
`and first back end circuitry (update stage, Fig. 7 in 20A,Fig. 3), operative to determine which set
`oftiles ofrepeating tile pattern are to be processed byfirst back endcircuitry (c. 3, ll. 22-23; c. 8,
`
`Il. 33-c. 9, Il. 23), and operative to provide position coordinatesto first back end circuitry in
`
`responseto pixel data (c.4,Il. 60-62; c. 8, Il. 52-65; c. 6, ll. 36-38); second scan converter,
`
`coupled betweenfront end circuitry and second back endcircuitry (update stage, Fig. 7 in 20B,
`Fig. 3), operative to determine whichset oftiles ofrepeatingtile pattern are to be processed by
`second back endcircuitry, and operative to provide position coordinates to second back end
`
`Ex. 13, p. 8
`
`Ex. 13, p. 8
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 9 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 9 of 14
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`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 8
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`circuitry in responseto pixel data (c. 3,Il. 22-23; c. 8, ll. 33-c. 9, Il. 23; c. 4, Il. 60-62; c. 8, ll. 52-
`
`65; c. 6, ll. 36-38). This would be obvious for same reasonsgiven in the rejection for Claim 5.
`
`However, Perego and Kelleher do not teach front end circuitry, first back endcircuitry,
`
`first scan converter, second back endcircuitry, and second scan converterare all on samechip.
`However, Furtner teachesgraphics pipelines are on samechip(c.6,ll. 30-32). Front end
`
`circuitry, first back endcircuitry, and first scan converter of Perego-Kelleher combination make
`
`up one graphicspipeline, and front end circuitry, second back end circuitry, and second scan
`
`converter of Perego-Kelleher combination make up another graphics pipeline, as discussed
`above. Since Furtner teaches graphics pipelines are on samechip, this teaching from Furtner can
`
`be applied to Perego-Kelleher combinationso front endcircuitry, first back endcircuitry, first
`scan converter, second back endcircuitry, and second scan converter are all on samechip. This
`
`would be obvious for reasons for Claim 1.
`
`However, Perego, Kelleher, and Furtner do not teach memory controller is also on the
`same chip. However, MacInnisteachesthis limitation, as discussed in the rejection for Claim 1.
`
`20.
`Claims 11, 13, 15, and 16 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`Perego (US006864896B2), Furtner (US006778177B1), and MacInnis (US006570579B1) in view
`
`of Kelleher (US005794016A), further in view of Hamburg (US005905506A).
`
`Perego, Furtner, and MacInnis are relied upon for teachingsrelative to Claim 10.
`
`However, Perego, Furtner, and MacInnis do not explicitly teach scan converter.
`However, Kelleher teachesfirst of the at least two graphics pipelines(20A, Fig. 3; c. 3, Il. 22-23;
`
`c. 4, ll. 9-14) further includes scan converter (84, Fig. 7), coupled to front end circuitry (80, 82)
`
`and backendcircuitry (c.8,ll. 52-c. 9, 1]. 23). Scan converter determines which groups ofblocks
`
`Ex. 13, p. 9
`
`Ex. 13, p. 9
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 10 of 14
`Case 6:22-cv-00466-ADA-DTG -Document 50-13 Filed 12/19/22 Page 10 of 14
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`Application/Control Number:
`10/459,797
`Art Unit: 2628
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`Page 9
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`52 within graphics memory 22are allocated to and controlled by graphics pipelines (c. 8, I. 52-
`65; c. 6, ll. 26-28). Graphics memory is partitioned into plurality ofpixel blocks that are tiled in
`
`x-and y-direction of graphics memory (c.4,ll. 60-62). So, scan converter is inherently operative
`to provide memory addressesor position coordinates ofpixels withinfirst set oftiles to be
`processed by back endcircuitry. This would be obvious for reasons for Claim 5,
`
`But, Perego, Furtner, MacInnis, Kelleher do not explicitly teach usingtile identification
`
`data to indicate which tiles are to be processed. But, Hamburg teachespixel identification line
`
`for receivingtile identification data indicating which tiles are to be processed(c.5,Il. 35-52).
`
`It would have been obviousto one of ordinary skill in the art at the time of invention by
`
`applicant to modify devices of Perego, Furtner, MacInnis, and Kelleher to include usingtile
`
`identification data to indicate whichtiles are to be processed because Hamburg suggests
`
`advantage ofusingtile identification data to easily track storage locations oftile pixel data and
`being able to easily retrieve data for particular image tile (c. 1, ll. 46-54).
`
`21.
`
`Claim 19 is rejected under 35 U.S.C. 103(a) as being unpatentable over Perego
`
`(US006864896B2), Furtner (US006778177B1), and MacInnis (US006570579B 1) in view of
`
`Kent (US 20030164830A1).
`
`- Perego, Furtner, and MacInnis are relied on for teachings for Claim 17. Perego teaches
`data includes polygon(c.5, Il. 19-23). Furtner teaches third and fourth graphics pipelines are on
`
`separate chips(c.6,ll. 47-51), as discussed for Claim 17.
`
`But, Perego, Furtner, and MacInnis do not teach creating bounding box around polygon
`
`and each corner of bounding box is checked against supertile that belongs to each separate chip
`
`and if bounding box does not overlap any of supertiles associated with separate chip, then
`
`Ex. 13, p. 10
`
`Ex. 13, p. 10
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 11 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 11 of 14
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`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 10
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`processingcircuit rejects whole polygon and processes next one. But, Kent teaches graphics
`pipeline [0006] calculates bounding boxofprimitive and testing this against VisRect.If
`bounding box ofprimitive is contained in other P10’s supertile the primitive is discardedat this
`
`stage [0129]. Primitive can be polygon [0088]. Method usedis to calculate distance from each
`
`subpixel sample point in point’s bounding box to point’s center and comparethis to point’s
`radius, Subpixel sample points with distance greater than radius do not contribute to pixel’s
`
`coverage. Cost ofthis is kept low by only allowing small radius points hence distance calculation
`
`is a small multiply and by taking a cycle per subpixel sample per pixel within bounding box
`
`[0144]. Since method calculates distance from each subpixel sample point in point’s bounding
`box, this must include all corners ofbounding box. So, Kent teaches data includes polygon and
`
`graphics pipeline creates bounding box around polygon and wherein each corner of bounding
`box is checkedagainst supertile that belongs to graphics pipeline and if bounding box does not
`
`overlap any ofsupertiles, then processingcircuit rejects whole polygon and processes next one.
`
`It would have been obviousto one ofordinary skill in the art at the time of invention by
`
`applicant to modify Perego, Furtner, and MacInnis to include bounding box as because Kent
`
`suggests processing supertiles one at a time in orderto hide page break costs [0129, 0051].
`22.
`. Claims 20-22 and 25 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`Perego (US006864896B2)in view ofFurtner (US006778177B1).
`|
`
`23.
`
`Asper Claim 20, Perego teaches graphics processing method, comprising generating
`
`pixel data (c. 5, ll. 19-25), which is inherently generated in response to received vertex data;
`determining pixels within setoftiles ofrepeating tile pattern corresponding to screen locations to
`
`be processed by corresponding oneofat least two graphics pipelines (312, Fig. 3) in response to
`
`Ex. 13, p. 11
`
`Ex. 13, p. 11
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 12 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 12 of 14
`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 11
`
`pixel data, repeating tile pattern including horizontally and vertically repeating pattern of square
`
`regions, as shown in Fig. 5; performing pixel operations on pixels within determinedsetoftiles
`by corresponding oneofat least two graphicspipelines (c.5, ll. 19-44); and transmitting
`
`processed pixels to memory controller (310), wherein at least two graphicspipelines share
`
`memory controller (c. 3, ll. 65-c. 4, Il. 25; ¢. 5, ll. 31-44).
`
`However, Perego doesnotteach that the graphics pipelines are on a same chip. However,
`
`Furtner teaches graphics pipelines are on a samechip (c.6,I. 30-32), as discussed for Claim 1.
`
`24.
`
`As per Claim 21, Perego teaches determining pixels within set oftiles of repeatingtile
`
`pattern to be processed further comprises determiningset oftiles that corresponding graphics
`
`pipeline is responsible for (c.5, ll. 19-50).
`
` -As per Claim 22, Perego teaches determining pixels within set of tiles of repeatingtile
`25.
`pattern to be processed comprises providing position coordinates ofpixels within determined set
`
`of tiles to be processed to corresponding oneofat least two graphics pipelines(c. 5, ll. 19-44).
`
`26.
`
`Asper Claim 25, Perego teaches graphics processingcircuit (300, Fig. 3; c. 3, ll. 61-63)
`
`havingat least two graphics pipelines (312) operative to process data in correspondingsetoftiles
`
`of repeatingtile pattern correspondingto screen locations, respective one ofat least two graphics
`
`pipelines operative to process data in a dedicatedtile (c. 5, Il. 19-27, 38-44), wherein the
`
`repeatingtile pattern includes a horizontally and vertically repeating pattern of regions of square
`
`regions, as shown in Fig. 5 (c. 5, Il. 19-27, 38-44).
`
`However, Perego doesnotteachthat the graphics pipelines are on a same chip. However,
`
`Furtner teaches graphics pipelines are on a samechip(c. 6,Il. 30-32), as discussed for Claim 1.
`
`Ex. 13, p. 12
`
`Ex. 13, p. 12
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 13 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 13 of 14
`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 12
`
`Conclusion
`
`Applicant's amendmentnecessitated the new ground(s) ofrejection presented in this
`
`Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP §.706.07(a).
`Applicant is reminded ofthe extension oftime policyas set forth in 37 CFR 1.136(a).
`
`A shortenedstatutory period forreply to final action is set to expire THREE MONTHS
`
`~
`
`from the mailing date ofthis action. In the eventa first reply is filed within TWO MONTHSof
`
`the mailing date of this final action and the advisory action is not mailed until after the end of the
`THREE-MONTH shortenedstatutory period, then the shortenedstatutory period will expire on
`
`the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be
`
`calculated from the mailing date of the advisory action. In no event, however, will the statutory
`period for reply expire later than SIX MONTHSfromthe date ofthis final action. |
`| Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to Joni Hsu whose telephone numberis 571-272-7785. The
`examiner can normally be reached on M-F Bam-Spm.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Kee Tung can be reached on 571-272-7794. The fax phone numberfor the
`
`organization where this application or proceeding is assigned is 571-273-8300.
`
`Ex. 13, p. 13
`
`Ex. 13, p. 13
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 14 of 14
`Case 6:22-cv-00466-ADA-DTG Document 50-13 Filed 12/19/22 Page 14 of 14
`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 13
`;
`
`Information regarding the status ofan application maybe obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`maybe obtained from either Private PAIR or Public PAIR.Status information for unpublished
`applications is available through Private PAIR only. For more information aboutthe PAIR
`
`system,see http://pair-direct.uspto.gov. Should you have questions on accessto the Private PAIR
`
`system, contact the Electronic Business Center (EBC)at 866-217-9197(toll-free). If you would
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`like assistance from a USPTO Customer Service Representative or access to the automated
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`information system, call 800-786-9199 (IN USA OR CANADA)or 571-272-1000.
`
`JH
`
`KEE M. TUNG
`SUPERVISORY PATENT EXAMINER
`
`Ex. 13, p.14
`
`Ex. 13, p. 14
`
`