Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 1 of 11
`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 1 of 11
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicants: Mark M. Leatheretal.
`Serial No.: 10/459,797
`Filing Date: June 12, 2003
`Confirmation No.: 4148
`
`Examiner: Joni Hsu
`Art Unit: 2628
`OurFile No.: 00100.02.0053
`
`Title: DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING
`A SUPER-TILING TECHNIQUE
`
`Mail Stop Amendment
`Commissionerfor Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`DearSir:
`
`AMENDMENT AND RESPONSE
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`In response to the Office Action mailed August 28, 2007, Applicants respondas follows.
`
`Amendments to the Specification begin on page 2 of this paper.
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`Amendments to the Claims begin on page 3 ofthis paper.
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`Remarksbegin on page 9 ofthis paper.
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`CHICAGO/#1718760.1
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`1
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`Ex. 12, p. 1
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`Ex. 12, p. 1
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 2 of 11
`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 2 of 11
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`Amendments to the Specification:
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`Please replace paragraph [0001] with the following amended paragraph:
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`[0001]
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`This is a related application to a co-pending application entitled “Parallel Pipeline
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`Graphics System’—havine—deeket-number010025, having serial number 10/724,384, having
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`Leather et al. as the inventors, filed on even—date-November 26, 2003, owned by the same
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`assignee and hereby incorporated by referencein its entirety.
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`CHICAGO/#1718760.1
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`2
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`Ex. 12, p.2
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`Ex. 12, p. 2
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 3 of 11
`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 3 of 11
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`Amendments to the Claims:
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`Re-write the claims as set forth below. This listing of claims will replace all prior versions and
`listings, of claims in the application:
`
`Listing of Claims:
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`1. (currently amended) A graphics processing circuit, comprising:
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`at
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`least
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`two graphics pipelines on_a_ same chip operative to process data in a
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`corresponding set of tiles of a repeating tile pattern corresponding to screen locations, a
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`respective one of the at least two graphics pipelines operative to process data in a dedicatedtile;
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`and
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`a memory controller on the chip in communication with the at
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`least two graphics
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`pipelines, operative to transfer pixel data between each ofa first pipeline and a second pipeline
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`and a memory;
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`wherein the repeating tile pattern includes a horizontally and vertically repeating pattern
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`of square regions.
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`2.
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`(original) The graphics processing circuit of claim 1, wherein the square regions
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`comprise a two dimensional partitioning of memory.
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`3.
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`(original) The graphics processing circuit of claim 2, wherein the memory is a frame
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`buffer.
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`4.
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`(original) The graphics processing circuit of claim 1, wherein each ofthe at least two
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`graphics pipelines further includes front end circuitry operative to receive vertex data and
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`generate pixel data corresponding to a primitive to be rendered, and back end circuitry, coupled
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`to the front end circuitry, operative to receive and processa portion of the pixel data.
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`CHICAGO/#1718760.1
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`3
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`Ex. 12, p.3
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`Ex. 12, p. 3
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 4 of 11
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`5.
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`(original) The graphics processing circuit of claim 4, wherein each ofthe at least two
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`graphics pipelines further includes a scan converter, coupled to the back end circuitry, operative
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`to determine the portion of the pixel data to be processed by the back endcircuitry.
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`6.
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`(original) The graphics processing circuit of claim 1, wherein eachtile of the set of
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`tiles further comprises a 16x16 pixelarray.
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`7. (original) The graphics processing circuit of claim 4, wherein the at least two graphics
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`pipelines separately receive the pixel data from the front end circuitry.
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`8. (canceled)
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`9. (canceled)
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`10.
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`(original) The graphics processing circuit of claim 4, wherein a first of the at least
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`two graphics pipelines processes the pixel data only in a first set of tiles in the repeating tile
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`pattern.
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`11.
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`(original) The graphics processing circuit of claim 10, wherein the first of the at
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`least two graphics pipelines further includes a scan converter, coupled to the front end circuitry
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`and the back endcircuitry, operative to provide position coordinates of the pixels within thefirst
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`set of tiles to be processed by the back end circuitry, the scan converter including a pixel
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`identification line for receivingtile identification data indicating whichofthe setoftiles is to be
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`processed by the back end circuitry.
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`CHICAGO/#1718760.1
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`4
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`Ex. 12, p.4
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`Ex. 12, p. 4
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 5 of 11
`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 5 of 11
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`12.
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`(previously presented) The graphics processing circuit of claim 1, wherein a second
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`of the at least two graphics pipelines processes the data only in a second set oftiles in the
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`repeatingtile pattern.
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`13.
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`(previously presented) The graphics processing circuit of claim 12, wherein the
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`second of the at least two graphics pipelines further includes a scan converter, coupled to front
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`end circuitry and back end circuitry, operative to provide position coordinates of the pixels
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`within the second set of tiles to be processed by the back end circuitry, the scan converter
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`including a pixel identification line for receiving tile identification data indicating which of the
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`set of tiles is to be processed by the back endcircuitry.
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`14.
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`(original) The graphics processing circuit of claim 1
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`including a third graphics
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`pipeline and a fourth graphics pipeline, wherein the third graphics pipeline includes front end
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`circuitry operative to receive vertex data and generate pixel data correspondingto a primitive to
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`be rendered, and back end circuitry, coupled to the front end circuitry, operative to receive and
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`process the pixel data in a third set of tiles in the repeating tile pattern, and wherein the fourth
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`graphics pipeline includes front end circuitry operative to receive vertex data and generate pixel
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`data corresponding to a primitive to be rendered, and back end circuitry, coupled to the front end
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`circuitry, operative to receive and process the pixel data in a fourth set of tiles in the repeating
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`tile pattern.
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`15.
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`(original) The graphics processing circuit of claim 14, wherein the third graphics
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`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
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`circuitry, operative to provide position coordinates of the pixels within the third set of tiles to be
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`processed by the back end circuitry, the scan converter including a pixel identification line for
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`CHICAGO/#1718760.1
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`5
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`Ex. 12, p.5
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`Ex. 12, p. 5
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 6 of 11
`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 6 of 11
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`receiving tile identification data indicating which ofthe sets of tiles is to be processed by the
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`back end circuitry.
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`16.
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`(original) The graphics processing circuit of claim 14, wherein the fourth graphics
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`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
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`circuitry, operative to provide position coordinates of the pixels within the fourth set oftiles to
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`be processed by the back end circuitry, the scan converter including a pixel identification line for
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`receiving tile identification data indicating which ofthe sets of tiles is to be processed by the
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`back end circuitry.
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`17.
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`(original) The graphics processing circuit of claim 14, wherein the third and fourth
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`graphics pipelines are on separate chips.
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`18.
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`(original) The graphics processing circuit of claim 14, further including a bridge
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`operative to transmit vertex data to each ofthe first, second, third and fourth graphics pipelines.
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`19.
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`(original) The graphics processing circuit of claim 17 wherein the data includes a
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`polygon and wherein each separate chip creates a bounding box around the polygon and wherein
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`each corner of the bounding box is checked against a supertile that belongs to each separate chip
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`and wherein if the bounding box does not overlap any of the super tiles associated with a
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`separate chip, then the processing circuit rejects the whole polygon and processesa next one.
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`20. (currently amended) A graphics processing method, comprising:
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`receiving vertex data for a primitive to be rendered;
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`generating pixel data in response to the vertex data;
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`CHICAGO/#1718760.1
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`6
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`Ex. 12, p.6
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`Ex. 12, p. 6
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 7 of 11
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`determining the pixels within a set of tiles of a repeating tile pattern corresponding to
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`screen locations to be processed by a corresponding one ofat least two graphics pipelines ona
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`same chip in response to the pixel data, the repeating tile pattern including a horizontally and
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`vertically repeating pattern of square regions;
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`performing pixel operations on the pixels within the determined set of tiles by the
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`corresponding oneofthe at least two graphics pipelines; and
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`transmitting the processed pixels to a memory controller, wherein the at
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`least two
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`graphics pipelines share the memory controller.
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`21.
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`(original) The graphics processing method of claim 20, wherein determining the
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`pixels within a set of tiles of the repeating tile pattern to be processed further comprises
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`determiningtheset of tiles that the corresponding graphics pipeline is responsible for.
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`22.
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`(original) The graphics processing method of claim 20, wherein determining the
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`pixels within a set of tiles of the repeating tile pattern to be processed further comprises
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`providing position coordinates of the pixels within the determinedset of tiles to be processed to
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`the corresponding one ofthe at least two graphics pipelines.
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`23. (canceled)
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`24. (currently amended) A graphics processing circuit, comprising:
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`front end circuitry on a chip operative to generate pixel data in response to primitive data
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`for a primitive to be rendered;
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`first back end circuitry_on the chip, coupled to the front end circuitry, operative to process
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`a first portion of the pixel data in response to position coordinates;
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`CHICAGO/#1718760.1
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`7
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`Ex. 12, p. 7
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`Ex. 12, p. 7
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 8 of 11
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`a first scan converter_on the chip, coupled between the front end circuitry and the first
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`back end circuitry, operative to determine whichset of tiles of a repeating tile pattern are to be
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`processed by the first back end circuitry, the repeating tile pattern including a horizontally and
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`vertically repeating pattern of square regions, and operative to provide the position coordinates to
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`the first back end circuitry in responseto the pixel data;
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`second back end circuitry_on the chip, coupled to the front end circuitry, operative to
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`process a second portion of the pixel data in response to position coordinates;
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`a second scan converter_on the chip, coupled between the front end circuitry and the
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`second back endcircuitry, operative to determine whichset oftiles of the repeating tile pattern
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`are to be processed by the second back end circuitry, and operative to provide the position
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`coordinates to the second back end circuitry in responseto the pixel data; and
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`a memory controller_on the chip, coupled to the first and second back end circuitry
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`operative to transmit and receive the processed pixel data.
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`25. (currently amended) A graphics processing circuit, comprising:
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`at least two graphics pipelines on a chip operative to process data in a corresponding set
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`of tiles of a repeating tile pattern corresponding to screen locations, a respective one of the at
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`least two graphics pipelines operative to process data in a dedicated tile, wherein the repeating
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`tile pattern includes a horizontally and vertically repeating pattern of regions;
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`wherein the horizontally and vertically repeating pattern of regions include NxM number
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`of pixels.
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`26. (canceled)
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`CHICAGO/#1718760.1
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`8
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`Ex. 12, p.8
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`Ex. 12, p. 8
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 9 of 11
`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 9 of 11
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`Applicants respectfully traverse and request reconsideration.
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`REMARKS
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`Claims 1-4, 7, 10, 12, 14, 20-22 and 25 stand rejected under 35 U.S.C. § 102(e) as being
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`anticipated by U.S. Patent No. 6,864,896 (Perego). This is a new ground ofrejection. Perego is
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`directed to a scalable unified memory architecture and describes a “system...that provides
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`multiple discrete memory modules coupled to a common memory controller. Each memory
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`module includes a computing engine and a shared memory. A data processing task from the
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`memory controller can be partitioned among the different computing engines to allow parallel
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`processing of the various portions of the processing task.” (Column 7, lines 35-42) (emphasis
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`added). As such, Perego is directed to a system that employs separate and discrete memory
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`modules wherein each memory module includes a computing engine and corresponding shared
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`system memory and graphics memory.
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`In contrast, the amended independent claims require a multi-graphics pipeline circuit on a
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`same chip that is operative to process data in a correspondingset of tiles of a repeating tile
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`pattern corresponding to a screen location.
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`In addition, a memory controller on the chip is in
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`communication with the at least two graphics pipelines on the same chip to transfer pixel data
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`between each of the first pipeline and the second pipeline in the memory.
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`(See for example,
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`claim 1).
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`Perego describes a different system. For example, Perego requires multiple discrete
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`memory modules each with its own rendering engine and each with its own memory and shared
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`main memory. Such multiple memory modules require multiple chips and packages taking up
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`additional space and requiring additional signaling and synchronization operations and can be
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`more acceptable to electromagnetic interference.
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`In addition, a separate memory controller is
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`described as being a part of a different and separate memory controller subsystem/CPU 302 that
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`CHICAGO/#1718760.1
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`9
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`Ex. 12, p.9
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`Ex. 12, p. 9
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 10 of 11
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`is coupled “to four distinct memory modules 304”.
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`(See column 4, lines 26-36). Perego further
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`describes that the memory controller/graphics controller is responsible for distributing particular
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`processing tasks to the different rendering engines on different discrete memory modules.
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`Perego does not describe multi-graphics pipeline circuitry on a same chip nor a memory
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`controller on the same chip but instead describes discrete memory modules having separate and
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`single graphics engines thereon. In addition, the memory controller described in Perego is not on
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`a same chip noris it part of the memory module as described in Perego. As such, the Perego
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`reference does not anticipate Applicants’ claimed subject matter. Other differences will be
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`recognized by those of ordinary skill in the art.
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`The dependent claims add additional novel and non-obvious subject matter. For example
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`as to claim 4, the claim requires that each of the two graphics pipelines on a samechip include
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`front end circuitry that receives vertex data and generates pixel data corresponding to a primitive
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`to be rendered. The office action cites the CPU 308 as being the front end circuitry in Perego.
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`However as claimed, the multiple graphics pipelines on the same chip include the front end
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`circuitry, and not a separate CPU that passes information through a graphics controller as taught
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`in Perego. Accordingly, Applicants respectfully submit that this claim is also in condition for
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`allowance. The other dependent claims add additional novel and non-obvious subject matter.
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`Claims 5, 18, and 24 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over
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`Perego in view of Kelleher. Claim 24 requires front end circuitry on a chip andfirst and second
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`backend circuitry on the chip. The first and second backend circuitry processes different
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`portions of the pixel data in response to position coordinates. A memory controller on the same
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`chip is also coupled to the first and second backend circuitry.
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`In this example, commonfront
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`end circuitry is used on a chip for multiple backend operations. Again, the Perego reference
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`CHICAGO/#1718760.1
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`10
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`Ex. 12, p. 10
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`Ex. 12, p. 10
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`Case 6:22-cv-00466-ADA-DTG Document 50-12 Filed 12/19/22 Page 11 of 11
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`illustrates a completely different structure and does not describe multiple backend circuitry on a
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`common chip nor common front end circuitry and memory controller on a common chip as
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`claimed. As such, the claim is also in condition for allowance. Also, these claims add additional
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`novel and non-obvious subject matter.
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`Claims 6 and 17 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over
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`Perego in view of Furtner. Applicants respectfully reassert the relevant remarks made above and
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`as such, these claimsare also in condition for allowance.
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`Claims 11, 13, 15 and 16 stand rejected under 35 U.S.C. § 103(a) as being unpatentable
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`over Perego in view of Kelleher, further in view of Hamburg. Applicants respectfully reassert
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`the relevant remarks made aboveandas such, these claimsare also in condition for allowance.
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`Claim 19 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Perego and
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`Furtner in view of Kent. Applicants respectfully reassert the relevant remarks made above and
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`as such, this claim is also in condition for allowance.
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`Applicants respectfully submit
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`that
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`the claims are in condition for allowance and
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`respectfully request that a timely Notice of Allowance be issued in this case. The Examineris
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`invited to contact the below listed attorney if the Examiner believes that a telephone conference
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`will advancethe prosecution ofthis application.
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`Respectfully submitted,
`
`By: /Christopher J. Reckamp/
`Christopher J. Reckamp
`Registration No. 34,414
`
` Date: November28, 2007
`
`Vedder, Price, Kaufman & Kammholz, P.C.
`222 North LaSalle Street, Suite 2600
`Chicago, Illinois 60601
`phone: (312) 609-7599
`fax: (312) 609-5005
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`CHICAGO/#1718760.1
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`11
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`Ex. 12, p.11
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`Ex. 12, p. 11
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