Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 1 of 17
`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 1 of 17
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`EXHIBIT 7
`EXHIBIT 7
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 2 of 17
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`l)()C.~KE~l' N(). CH)l00.02.0053
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`IN THE lJNJTED STATES PATENT AND TRADEMARK OFFICE
`
`App!icam.s: J'vlark i'vl. Leather et al.
`Serial No.: l\}/45~\'"797
`Filing Date: June 12, 2003
`Confirrnur.1on No.: 4148
`
`Examiner: Joni Hsu
`Art Unit: 2628
`Our File No.; 00100.02.0053
`
`Title: DIVIDING WORK AMONG 1\-lULTlPLE GRAPIHCS PlPEUNES tJSING
`___ A_SUPER-TffJNG_TECHNIQUE
`...................
`...........
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`i'vlail Stop .l\111cndrnent
`Comrnissioncr frlr Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`AMENDMENT AND RESPONSE
`
`Dear Sir:
`
`In response to the Office Action mailed February 9, 2007, Applicants petition for a one
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`month extension of time and subrnit the following response.
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`Amendments to the Claims are reflected in the Listing of the Claims, which begins on page 2
`of this paper.
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`Remarks l:x~gin on page 8 of this paper.
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`AST0000729
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 3 of 17
`PATENT
`DOC KE NO. 00 l OOJ;:!.0()53
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`Amendments to the Claims:
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`Re-write the claims as set forth below. This listing of claims \vill rep1acc all prior versions and
`listings, of c1uims in the application:
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`~Jsting of Claims:
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`l. ( c:..rrrcnt!y amended) A graphics processing circuit, comprising:
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`at least t\vo graphics pipelines operntivc to process data in a corresponding set of tiles of
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`a repeating tile pattern com.:sponding to screen locations, a respective one of the at least two
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`a me1norv_co11troller_in commlmication with the _HUeast twugraphics __ pipchncs, operative
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`to transfcr_pixcl_data _betv,reen each of a_tirst_ nipebneand a secondpipcline_ and_ a_mernor_y;_
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`\vhcrcin the repeating tile pattern includes a horizontatly and vertically repeating pattern
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`of squa:re regions.
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`2.
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`(original) The graphics processmg circuit of claim l, \vhctein the square regions
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`corn prise a tvvo dimensiunal pmiitioning of memory.
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`l)ttffcr.
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`graphics pjpdines ftu-ther includes front end circuitr_y operative to receive vertex data and
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`generate pixel data corresponding to a pnmitivc to he rendered,. and back end circuitry, coupled
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`to the front end circuitry, operative to receive and process a pmiion ofthc pixel data.
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`AST0000730
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 4 of 17
`P1\TEN'I.
`l)f)C:KE .. l, "I\i(). OfJ100,0:2.{)053
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`5. ( original) The graphics processing circuit of claim 4, \.Vhcrefr1 each of the at least two
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`graphics pipelines further includes a scan converter, coupled to the back end circuitry, operative
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`to detcnninc the portion of the pixel data to he processed by the back end circuitry.
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`6. ( original) The graphics processing circuit of claim l, whcrcm each tile of the set of
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`tiles further coniprises a 16x16 pixel array.
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`I. ( onginal) The gn1phics processing circuit of claim 4, wherein the at kast tv,;o graphics
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`1)ll)CLincs separatdv receive the nixcl data from the front end cin:uitrv.
`t
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`..
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`•'
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`~
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`9. ( ca~nceled)
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`10. (original) The graphics processing circuit of claim 4, wherein a first of the at kast
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`two graphics pipelines processes the pixel data only in a first set of tiles in the repeating tile
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`pattern.
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`11 4
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`(or1g.inal)
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`'T'hc grap11ics f)rocessn1g circuit of clairn 10~ \vhcrcin the first of the at
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`least two graphics pipelines further includes a scan converter, coupled to the frnnt end circuitry
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`and the back end circuitry, operative to provide position coordinates of the pixels \Vi thin the first
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`set of tiles to bi;; processed by the back end circuitry, the scan cunvcrtcr including a pixel
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`identification line fix receiving tile identification data indicating which of the set of tiks is to be
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`processed by the hack end circuitr:,'.
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`AST0000731
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 5 of 17
`Pi\TFNT
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`(previously presented) The graphics processing circuit of claim 1, wherein a second
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`of the at least two graphics pipelines processes the data only 111 a second set of tiks in the
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`LL
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`(pn.~viously presented) The graphics processing circuit of cbim 12, wherein the
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`second of the at least t\VO graphics pipelines further includes a scan converter, coupled to front
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`end circuitry and back end circuitry, operative to provide position coordinates of the pixels
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`vvithin the second set of tiles to be processed by the back end circuitry, the scan converter
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`including a pixel identification line for receiving tile identification data indi<.:aling \vhich of the
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`set oftiks is to be processed by the back end circuitry.
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`14. { original) The graphics prncessmg circuit of claim 1 including a third graphics
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`pipeline and a frmrth graphics pipeline, wherein the third graphics pipeline includes front end
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`circuitry operative to receive vertex: data and generate pixel data corresponding to a primitive to
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`be rendered, and back end circuitry, coupled to the front end circuitry, operative tu rccei vc and
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`process the pixd data in a third set of tiles rn tbe repeating tile pattern, and -wherein the fourth
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`graphics pipeline includes front end circuitry operative to receive ve1iex data and generate pixel
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`data corresponding to a primitive to be rendered, and back end circuitry, coupled to the front end
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`circuitry, opcrntive to receive and process the pixel data in a fourth set of tiks in the repeating
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`ti le pattern.
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`15, (origirrnl) The gn.iphics processing circuit of claim 14, wherein the third graphics
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`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
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`circuitry, operative to provide position coordinates of the pixels \vi thin the third set of tiles to be
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`processed by the back end circuitry, the scan converter including a pixd identification !inc for
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`ClnC t\G(;/# i 642325. l
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`4
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`AST0000732
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 6 of 17
`P:\TENT
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`receiving tile identification data indicating \Vhkh of the sets of tiles is to be processed hy the
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`back end circuitry.
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`16. {original) The graphics processing circujt of claim 14, wherein the frmrth graphics
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`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
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`circuitry, operative to provjdc position coordinates of the pixels within the frirn1h set of tiles to
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`be processed by the back end circuitry, the scan converter including a pixel identification Enc for
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`reccjving tik identification data indicating which of the sets of tiles is to be processed by the
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`back end circuitry.
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`17. (original) The graphics processing circuit of claim 14, -,vhen:.~m the third and fourth
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`graphics pipelines an.' on separate chips.
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`J 8.
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`(original) The graphics processing circuit of cLirn 14, hnther including u bridge
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`operative to transmit vc1icx data to each of the first second, third and fourth graphics pipelines.
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`polygon and \Vhcrcin each separate chip creates a bounding box around the polygon and wherein
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`nnd wherein if the bounding box does not overlap any of the super tiles associated with a
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`separate chip, then the processing circuit rejects the whole polygon and processes u next one,
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`20. (currently umcndcd) A graphics processing method, cornprising:
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`ge11eratint; pixel data in response to the vt~rtcx duta~
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`AST0000733
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 7 of 17
`Pl\'TFN1'
`DOCKET NO. OUlUO.OJ.U053
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`deterrnining the pixds \Vithin a set of tiles of a repeating tile pattern corresponding to
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`screen locations to be processed by a co1Tesponding one of at least t',VO graphics pipelines in
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`response to the pixel data, the repeating ti1e pattern including a horizontaHy and ve1iical!v .,
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`pcrfom1ing pixel opcrntions on the pixels within the detern1ined set of tiles
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`the
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`corresponding one uf the at least two graphics pipelines_; __ ;rni:l
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`2 l.
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`(original) The graphics processing method of clairn 20, wherein detennining the
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`pixels withi11 a set of bks of the repeating tile pattern to be processed further con1pnses
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`determining the set of tiks that the corresponding graphics pipeline is responsible for.
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`'"J'!
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`( original)
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`·-rhe gra1)hics 11roccssi11g _rncthod of c.lai111 20~ \\•<hcrefn dctcrrr.lirllng the
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`pixels \vithin a set of tiles of the repeating tile pattern to be processed further comprises
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`providing position coordinates of the pixels \.Vi thin the determined set of tiles to be processed to
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`the corresponding un,:;; of the at least tv,,.-o graphics pipelines.
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`24. (previously presented) A graphics processing circuit. comprising:
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`front end circuitry operative to generate pixel data in response to primitive data for a
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`primitive to be rcnd,:;;red;
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`first hack end circuitry, coupled to the ii.-ont end circuitry, operative to process a first
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`portion of Hw pixel data in response to position coordinates;
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`6
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`AST0000734
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 8 of 17
`PA.TENT
`DOCKET NO. iJOlOOJC 0053
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`a first scan converter, coupled hct\veen the front end circuitry and the first back end
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`circuitry, operative to detcrrnine which sd of tiles of a repeating tile pattern are to be processed
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`back end circuitry i11 resr)o11se to the p_ixcl tiata;
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`second bc1ek. end circuitry, coupled to the front end circuitry, opcrntivi:. to process a
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`second ponion of the pixel data in response to position coordinates;
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`a second scan converter, coupled between the front end circuitry Hnd the second back end
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`circuitry, operative to determine which set of tiles of the repeating tile pattern arc to be processed
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`by the second back end circuitry, and operative to provide the positiun coordinates to the second
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`back end circuitry in response to the pixel data; and
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`a memory controller, coupled to the first and second back end circuitry operative io
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`transmit and receive the processed pixel data.
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`25. ( cun-ently mne11dcd) A graphics processing circuit, comprising:
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`at least two graphics pipelines operative to process data in a corresponding set of tiles of
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`a repeating bk pattern corresponding to screen locations, :1 respective one of the at !cast two
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`graphics pipelines operative to process d:ita in a d1xlicatcd tile, wherein the repeating tile pnttem
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`includes a horizontally and ve1iically repeating pattern of regions;
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`26. (canceled)
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`AST0000735
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 9 of 17
`t-'A'lTN·r
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`Clajms l "26 arc now pending in the application. Applicants rcspectfo!ly trnversc and
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`REMARKS
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`request reconsidcratior1.
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`Claim 25 stands objected to because it is allegedly exactly the smne as claim 1 and ,s
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`thcrdi.)n:: a repeated claim. Applicants respectfully pnint out that claim l includes a "repeating
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`regions" (without the limitation that those regions be square). Furthennore, Applicants have
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`amended claim D
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`tn incorporate the limitation of claim 2.6 into claim 25, as noted below.
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`Therefore, Applicants respectfully request that the objection be withdrawn.
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`Claims 20-23 stand rejected under 35 U.S.C. § 101 f()r allcgcd!y being directed to non-
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`statutory subject matter. As an initial matter, Applicants note that claim 23 has been canceled
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`without prejudice, thereby rendering this r~jection moot as to c]airn 23.
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`With regard to claim 20, the Examiner rncrcl-:i states that the graphics processing rncthod
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`does not yield a ''usefol, concrete and tangible result.'' The Exarnincr merely provides a
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`ccmcl usive statement that the claims allegedly constitute non-statutory subject rnattcr without an
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`explanation J'.~ to why the claims allegedly constitlltc non-statutory subject 1n;.Jter.
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`Applicants object to this rejection for at least the reason that no explanation has been
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`gt ven us to why the afi:)rernentioned claims arc non-statutory, Accordingly, a prima _(acie case
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`has not been established .. A_pp]icants kindly remind the Oilice that tviPEP §2 l 06(1\/)(B) states
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`the exarniner idc111j_fi_i;;~_u,md explain~ in the record the basis frir \vhy a claim is form, abstract idea
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`with no practical application, then the burden shills to the applicant to either mnend the dairn or
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`make a showing of why the claim is eligible for patent protection." fv1PEP §2106( !V)(D}.
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`8
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`AST0000736
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 10 of 17
`PATEN!
`DOCKET NO. ()0100.0:2.0053
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`in addition, the Examiner states that the claimed method fails to yield a useful, concrete,
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`and tangible resuit. Ho,.vever, according the Federal Circuit, patentable subject rnatter includes a
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`"pro;.;ess if the claimed invention .~I!? ... ?.: .. \Y.b~~AY- is applied in a 'uscti.11' manner.''' AT&J' C'orp. v.
`
`E\ce! ('ommwiica!ions, Inc., 172 F.3d 1352, 1357 (Fed. Cir. 1999). A proper inquiry requires
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`"an ex.mnination of lhc contested clairn.s to sec if the claimed subject matter as _a_\vholc is ... a
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`'law of nature' or an 'abstract idea, or if the ... concept has been reduced to some practical
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`application rendering it 'uscfo]' ."
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`id.
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`1n addition, IvlPEP §2 l06(l V)(C) states that ''[f!n
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`evaluating \Vhether a claim meets the requirements of section l O l ., the clairn must be considc1-ed
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`as . .a .. wholc to determine whether it is for a particular application of an abstract idea, natural
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`pl1eno1rwnon, or lavv of nature, rather than for an abstract idea, natural phenomenon, or li.:-vV of
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`nature.'' Therefore, the daimed invention as a whole should yield a usd:.1l, concrete, and
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`tangible resuiL
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`Applicants respectfully submit that at least independent claim 20 recites statutory subject
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`the same input data for the primitive to be rendered wi1l ahvays produce the san,e processed
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`pixds), w:;efrd ( c,g., bas a practical utility), and has a real world, tangibk result. For cxmnplc,
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`Applicants present a method for perfrmI1ing graphics processing that compnscs .. arnong other
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`things, transrnitting processed pixels to a memory controller.
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`For such subject matter to be statutory, the claimed process must be li:nited to a prnctical
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`application of the abstrnct idea or mathematical aigorithm in the tcclmological arts.
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`1n re
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`Aiappat, 33 F.3d 1526, 1543 (Fed. Cir. 1994). A clairn is Limited to a practical applicttion when
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`the nicthod, as clainied, produces a concrete, tangible, and useful result AT&T Corp., l 72 F.3d
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`at 1357.
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`In AT&T foe clai1ns in question \Vere directed to generating a rnessagt.'. record for an
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`9
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`AST0000737
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 11 of 17
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`interexchange cal 1 hct\vccn an originating suhsc1iher and a tcnn1nating subscriber and adding a
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`non-
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`aostract resu t HJ.at raci 1tatcs c r H:rentia tn l mg o · ong-mstancc cal s mace ))' a ... sunscn Der.
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`id. at 1358) Likewise, a machine claim is statutory when the machine, as cfoirned, produces a
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`concrete, tangible and useful result (as m State Street Bank & Trust
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`v. S'ig:natt{re f-/inrtncial
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`(;t'OUj'.J,,
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`!f'zc.~ 149 F.3d 1368, 1373 (Fed. c:ir. 1998)).
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`llo\VC'<''Cr~ the analysis 1s the sa111e
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`regardless of ,vhcther the claim is directed to a machine or a process.
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`ln State Street, the Federal Circuit reviewed a claim directed to a '\lat.i processing systcrn
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`t()r rrnmaging a financial services configuration of a portfrilio established as a partnership, each
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`partner being one of a plurality of funds, comprising" a variety of structural components
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`including u ''fifth rncans for processing data regarding aggregate year-end income, expenses, and
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`capita! gain or less for the portfolio and each ofthc funds.'' id. at 1371--72. The Federal Circuit
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`held that:
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`[ tjhe transformation of data, representing discrete dollar m11olmts, by a
`machine through a series of mathematkal culcu!ations into a final share
`price, constitutes a practical application of a niathernatical algorithm,
`frinnula, or cakuiation, because it produces ·a useful, concrete and
`tangible result' ··· a final share price momentarily fixed frir recording and
`reporting purposes and even accepted and rdied upon by regulatory·
`authorities and in subscque11t !n:1tfos. Id. at 1373.
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`Notably, the clairri did not require that the tangible result \Vhich was the share price, be t:.!aimed
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`or produced. The mere fact that the State Street claim required "processing data" regarding
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`expenses etc. \Vas enough to be considered statutory subject matter. Thus, at least according to
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`the Federal Circuit, a claim need not expressly recite a result that is uscfuL co11crctc, and tangible
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`in a last step or any,vhere else in order to be considered statutory subject matter. The fact that
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`C'HfC:'\GO/Nl642.)25.1
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`AST0000738
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 12 of 17
`J);\~l'TiN'l'
`I)()(~1(1~·r N{J. 0010(;_()2.0053
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`the claimed process led to or a1h)'>Ved for a recorded, accepted, and/or relied upon result \Vas
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`sufficient to establish compliance \Vith 35 U.S.C. ~ JOL
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`\Vhilc n:ethod claims take a diflercnt frrrm than a machine claim, foe Lict that ;\pplic,mts
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`claim rncthods and not rnachincs, as presented in State Streer, has no impact on the present
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`opinion notes that the dai1n is directed to a machine has no weight on the instant analysis.
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`things, generating pixel datu in response to the vertex data and pcrfonning pixel operations on
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`the pixels within the dctcm1incd set of tiles by the corresponding one of the at least two gm phi cs
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`pipelines. Simi1ar to the claimed invention in State Street, Applicants' ciai1ned subject inatter is
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`directed
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`once but
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`generating p1xcl data in
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`response to the vertex data and pcrh,rming pixel operations on the pixels. For at icast this
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`reaso.rt claim 20 appears to be directed to a practical application of the section 101 judicial
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`exception. Therefore, reconsideration and withdrawai of the rejection of claim 20 is respectfully
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`requested.
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`Dcpcn1.knt claims 21-22 arc believed to also he directed to statutory subject ni.atier f(.w the
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`same or similar reasons as provided above. Therefr)re. reconsideration and \Vithdrnwal of the
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`rejection cf daims 21-22 is respectfully requested.
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`Claims 1-5,. 7, 9, 10, 12-16, 18, and 20-26 stand rejected under 35 U.S.C. § l02(b) as
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`being anticipated by U.S. Patent No. 5,794,0l 6 ("Kelleher"). Kelleher is generally directed to a
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`parnlkl-processor graphics architecture appropriate for rnultin1edia graphics workstations that is
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`scalable to the needs of a user. {Abstract.) As sho\vn in FIG. 3, iix cxarnplc, N separate
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`rcndc1ing processors '.20 each implement graphics and multimedia algorithms and interface \Vith
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`11
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`AST0000739
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 13 of 17
`PATENT
`l)()C(I<ET N(). 00 l OU.U2.0(J53
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`the PC! bus 30 ami all other components ofihe system 10. (Col. 3, line 65 ···· coL 4, line l.) Each
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`separate _ _processor 20 __ has its __ own bus _ _32 coupled to its.own SDRAM __ chip _ _42.
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`In other words,
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`graphics memory 22 is composed of a p1urabty of rnemory SDRAM chips 42, 'vVherein each
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`SDRAM chip 42 is coupled lo at most one processor. As described in col. 4, lint:'.S 42-59, among
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`other places, Kelleher teaches that it is beneficial to provide each processor v:ith jts O\.vn mernory
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`chip{s) and O\vn bus lo the n-,emory ehip(s) improves perfrmnancc by, arnong other things,
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`dfrninating dependencies among the processors. In contrast, Applicants' claimed subject matter
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`pixel data betvvcen each of a first pipeline and a second pipeline and a memory.'' (Emphasis
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`added.)
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`.Applicants have canceled claim 9 and incorporated the limitations of the originally fikd
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`claim 9 into claim 1. As such, Applicants i-Vill only address the rejection as to claim 9.
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`Applicants have also c,rncded claim 8 without prejudice.
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`The Examiner suggests that Kelleher "discloses a memory controller (68, Figures 7 and
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`4, lines 9--14), operative to transfer pixel data between each of a first pipeline and a second
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`pipcli11c and a rnc111ory· (22) (adtires.5 ,generation circ1.1il 68 at..".?CC(Jts tlu.:· lnilial J?,4eo1rtetr:v values
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`JOrm tr1e geomc!nc setup c1rct11! 01_1, ana generates p 1ys1cul memo/Ji ac.c.resses,
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`23: Col. 10, lines 40-47).'' Applicants respectfully disagree that Kelleher discloses a mcinory
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`controller l'.Oupkd to at least t\No graphics pipelines. Instead, A.pplicants submit that KeHeher, in
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`-·.
`frict., shows each nrocessor f,e.~r., the oi1;dine of each processor)·. counlcd to onlv one bus, which
`...
`....
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`~
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`~
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`-
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`couples one processor 20 to one SDRAM 42 or SDRAM set through one meinor-::,,· controller.
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`For example, the Examiner suggests that 68 1s a memory controller, but as shown in FlGs. 7 and
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`AST0000740
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 14 of 17
`PAI t·:NT
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`l l, address generator 68 is inside one processor 2U. Kelleher teaches that "the rendering
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`processor 20 provides £1 videg_gip2Un~ for multimedia applications" (emphasis added); Kelleher
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`does not leach that each rendering processor 20 contains multiple pipelines. Thercfrnc, since
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`each address generator is within each processor 20, it is clear that each ,;'memory controller'' in
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`Kelleher is not coupled to the at !east 1\'i~'. graphics pipelines. Applicants fru-ther point out that
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`FKi. 4, for example, shows that each graphics mernory 22 is partitioned into PlJY.fi.f.~iJ. rnemory
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`scg.rncn1s 42, with each memory segment 42 being coupkd to a different processor 20 via its
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`Thus, Kelleher does not teach "a memory ccmtrol1er coupled to the at k:1st two graphics
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`pipelines, operative to transfor pjxc! data between each of a first pipeline and a second pipeline
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`and a rnernory.'' Thercfim~, claim l is in condition fix allov,,ance. The dependent claims add
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`nov(.J and nonobvious subject matter and are therd<.ffe also in condition for alhl\vnnce.
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`/\s to clai-m 20, Applicants have an1ended the claim to include the step of transmitting the
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`processed pixds to a memory controller, wherein the at least two graphics pipelines share the
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`memory controller. !\ppLicants therefi.m.:: respectfully reassert the relevant remarks made above
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`with respect to daim 1, and therefore respectfu!1v submit that the claim is in condition t<.1r
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`•
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`.I
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`allowance. The dependent claims add novd and nonobvious subject rnatkr and arc therefore
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`also in condition for allcrwance.
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`As to cbin1 24, Applicants respectfully submit tlu,t Kdkher docs not disclose the
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`claimed subject rnatter. For example, the Exan1iner states that Kelleher disdoses a graphics
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`processing circuit ''comprising front end circuitry ( 80, 82,, Figure 7) .
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`first back end circuitry
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`(84) ... " The clairned subject matter, also includes a first. scan converter ,md a second scan
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`converter, both coupled. between the front end circuitry and a back end circuitry. Nuthing the
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`AST0000741
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 15 of 17
`FATEN'l
`DOCKET NO. no l 00.02.0053
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`Examiner cites, however, nor does Kelleher disclose an)T\Vherc else, as best understood, discloses
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`a first ~rnl a second scan converter both coupled to the front end circuitry. Ai best, Kelleher
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`discloses nrnltipk processors 20, each of \vhkh rnay have its own front end circuitry and a scan
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`converter.
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`The claimed subject matter also includes "a men10ry contrdkr,. coupled to foe first and
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`second hack end circuitry operative to transmit and receive foe processed pixel data." Thus,
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`even if the processors did share front end circuitry (which is not disclosed), the processors, and
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`thercfi.)rc the first and second back end circuitry, do not share H mernory controller frn- the
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`reasons submitted above with respect to clairn l. Therefore, clairn 24 is in condition for
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`allowance.
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`As to dajrn 25, Applica11ts have amended the claim to i11corporate the limitations of
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`discloses a hur1zorital]y and vc1iically repeating pattern of regions (Col. 4, line 65-CoL 5, Ene
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`19) include NxM number of pixels (eachpi:re! block 52 is i28xl28 pL1.ds in size, Col. 6, lines 2-
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`4)." As the Office Action notes, however. Kelleher teaches that each block is smmre: 128 }Jixds
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`...
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`-
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`'
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`-
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`by l 28 pixels. This is contrary to Applicants' clahned subject matter, v,rhich claims ,1 region that
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`include NxM number of pixels. Since Kelleher, as best understood, docs not teach any blocks
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`that arc not square, claim 25, as amended, is in condition fi:)r al!O\vancc, and App!icunts
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`rcspcctfu1ly request that the rejection he withdrawn.
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`Claims 6, 8, and 17 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over
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`Kelleher in vie,.v of U.S. Patent No. 6,778,177 ("Funner:"). As noted above, Applicants havt:
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`canceled claim 8 and have an1ended claim l, the clain1 from which claim 6 and l 7 ultimu.tdy
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`depend, so that it now includes the lirnitations of clafrn 9. Thus, this rejection is moot and
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`CHiCAGO/if 164}325. !
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`14
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`AST0000742
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 16 of 17
`PATEN'['
`DOCK.FT NO. 0010().()2.0053
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`Applicants respectfully resubmit the relevant reniarks made above as to dairn l. Therefore,
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`daims 6 and 17 are in condition h.1r allmvance.
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`Claim 11 stands rejected under 35 U.S.C. § 103(a) as being unpatentubk over Kelleher in
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`view of U.S. Patent No. 5,905,506 ("Hamburg"). As noted above, Applicants have amended
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`V.\(~~-\~ ~ from \vhich claim 11 ultimately depends, so thm it no\v indudes the
`claim l, the ,-.. l q~<',....,
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`limitations of c]ain1 9. Thus, this rejection is moot, and. Applicants respectfully resubmit the
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`relevant remarks made above as to claim l. Therefore, claim 11 is in condition for allowance.
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`and Furtner in vie\v of U.S. Patent Applkafam No. 2003/0164830 ("Kent"). As noted above,
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`Applicants have arnended claim l, the claim from ,vhich daiTn 19 ultirnatcly depends, so that it
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`now includes the lirnitations of claim 9. Thus, this rejection is moot, and Applicants respectfully
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`resubrnit the relevant n.'.marks made a.hove as to claim 1. Therefore, claim 19 is in condition fr,r
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`allowance.
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`15
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`AST0000743
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`Case 6:22-cv-00466-ADA-DTG Document 49-7 Filed 11/28/22 Page 17 of 17
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`lt is belii:.ved that all of the stated grounds of rejection have been properly traversed,
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`accommodated, or rendered moot. Applicants therefore respectfully request that the Examiner
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`reconsider and \vithdravv all presently outstanding rejections.
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`It is believed that a fuU and
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`complete response has been made to the outstanding Oi1icc Action and the present application is
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`in condition for allowance. Thus, prompt and favorable consideration of this response is
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`respectfully requested.
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`ff the Examiner believes that personal communication will expedite
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`prosecution of this application, the Examiner 1s invited to tdcpho11c Uw undersigned at
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`(312) 609--7599.
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`Respectfully submitted,
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`n_ \''.
`D,
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`-
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`Christoph01-··). Rcckarnp
`Registration No. 34,414
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`Date:
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`Vedder, P1icc, Kaufman & Kammholz, P.C.
`222 North LaSalle Street, Suite 2600
`C:h1cago, _Hl1r101s 6060 l
`phone: {312) 609-7599
`fax: (312) 609-5005
`
`16
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`AST0000744
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