Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 1 of 22
`
`
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`No. 6:22-CV-0466-ADA-DTG
`
`ADVANCED SILICON
`TECHNOLOGIES LLC,
`
`
`
`v.
`
`NXP SEMICONDUCTORS N.V.,
`NXP B.V., and
`NXP USA, INC.,
`
`
`
`Plaintiff,
`
`Defendants.
`
`DEFENDANT NXP USA, INC.’S
`OPENING CLAIM CONSTRUCTION BRIEF
`
`
`
`
`
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 2 of 22
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`
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`A.
`B.
`
`III.
`
`IV.
`
`INTRODUCTION .............................................................................................................. 1
`
`OVERVIEW ....................................................................................................................... 1
`
`’945 Patent .................................................................................................................... 1
`’435 Patent .................................................................................................................... 3
`PRIOR PROCEEDINGS .................................................................................................... 3
`
`ARGUMENT ...................................................................................................................... 4
`
`V.
`
`
`
`A.
`
`B.
`C.
`D.
`
`E.
`
`Term 1: “A method for reducing power consumption for a video decoder comprising”
`....................................................................................................................................... 4
`Term 2: “graphics pipeline” .......................................................................................... 6
`Term 3: “graphics pipelines operative to process data in a dedicated tile” .................. 7
`Term 4: “a memory controller . . . operative to transfer pixel data between each of a
`first pipeline and a second pipeline [the two graphics pipelines] and a memory shared
`among the at least two graphics pipelines” ................................................................. 10
`Term 5: “NxM number of pixels” ............................................................................... 13
`1. Applicant Denied “N×M number of pixels” Encompassed an N×N Array .......... 13
`2. Applicants’ Arguments in the Prosecution History Prevent Claim 21 From
`Encompassing a Square Array of Pixels ............................................................... 14
`CONCLUSION ................................................................................................................. 16
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 3 of 22
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`
`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`CASES
`
`Am. Piledriving Equip. v. Geoquip, Inc.,
`637 F.3d 1324 (Fed. Cir. 2011)................................................................................................15
`
`Anglefix, LLC v. Wright Med. Tech., Inc.,
`No. 2:13-cv-2407, 2015 WL 9581865 (W.D. Tenn. Dec. 30, 2015) .........................................9
`
`Aylus Networks, Inc. v. Apple Inc.,
`856 F.3d 1353 (Fed. Cir. 2017)..................................................................................................9
`
`Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc.,
`289 F.3d 801 (Fed. Cir. 2002)................................................................................................4, 5
`
`CommScope Techs. LLC v. Dali Wireless Inc.,
`10 F.4th 1289 (Fed. Cir. 2021) ................................................................................................12
`
`Computing or Graphics Systems, Components Thereof, and Vehicles Containing Same,
`Inv. No. 337-TA-984 (ITC May 20, 2016) ..........................................................................3, 15
`
`Corel Software, LLC v. Microsoft Corp.,
`No. 2:15-CV-528, 2016 WL 4444747 (D. Utah Aug. 23, 2016) ...............................................9
`
`Corning Glass Works v. Sumitomo Electric U.S.A., Inc.,
`868 F.2d 1251 (Fed. Cir. 1989)..................................................................................................5
`
`Datamize, LLC v. Plumtree Software, Inc.,
`417 F.3d 1342 (Fed. Cir. 2005)................................................................................................11
`
`Digital Retail Apps, Inc. v. H-E-B, LP,
`No. 6-19-cv-167-ADA, 2020 WL 376664 (W.D. Tex. Jan. 23, 2020) ......................................5
`
`Evolutionary Intelligence, LLC v. Sprint Nextel Corp.,
`No. C-13-4513, 2014 WL 4802426 (N.D. Cal. Sept. 26, 2014) ................................................9
`
`Halliburton Energy Servs., Inc. v. M-I LLC,
`514 F.3d 1244 (Fed. Cir. 2008)................................................................................................11
`
`Hockerson-Halberstadt, Inc. v. Avia Grp. Int’l, Inc.,
`222 F.3d 951 (Fed. Cir. 2000)..................................................................................................15
`
`Pitney Bowes, Inc. v. Hewlett-Packard Co.,
`182 F.3d 1298 (Fed. Cir. 1999)..................................................................................................5
`
`Princeton Digital Image Corp. v. Konami Digital Entm’t Inc.,
`No. 12–1461, 2017 WL 6375173 (D. Del. Dec. 13, 2017) ........................................................9
`
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 4 of 22
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`
`Seachange Int’l, Inc. v. C-COR, Inc.,
`413 F.3d 1361 (Fed. Cir. 2005)................................................................................................14
`
`Signal IP, Inc. v. Fiat U.S.A., Inc.,
`No. 14-cv-13864, 2016 WL 5027595 (E.D. Mich. Sept. 20, 2016) ..........................................9
`
`Springs Window Fashions LP v. Novo Indus., L.P.,
`323 F.3d 989 (Fed. Cir. 2003)............................................................................................14, 15
`
`Texas Instruments Inc. v. Advanced Silicon Techs. LLC,
`IPR2016-01108 (PTAB May 27, 2016) .....................................................................................3
`
`Unified Patents Inc. v. Advanced Silicon Techs. LLC,
`IPR2016-01060 (PTAB May 19, 2016) .......................................................................3, 4, 8, 12
`
`Volkswagen Grp. of Am., Inc. v. Advanced Silicon Techs. LLC,
`IPR2016-00894 (PTAB Apr. 15, 2016) .................................................................................3, 4
`
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 5 of 22
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`
`Exhibit
`Number
`
`TABLE OF EXHIBITS
`
`Description
`
`1
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`2
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`3
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`4
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`5
`
`6
`
`7
`
`8
`
`
`
`
`
`Patent Owner’s Preliminary Response Pursuant to 37 C.F.R. § 42.107(a), Unified
`Patents Inc. v. Advanced Silicon Techs. LLC, No. IPR2016-01060, Paper 8 (PTAB
`Aug. 23, 2016) (NXP-AST00156732-85)
`
`Patent Owner’s Preliminary Response Pursuant to 37 C.F.R. § 42.107(a),
`Volkswagen Grp. Of Am., Inc. v. Advanced Silicon Techs. LLC, No. IPR2016-
`00894, Paper 9 (PTAB July 18, 2016) (NXP-AST00156668-731)
`
`IBM Dictionary of Computing (10th 1994) (NXP-AST00156786-89)
`
`The Computer Desktop Encyclopedia (2d 1999) (NXP-AST00156790-92)
`
`Excerpt of Prosecution History for the ’945 Patent, Applicants’ Response (Mar.
`14, 2005) (AST0000877-89)
`
`Excerpt of Prosecution History for the ’945 Patent, Office Action (Feb. 9, 2007)
`(AST0000751-67)
`
`Excerpt of Prosecution History for the ’945 Patent, Applicants’ Response (June 7,
`2007) (AST0000729-44)
`
`Excerpt of Prosecution History for the ’945 Patent, Office Action (Aug. 28, 2007)
`(AST0000700-12)
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 6 of 22
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`
`I.
`
`INTRODUCTION
`
`NXP USA, Inc.’s (“NXP’s” or “Defendant’s”) claim constructions remain true to the
`
`intrinsic and extrinsic evidence, while Advanced Silicon Technologies LLC (“AST” or “Plaintiff”)
`
`ignores that evidence by proposing “plain and ordinary meaning” for every term. NXP’s
`
`constructions reflect arguments AST itself made during prior proceedings before the PTAB while
`
`seeking to preserve validity—arguments AST seeks to evade in order to impermissibly broaden
`
`the asserted claims. It is axiomatic that claims are construed the same for purposes of both
`
`infringement and invalidity, and AST’s contradictory arguments here should be rejected. Because
`
`NXP’s proposed constructions are consistent with the principles of claim-construction law, NXP
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`respectfully submits that this Court should adopt NXP’s constructions.
`
`II.
`
`OVERVIEW
`
`A.
`
`’945 Patent
`
`U.S. Patent No. 8,933,945 (“the ’945 Patent”) “relates to graphics processing circuitry and,
`
`more particularly, to dividing graphics processing operations among multiple pipelines.” ’945
`
`Patent, 1:21–23. The ’945 Patent states that conventional “graphics processing systems typically
`
`include a host processor, graphics (including video) processing circuitry, memory (e.g. frame
`
`buffer), and one or more display devices.” Id., 1:26–30. The graphics processing circuitry
`
`generates pixel data, which is presented as an object or a scene on the display screen. Id., 1:41–
`
`43.
`
`The ’945 Patent states that prior art systems “partitioned” the screen of a “conventional
`
`display device” into a series of vertical or horizontal “strips,” each “typically 1-4 pixels in width.”
`
`Id., 1:44–51. Rather than assigning graphics processing circuits to process data in vertical or
`
`horizontal strips, the ʼ945 Patent employs a conventional technique that partitions the display (and
`
`frame buffer) into a horizontally and vertically repeating pattern of regions, or tiles. Id., 3:25–26,
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 7 of 22
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`2:35–39, 5:48–49. Each independent claim of the ʼ945 Patent recites a “repeating tile pattern,”
`
`where the repeating tile pattern includes a “horizontally and vertically repeating pattern of . . .
`
`regions,” where graphics pipelines “process data in a corresponding set of tiles of a repeating tile
`
`pattern.” Id., 9:66–10:1, 10:9–10, 12:23–30. Annotated FIG. 3 (reproduced below) illustrates this
`
`approach:
`
`
`
`Id., FIG. 3, FIG. 2.
`
`FIG. 3 depicts partitioning the display into a repeating tile pattern of horizontal and vertical
`
`square tiles (or regions) 72–75. Id., 5:46–49. The repeating pattern of tiles (or regions) in the
`
`frame buffer corresponds to the partitioning of the display into tiles (or regions). Id., 5:52–53.
`
`The partitioning pattern is based on the number of and assignment of active graphics pipelines to
`
`the horizontally and vertically arranged regions, and in a “two pipeline configuration, a
`
`‘checkerboard’ pattern is created for the pipes and the patterns repeat over the full screen.” Id.,
`
`8:58–62.
`
`As shown in annotated FIG. 2 (reproduced above), one graphics processing circuit (or
`
`“graphics pipeline”) is responsible for tiles labeled “A,” and a second graphics pipeline is
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 8 of 22
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`responsible for tiles labeled “B.” Id., 5:45–65. More precisely, “[w]hen rendering a primitive
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`(e.g. triangle) 80, the first graphics pipeline 101 processes only those pixels in portions 81, 82 of
`
`the primitive 80 that intersects tiles labeled ‘A’, for example, 72 and 75” (id., 5:54–57) and “the
`
`second graphics pipeline 102 processes only those pixels in portions 83, 84 of the primitive 80 that
`
`intersects tiles labeled ‘B’, for example 73–74.” Id., 5:60–63; FIG. 3.
`
`B.
`
`’435 Patent
`
`U.S. Patent No. 7,804,435 (“the ’435 Patent”) relates to reducing power consumption
`
`within a video processing unit. ’435 Patent, Abstract. Specifically, the patent describes a video
`
`decoder that includes a power controller able to select between various power consumption states,
`
`and to adjust the power consumption in at least a portion of the video decoder. Id. For example,
`
`the ’435 Patent describes varying the frequency of a processor in order to change power
`
`consumption. See, e.g., id., 6:23–25; Abstract.
`
`III.
`
`PRIOR PROCEEDINGS
`
`AST previously asserted the ’945 Patent in the ITC (Computing or Graphics Systems,
`
`Components Thereof, and Vehicles Containing Same, Inv. No. 337-TA-984 (ITC Dec. 21, 2015)
`
`(“ITC Action”)) and in related District of Delaware litigations. Three respondents in the ITC
`
`Action initiated inter partes review (“IPR”) proceedings that were each terminated prior to
`
`institution.1 AST has not previously asserted the ’435 Patent.
`
`In the ITC Action, the parties agreed that (1) “repeating tile pattern includes a horizontally
`
`and vertically repeating pattern of [square] regions” has a plain and ordinary meaning and need
`
`not be construed and (2) “repeating tile pattern” means an arrangement of tiles that includes at
`
`
`
`
`
`
`
`
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`
`
`1 The prior IPRs are Volkswagen Grp. of Am., Inc. v. Advanced Silicon Techs. LLC, IPR2016-
`00894 (PTAB Apr. 15, 2016) (“VW IPR”); Unified Patents Inc. v. Advanced Silicon Techs. LLC,
`IPR2016-01060 (PTAB May 19, 2016) (“Unified Patents IPR”); and Texas Instruments Inc. v.
`Advanced Silicon Techs. LLC, IPR2016-01108 (PTAB May 27, 2016) (“TI IPR”).
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 9 of 22
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`least two tiles in a row and at least two tiles in a column, and “includes a horizontally and vertically
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`repeating pattern of [square] regions.” ITC Action, Order No. 42: Construing Terms of the
`
`Asserted Patents, at 3 (ITC July 15, 2016). The parties briefed the construction of “NxM number
`
`of pixels,” but AST dropped claim 21 prior to issuance of the claim construction order. Id. at 4.
`
`As discussed below, in the prior IPRs, AST made arguments that relate to term 3: “graphics
`
`pipelines operative to process data in a dedicated tile” and term 4: “a memory controller . . .
`
`operative to transfer pixel data between each of a first pipeline and a second pipeline [the two
`
`graphics pipelines] and a memory shared among the at least two graphics pipelines.” See Exs. 1
`
`(Patent Owner’s Preliminary Response Pursuant to 37 C.F.R. § 42.107(a), Unified Patents Inc. v.
`
`Advanced Silicon Techs. LLC, No. IPR2016-01060, Paper 8 (PTAB Aug. 23, 2016) (NXP-
`
`AST00156732–85) (“Unified Patents POPR”)) and 2 (Patent Owner’s Preliminary Response
`
`Pursuant to 37 C.F.R. § 42.107(a), Volkswagen Grp. Of Am., Inc. v. Advanced Silicon Techs. LLC,
`
`No. IPR2016-00894, Paper 9 (PTAB July 18, 2016) (“VW POPR”) (NXP-AST00156668–731).
`
`IV. ARGUMENT
`
`A.
`
`Term 1: “A method for reducing power consumption for a video decoder
`comprising”
`
`Patent/
`Claim
`
`AST’s Proposed Construction
`
`NXP’s Proposed Construction
`
`435:26
`
`Plain and ordinary meaning
`
`Preamble is limiting
`
`
`AST argues that the preamble of claim 26 is non-limiting because the claim’s plain
`
`language confirms that it is inoperable. Specifically, the claim is directed to “[a] method for
`
`reducing power consumption for a video decoder,” but, by its terms, the claim recites steps of
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`increasing—not decreasing—power consumption.
`
`“In general, a preamble limits the invention if it recites essential structure or steps, or if it
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`is ‘necessary to give life, meaning, and vitality’ to the claim.” Catalina Mktg. Int’l, Inc. v.
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 10 of 22
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`Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002) (quoting Pitney Bowes, Inc. v. Hewlett-
`
`Packard Co., 182 F.3d 1298, 1305 (Fed. Cir. 1999)); see also Digital Retail Apps, Inc. v. H-E-B,
`
`LP, No. 6-19-cv-167-ADA, 2020 WL 376664, at *7 (W.D. Tex. Jan. 23, 2020). “Whether to treat
`
`a preamble as a limitation is a determination ‘resolved only on review of the entire[ ] ... patent to
`
`gain an understanding of what the inventors actually invented and intended to encompass by the
`
`claim.’” Catalina, 289 F.3d at 808 (quoting Corning Glass Works v. Sumitomo Electric U.S.A.,
`
`Inc., 868 F.2d 1251, 1257 (Fed. Cir. 1989)). Guideposts used by the Federal Circuit to determine
`
`whether the preamble is limiting include “when the preamble is essential to understand limitations
`
`or terms in the claim body, [then] the preamble limits claim scope.” Catalina, 289 F.3d at 808.
`
`The term “reducing power consumption” is essential to understand limitations in the claim
`
`body and limits the claim scope. The specification explains that “[t]he invention2 relates generally
`
`to video decoders and, more particularly, to a video decoder with reduce power consumption and
`
`method thereof.” ’435 Patent, 1:15–17. The specification describes “an optional step in which,
`
`video decoder 810 determines if there is more than one input stream and increases the power
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`consumption of at least one operational portion of the video decoder 810 in response to the
`
`determination of the encoding description data 834. For example . . . the clock frequency and
`
`supply voltage for the decoder and supporting circuitry is increased if it is not already at the desired
`
`level.” Id., 14:4–12. This step is directly claimed as the last limitation in claim 26.
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`Because the specification discloses a method of “controlling power consumption” (id.,
`
`14:3–4)—where power consumption could be either increased or decreased—the preamble of
`
`claim 26 is “essential to understand” the claim body because it limits the claim to a method for
`
`“reducing power consumption.” Without the preamble term, one would not understand the
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`2 All emphasis added unless otherwise noted.
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 11 of 22
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`remaining limitations of the claim to be directed to reducing the power consumption rather than
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`increasing or otherwise “controlling” power consumption.
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`For these reasons, the Court should determine that the preamble of claim 26 is limiting.
`
`B.
`
`Term 2: “graphics pipeline”
`
`Patent/
`Claim
`
`945.1, 4, 12,
`21
`
`AST’s Proposed Construction
`
`NXP’s Proposed Construction
`
`Plain and ordinary meaning
`
`“hardware, which may be one or more
`circuits, that processes graphics data”
`
`
`The ’945 Patent specification supports NXP’s construction of “graphics pipeline” as
`
`“hardware, which may be one or more circuits, that processes graphics data.” Beginning with the
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`claims, the preambles of independent claims 1 and 21 indicate that a graphics pipeline is an element
`
`of a “graphics processing circuit.” ’945 Patent, claims 1 and 21. Claims 1 and 21 further require
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`a graphics pipeline to be on a “chip” and in communication with a memory controller. Id. And
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`dependent claim 4 requires a graphics pipeline to include “front end circuitry” and “back end
`
`circuitry.” ’945 Patent, claim 4; see also id., claim 11. These requirements indicate that the
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`claimed graphics pipeline is in hardware.
`
`The ’945 Patent specification explains that “[t]he present invention generally relates to
`
`graphics processing circuitry and, more particularly, to dividing graphics processing operations
`
`among multiple pipelines.” Id., 1:21–23. Like the claims, the specification describes a graphics
`
`pipeline as hardware, which may be one or more circuits. The specification discloses that
`
`“graphics processing circuit 34 includes a first graphics pipeline 101” with “front end circuitry 35,
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`a scan converter 37, and back end circuitry 39.” Id., 4:5–9, FIG. 2. The specification explains
`
`“the graphics processing circuit 34 of the present invention is configured as a multi-pipeline
`
`circuit.” Id., 4:16–17.
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 12 of 22
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`Extrinsic evidence confirms NXP’s construction. For example, the IBM Dictionary of
`
`Computing defines a “pipeline” in terms of hardware and circuitry: “[a] A serial arrangement of
`
`processors or a serial arrangement of registers within a processor.” Ex. 3 at 512 (NXP-
`
`AST00156786–89 at -789). And similarly defines a “circuit” as “[o]ne or more conductors through
`
`which an electric current can flow.” Id. at 104 (NXP-AST00156788); see also Ex. 4 at 135 (The
`
`Computer Desktop Encyclopedia (defining “circuit” as “[a] set of electronic components that
`
`perform a particular function in an electronic system”) (NXP-AST00156790–92 at -792).
`
`Because the specification and claims of the ’945 Patent specifically describes that the
`
`“graphics pipeline” is a “circuit” and is composed of “circuitry,” the proper construction of this
`
`term in view of the intrinsic and extrinsic evidence is “hardware, which may be one or more
`
`circuits, that processes graphics data.”
`
`C.
`
`Term 3: “graphics pipelines operative to process data in a dedicated tile”
`
`Patent/
`Claim
`
`AST’s Proposed
`Construction
`
`NXP’s Proposed Construction
`
`945.1, 21 Plain
`meaning
`
`and
`
`ordinary
`
`“graphics pipelines operative such that data for a
`specific tile is processed by one and only one pipeline”
`
`
`NXP’s proposed construction for “graphics pipelines operative to process data in a
`
`dedicated tile” as “graphics pipelines operative such that data for a specific tile is processed by
`
`one and only one pipeline” is borne out by both the specification and prosecution history of the
`
`’945 Patent, including arguments AST made while arguing validity issues before the PTAB. The
`
`’945 Patent seeks to improve distribution of the processing workload among graphics pipelines.
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`’945 Patent, 3:21–31. To achieve this goal, the specification describes dividing the workload
`
`among pipelines, assigning each pipeline the task of processing data for specific tiles of the display.
`
`Id., 4:5–13, FIGS. 2–3 (pipelines processing data in dedicated tiles). The specification explains:
`
`“the first graphics pipeline 101 [is] operative to process graphics data in a first set of tiles,” and
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 13 of 22
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`the “second graphics pipeline 102 [is] operative to process graphics data in a second set of tiles.”
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`Id.
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`The claim language also indicates that the claimed graphics pipeline is operative such that
`
`data for a specific tile is processed by one and only one pipeline. Claims 1 and 21 require that “at
`
`least two graphics pipelines” are “operative to process data in a corresponding set of tiles of a
`
`repeating tile pattern corresponding to screen locations, a respective one of the at least two
`
`graphics pipelines operative to process data in a dedicated tile.” Id., claims 1 and 21. NXP’s
`
`proposed construction is consistent with and appropriately clarifies that the “dedicated tile” is
`
`processed by one and only one pipeline, as “dedicated” connotes and AST explained to the PTAB.
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`Specifically, AST’s representations and arguments in the prior IPR proceedings confirm
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`NXP’s proposed construction is correct. In the Unified Patents POPR, AST argued that the
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`Narayanaswami prior art reference failed to disclose a pipeline “operative to process data in a
`
`dedicated tile” because its processors processed all pixels:
`
`Narayanaswami does not describe any of these processors as hardware or a circuit
`that is exclusively allocated to processing the pixels in a particular tile. (See Hart
`Decl. ¶ 35.) To the contrary, Narayanaswami describes that the processors process
`all pixels, whether they are in a particular tile or not. (Narayanaswami at 7:21–
`28.) (See id. ¶ 36.)
`
`Ex. 1 at 39; see also id. at 40 (“As depicted in Figure 6 and Narayanaswami’s accompanying
`
`description, each Narayanaswami processor processes all pixels, whether they are in a particular
`
`tile or not.”). Indeed, AST explained that “each Narayanaswami processor scan converts and
`
`processes all of the subobject’s pixels, not just those in a specific tile” and such an ability “is
`
`contrary to the teachings of the ’945 Patent and the requirements of all of the challenged claims.”
`
`Id. at 41 (internal citation omitted). In addition to the Unified Patents IPR, AST made these same
`
`arguments regarding Narayanaswami in the VW IPR. Ex. 2 at 44–47.
`
`AST similarly distinguished the Perego prior art reference as not disclosing a pipeline
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 14 of 22
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`“operative to process data in a dedicated tile” because (1) the claimed “dedicated tile” is assigned
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`to one pipeline, i.e., “exclusively allocated” and (2) Perego’s processors process data for pixels
`
`not assigned (i.e., dedicated) to a processor:
`
`
`“But whether a rendering engine is assigned to a tile is not indicative of and does
`not disclose whether that engine is exclusively allocated (‘dedicated’) to processing the
`pixels for a particular tile.” (Ex. 2 at 42–43);
`
`
`“As a result, Perego does not describe a system in which a rendering engine only
`processes the pixels in the particular tile or tiles assigned to that engine.” (id. at 43);
`
`
`“[T]he [Perego] reference describes a system in which the rendering of certain tiles
`is assigned to a particular processor, but each processor processes pixel data that is not
`within the tiles assigned to that processor.” (id.).
`
`AST’s statements to the PTAB during the IPR proceedings constitute part of the ’945 Patent’s
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`prosecution history and constitute disclaimer. See Aylus Networks, Inc. v. Apple Inc., 856 F.3d
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`1353, 1360–61 (Fed. Cir. 2017); Princeton Digital Image Corp. v. Konami Digital Entm’t Inc.,
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`No. 12–1461, 2017 WL 6375173, at *5 (D. Del. Dec. 13, 2017) (patent owner statements during
`
`IPR constitute prosecution history disclaimer).3
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`Accordingly, AST’s proposal of plain and ordinary meaning for the term “graphics
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`pipelines operative to process data in a dedicated tile” is a belated attempt to distance itself from
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`its prior arguments. This attempt to broaden the term for infringement purposes should not be
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`allowed. NXP’s proposed construction of “graphics pipelines operative such that data for a
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`specific tile is processed by one and only one pipeline” is consistent with the claims, specification,
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`
`
`
`
`
`
`
`
`
`
`3 See also Evolutionary Intelligence, LLC v. Sprint Nextel Corp., No. C-13-4513, 2014 WL
`4802426, at *4 (N.D. Cal. Sept. 26, 2014) (“The IPR proceedings will also add to the [patent’s]
`prosecution history.”); Corel Software, LLC v. Microsoft Corp., No. 2:15-CV-528, 2016 WL
`4444747, at *2 (D. Utah Aug. 23, 2016) (noting potential for “additional intrinsic record
`develop[ment] during IPR”); Anglefix, LLC v. Wright Med. Tech., Inc., No. 2:13-cv-2407, 2015
`WL 9581865, at *7–8 (W.D. Tenn. Dec. 30, 2015) (prosecution history includes IPR proceedings);
`Signal IP, Inc. v. Fiat U.S.A., Inc., No. 14-cv-13864, 2016 WL 5027595, at *16 (E.D. Mich. Sept.
`20, 2016) (same)
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 15 of 22
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`prosecution history, and AST’s own validity arguments.
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`D.
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`Term 4: “a memory controller . . . operative to transfer pixel data between
`each of a first pipeline and a second pipeline [the two graphics pipelines] and
`a memory shared among the at least two graphics pipelines”
`
`Patent/
`Claim
`
`945.1, 21
`
`AST’s
`Proposed
`Construction
`
`and
`
`Plain
`ordinary
`meaning
`
`NXP’s Proposed Construction
`
`“a memory controller . . . operative to transfer pixel data to, from,
`and between (1) the first graphics pipeline and the second
`graphics pipeline, and also (2) the two graphics pipelines and a
`memory shared among the two graphics pipelines”
`
`
`AST’s proposal to ascribe an unspecified “plain and ordinary meaning” to the term “a
`
`memory controller . . . operative to transfer pixel data between each of a first pipeline and a second
`
`pipeline [the two graphics pipelines] and a memory shared among the at least two graphics
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`pipelines” is inconsistent with its arguments and representations in the prior IPR proceedings.
`
`Because the claim phrase “memory controller . . . operative to transfer pixel data between
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`each of a first pipeline and a second pipeline and a memory” is devoid of punctuation, there
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`are multiple possible ways to parse the claim term, and the jury needs to understand which parsing
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`is correct. This phrase could be understood to mean:
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`a) “the memory controller can transfer pixel data between (1) a first pipeline and a shared
`
`memory and (2) a second pipeline and a shared memory,” OR
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`b) “the memory controller can transfer pixel data between (1) the first pipeline and the
`
`second pipeline, (2) a first pipeline and a shared memory and (3) a second pipeline and
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`a shared memory.”
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 16 of 22
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`A claim term with multiple possible meanings must be resolved from the claim language,
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`specification, prosecution history, and knowledge of skill in the art or, otherwise, is indefinite.
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`Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1249–50 (Fed. Cir. 2008). Indeed,
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`terms are indefinite where a person of skill in the art has to guess or apply her subjective opinion.
`
`See Datamize, LLC v. Plumtree Software, Inc., 417 F.3d 1342, 1350 (Fed. Cir. 2005) (abrogated
`
`on other grounds in Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 907 (2014)) (term
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`indefinite if “completely dependent on a person's
`
`subjective opinion”).
`
`The specification itself fails to clarify which
`
`parsing controls. Regarding communications by the
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`memory controller in FIG. 2, the specification
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`discloses that “[t]he memory controller 46 is
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`operative to transmit and receive the processed pixel
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`data 43-44 from the back end circuitry 39 and 42;
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`transmit and retrieve pixel data 49 from the graphics
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`memory 48.” ’945 Patent, 5:37–40.
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`During the prior IPR proceedings, however, AST confirmed that the second interpretation
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`above (i.e., interpretation b)—reflected in NXP’s construction—is correct and controls.
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`Specifically, in the VW POPR, AST disputed the proper construction of the term “memory
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`controller.” Ex. 2 at 17–22. AST argued that the proper construction was “logic circuit operative
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`to transmit and receive processed pixel data to and from the first pipeline, the second pipeline, and
`
`the first and second pipelines’ shared memory.” Id. at 20. AST asserted that “[t]he specification
`
`further describes (and Fig. 2 further illustrates) that the memory controller does not just transmit
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`data to the shared graphics memory 48, but also to, from, and between the pipelines 101 and 102.
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`Case 6:22-cv-00466-ADA-DTG Document 49 Filed 11/28/22 Page 17 of 22
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`. . . This interaction with and between the first and second pipelines is confirmed by the only
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`passage that Volkswagen quotes in support of its claim construction.” Id. at 21. AST further
`
`argued over prior art that “Gove does not describe ‘transfer processor 11’ as receiving pixel data
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`from Gove’s ‘parallel processors’ (the purported pipelines), transmitting pixel data to those parallel
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`processors, or otherwise transferring pixel data between one parallel processor and another . . .”
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`Id. at 32–33; see also id. at 34 (“[I]t does not transfer data from one pipeline to another.”).
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`Similarly in the Unified Patents POPR, AST argued the same construction for “memory
`
`controller” and alleged that term required “that the memory controller be operative between the
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`shared memory and between the first and second pipelines.” Ex. 1 at 22; see also id. at 23 (“[T]he
`
`memory controller does not just transmit data to the shared graphics memory 48, but also to, from,
`
`and between the pipelines 101 and 102.”). Distinguishing prior art, AST reiterated this
`
`understanding: “But Seiler does not describe the ‘memory interface 210’ as transferring pixel data
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`(or any data) between one pipeline and another pipeline.” Id. at 26–27.
`
`As discussed in Section IV.C, above, AST’s statements to the PTAB during the IPR
`
`proceedings constitute part of the ’945 Patent’s prosecution history. See Section IV.C (collecting
`
`cases). Accordingly, AST proposed “plain and ordinary meaning” construction that ignores its
`
`prosecution history incorrectly attempts to twist the claims one way to avoid invalidity and another
`
`to argue infringement. See CommScope Techs. LLC v. Dali Wireless Inc., 10 F.4th 1289, 1299
`
`(Fed. Cir. 2021) (“a patent may not, like a nose of wax, be twisted one way to avoid anticipation
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`and another to find infringement”) (internal quotation marks omitted).
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`Thus, the Court should adopt NXP’s proposed construction for the “m