Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 1 of 51
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 1 of 51
`
`EXHIBIT 1
`EXHIBIT 1
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 1 of 51
`
`EXHIBIT 1
`EXHIBIT 1
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 2 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`The following is intended to provide examples of infringement by NXP’s i.MX family of microprocessors and other NXP
`products with substantially similar features and functionality (the “Accused Instrumentalities”), without limitation to other examples.
`The following claim chart supplements the allegations made in the Complaint (ECF No. 1) and Exhibit A (ECF No. 1-1), which AST
`incorporates by reference in full. This preliminary claim chart exists to supply reasonable notice of AST’s infringement contentions,
`not an exhaustive recitation of every possible theory and instance of infringement. The claim construction process has yet to begin.
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties uniquely possess information showing
`infringement of these asserted claims, including source code. AST thus cannot provide its complete and final contentions as to these
`asserted claims until discovery as to the Accused Instrumentalities, including inspection and source code review, takes place.
`Claim 1
`Evidence of Infringement
`[1a] An apparatus
`The Accused Instrumentalities are or include an apparatus within the meaning of this claim. For purposes
`comprising:
`of example and not limitation, the i.MX QuadMax Applications Processor is an applications processor
`including a Video Processing Unit.
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.1, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.2, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`—1—
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`
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`
`
`Claim 1
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 3 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`As another example, the i.MZ 8M Applications Processors are applications processors that include a Video
`Processing Unit.
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.1, Document No.:
`IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`
`
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`—2—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 4 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`:
`
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
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`—3—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 5 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.5.1, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`Further details about how the Accused Instrumentalities disclose this limitation are described with respect
`to elements [1b], [1c], and [1d] below.
`
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`—4—
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`
`
`Claim 1
`[1b] a power
`management
`controller
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 6 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`The Accused Instrumentalities include a power management controller within the meaning of this
`limitation. As shown below, the Accused Instrumentalities all perform power management functions and
`therefore necessarily include a power management controller.
`
`For purposes of example and not limitation, the i.MX 8QuadMax Applications Processor includes a
`System Control Unit (SCU) that handles power management.
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 1.2.1.1, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 8.18.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`
`—5—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 7 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 13.1.7.1, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`
`
`See System Controller Firmware API Reference Guide, § 1.1, i.MX8 QXP Die (Version 1.5), March 22,
`2019 (downloaded from nxp.com; see
`https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-
`processors/150415/1/sc_fw_api_qx_b0.pdf).
`
`
`
`
`—6—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 8 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`
`See System Controller Firmware API Reference Guide, § 1.3.1, i.MX8 QXP Die (Version 1.5), March 22,
`2019 (downloaded from nxp.com; see
`https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-
`processors/150415/1/sc_fw_api_qx_b0.pdf).
`
`As another example, the i.MX 8M Applications Processors includes a Clock Control Module (CCM) that
`manages the clocks.
`
`
`
`
`—7—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 9 of 51
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`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`
`
`
`
`—8—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 10 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 5.1.1, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com). The Clock Control Module is
`part of a power management controller within the meaning of this limitation.
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties uniquely possess
`information showing infringement of this claim limitation, including source code. AST thus cannot
`provide its complete and final contentions as to this limitation until discovery as to the Accused
`Instrumentalities, including inspection and source code review, takes place.
`
`
`—9—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 11 of 51
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`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`Each of the Accused Instrumentalities includes a power management controller that is operatively coupled
`to a video decoder that decodes at least one encoded digital input stream within the meaning of this claim.
`
`For purposes of example and not limitation, the i.MX 8QuadMax Applications Processing includes a
`Video Processing Unit.
`
`
`
`
`Claim 1
`[1c] operatively
`coupled to a video
`decoder that decodes
`at least one encoded
`digital input stream
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.2, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`The Video Processing Unit includes a Multi-Format Video Decoder (MFD) capable of decoding input
`streams using a variety of different encoding formats:
`
`
`
`
`
`
`—10—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 12 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.1.1.2, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`
`—11—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 13 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com).
`
`
`
`
`
`
`
`
`—12—
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`
`
`
`
`Claim 1
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 14 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.5.1.1, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.5.2, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`The Multi-Format Decoder (and the Video Processing Unit as a whole) is operatively coupled to the
`System Control Unit.
`
`
`
`
`—13—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 15 of 51
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`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`—14—
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`
`
`
`
`
`
`Claim 1
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 16 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`See i.MX 8QuadMax Applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com).
`
`As another example, the i.MX 8M Applications Processors include a Video Processing Unit that includes
`VPU G1 decoder and VPU G2 decoder functional blocks capable of decoding input streams using a variety
`of different encoding formats. Each block decodes streams based on different encoding formats such as
`VP8 and H.264 for VPU G1 and VP9 Profile0 and HEVC for VPU G2.
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`
`
`
`—15—
`
`
`
`
`
`
`
`Claim 1
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 17 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`Id. § 14.1.
`
`
`Id. § 14.1.2.
`
`
`Id. § 14.2.1.
`
`
`
`
`
`—16—
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`
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`
`
`
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`
`
`Claim 1
`
`[1d] and in response
`to a determination of
`encoding description
`that describes a
`scheme used to encode
`the input stream,
`varies power
`consumption of at
`least one operational
`portion of the video
`decoder.
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 18 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties uniquely possess
`information showing infringement of this claim limitation, including source code. AST thus cannot
`provide its complete and final contentions as to this limitation until discovery as to the Accused
`Instrumentalities, including inspection and source code review, takes place.
`
`The Accused Instrumentalities include a power management controller that, in response to a determination
`of encoding description that describes a scheme used to encode the input stream, varies power
`consumption of at least one operational portion of the video decoder.
`
`In order to choose the correct decoding process to use, the Accused Instrumentalities must necessarily
`determine an encoding description that describes a scheme used to encode the input stream.
`
`For purposes of example and not limitation, the i.MX 8QuadMax Applications Processor uses different
`clocks for decoding video using different encoding schemes.
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 8.18.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com). The “default” frequency for each of these clocks is 600 MHz.
`Discovery will confirm that the frequency of these clocks may be changed during operation and/or by the
`user. Indeed, there would be no reason to have different clocks for each different type of encoding format
`unless different frequencies were or could be used for the different encoding formats.
`
`
`
`
`—17—
`
`
`
`
`
`Claim 1
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 19 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`As a further example, the VPU of the i.MX 8M Applications Processors includes a VPU G1 decoder and a
`VPU G2 decoder capable of decoding input streams using various encoding formats. Whether the VPU G1
`decoder or the VPU G2 decoder is used for a given stream is determined by the encoding format used for
`that stream.
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com); see also Element [1c] above.
`
`The power management controller (including at least the CCM) operates the VPU G1 and VPU G2 at
`different clock frequencies.
`
`
`
`
`—18—
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 20 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`
`
`
`Claim 1
`
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 5.1.2, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com). Discovery will confirm that
`when a single input stream is used, depending on what format is detected, the Accused Instrumentalities
`will activate one of the VPU G1 or VPU G2, deactivate the other of the VPU G1 or VPU G2, and the total
`power consumed by the VPU will vary (because the clock speed will vary) according to which of the VPU
`G1 and VPU G2 are activated.
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties uniquely possess
`information showing infringement of this claim limitation, including source code. AST thus cannot
`provide its complete and final contentions as to this limitation until discovery as to the Accused
`Instrumentalities, including inspection and source code review, takes place.
`
`
`
`
`
`
`
`—19—
`
`
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 21 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`The Accused Instrumentalities are or include an apparatus of claim 1, as described above with reference
`to claim 1.
`
`Further details regarding how the Accused Instrumentalities meet this limitation are described below with
`reference to Elements [2b] and [2c].
`
`The Accused Instrumentalities include a video decoder operative to determine encoding description data
`from the encoded digital input stream wherein the decoder comprises a plurality of operational portions.
`
`Each of the Accused Instrumentalities include a video decoder. For purposes of example and not
`limitation, the i.MX 8QuadMax Applications Processing includes a Video Processing Unit.
`
`
`
`
`Claim 2
`[2a] The apparatus of
`claim 1 comprising
`
`[2b] a video decoder
`operative to determine
`encoding description
`data from the encoded
`digital input stream
`wherein the decoder
`comprises a plurality of
`operational portions
`and
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.2, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`The Video Processing Unit includes a Multi-Format Video Decoder (MFD) capable of decoding input
`streams using a variety of different encoding formats:
`
`
`
`
`—20—
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`
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 22 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`
`
`
`
`
`
`—21—
`
`
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 23 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.1.1.2, Document No.:
`IMX8QMRM, Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com).
`
`
`
`
`—22—
`
`
`
`
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`
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 24 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.5.1.1, Document No.:
`IMX8QMRM, Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.5.2, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`As another example, the i.MX 8M Applications Processors include a Video Processing Unit that includes
`VPU G1 decoder and VPU G2 decoder functional blocks capable of decoding input streams using a
`variety of different encoding formats. Each block decodes streams based on different encoding formats
`such as VP8 and H.264 for VPU G1 and VP9 Profile0 and HEVC for VPU G2.
`
`
`
`
`—23—
`
`
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 25 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`
`
`
`
`Id. § 14.1.
`
`
`
`
`
`—24—
`
`
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 26 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`
`Id. § 14.1.2.
`
`
`
`
`
`
`Id. § 14.2.1.
`
`The video decoders of the Accused Instrumentalities are capable of decoding digital input streams that
`were encoded with various encoding formats. For example, the MFD in the i.MX 8QuadMax
`
`
`
`—25—
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`
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 27 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Applications Processor can decode input streams encoded with H.265 HEVC, H.264 AVC, H.264 MVC,
`and other encoding formats.
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.5.2, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`As another example, the video decoder(s) in the i.MX 8M Applications Processors can decode input
`streams encoded with VP9, HECC/H.265, AVC/H.264, and other encoding formats.
`
`
`
`
`—26—
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`
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`
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`
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 28 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`In order to choose the correct decoding process to use, the Accused Instrumentalities must necessarily
`determine input stream encoding description data for the encoded digital input stream.
`
`The Accused Instrumentalities select one of a plurality of different power consumption states for the
`video decoder based on that data. For example, the i.MX 8QuadMax Applications Processor selects a
`different clock (corresponding to a different power consumption state) based on the input stream encoding
`description data.
`
`
`
`
` See i.MX 8QuadMax Applications Processor Reference Manual, § 8.18.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`As a further example, the i.MX 8M Applications Processors use different decoder blocks (VPU G1 or
`VPU G2) corresponding to different clocks and clocking frequencies (corresponding to different power
`consumption states) based on the input stream encoding description data.
`
`
`
`
`—27—
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`
`
`
`
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`
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`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 29 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties uniquely possess
`information showing infringement of this claim limitation, including source code. AST thus cannot
`provide its complete and final contentions as to this limitation until discovery as to the Accused
`Instrumentalities, including inspection and source code review, takes place.
`
`The Accused Instrumentalities meet this limitation.
`
` The power management controllers of the Accused Instrumentalities vary power consumption of at least
`one portion of a decoder, as described with reference to element [1d] of claim 1. The various ways in
`which the power consumption is varied correspond to different power consumption states.
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties uniquely possess
`information showing infringement of this claim limitation, including source code. AST thus cannot
`provide its complete and final contentions as to this limitation until discovery as to the Accused
`Instrumentalities, including inspection and source code review, takes place.
`
`
`[2c] wherein the power
`management controller
`is operative to select a
`power consumption
`state to vary power
`consumption of at least
`one portion of the
`decoder.
`
`
`
`—28—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 30 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Claim 3
`[3a] The apparatus of claim 1 wherein
`
`[3b] the power consumption is varied by
`varying parametric values selected from the
`group of clocking frequency, power supply
`voltage, and transistor back bias voltage.
`
`
`
`Evidence of Infringement
`The Accused Instrumentalities are or include an apparatus meeting the limitations
`of claim as described above with reference to claim 1.
`
`The Accused Instrumentalities meet this limitation by varying power consumption
`by varying clocking frequencies, as described above with reference to element [1d]
`of claim 1.
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third
`parties uniquely possess information showing infringement of this claim limitation,
`including source code. AST thus cannot provide its complete and final contentions
`as to this limitation until discovery as to the Accused Instrumentalities, including
`inspection and source code review, takes place.
`
`
`
`
`
`
`—29—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 31 of 51
`
`
`
`Claim 9
`[9a] A method for
`reducing power
`consumption for a video
`decoder comprising:
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Evidence of Infringement
`The Accused Instrumentalities perform a method for reducing power consumption for a video decoder
`within the meaning of this claim.
`
`Each of the Accused Instrumentalities include a video decoder. For purposes of example and not
`limitation, the the i.MX 8QuadMax Applications Processing includes a Video Processing Unit.
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.2, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com).
`
`The Video Processing Unit includes a Multi-Format Video Decoder (MFD) capable of decoding input
`streams using a variety of different encoding formats:
`
`
`
`
`
`
`—30—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 32 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.1.1.2, Document No.:
`IMX8QMRM, Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`
`—31—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 33 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com).
`
`
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.5.1.1, Document No.:
`IMX8QMRM, Rev 0, 9/2021 (downloaded from nxp.com).
`
`
`
`—32—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 34 of 51
`
`
`
`
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.5.2, Document No.:
`IMX8QMRM, Rev 0, 9/2021 (downloaded from nxp.com).
`
`As another example, the i.MX 8M Applications Processors include a Video Processing Unit that
`includes VPU G1 decoder and VPU G2 decoder functional blocks capable of decoding input streams
`using a variety of different encoding formats. Each block decodes streams based on different encoding
`formats such as VP8 and H.264 for VPU G1 and VP9 Profile0 and HEVC for VPU G2.
`
`
`
`
`—33—
`
`
`
`
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 35 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`
`
`Id. § 14.1.
`
`
`
`—34—
`
`
`
`
`
`
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 36 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`Id. § 14.1.2.
`
`
`
`
`
`
`Id. § 14.2.1.
`
`The Accused Instrumentalities perform the method as described below with reference to elements [9b]
`and [9c].
`
`The Accused Instrumentalities determine input stream encoding description data, associated with at
`least one encoded digital input stream, to select one of a plurality of different power consumption states
`for a video decoder, within the meaning of this claim.
`
`The Accused Instrumentalities include video decoders as discussed above with reference to element
`[9a]. The video decoders are capable of decoding digital input streams that were encoded with various
`encoding formats. For example, the MFD in the i.MX 8QuadMax Applications Processor can decode
`input streams encoded with H.265 HEVC, H.264 AVC, H.264 MVC, and other encoding formats.
`
`
`[9b] determining input
`stream encoding
`description data,
`associated with at least
`one encoded digital input
`stream, to select one of a
`plurality of different
`power consumption
`states for a video
`decoder; and
`
`—35—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 37 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`
`See i.MX 8QuadMax Applications Processor Reference Manual, § 16.5.2, Document No.:
`IMX8QMRM, Rev 0, 9/2021 (downloaded from nxp.com).
`
`As another example, the video decoder(s) in the i.MX 8M Applications Processors can decode input
`streams encoded with VP9, HECC/H.265, AVC/H.264, and other encoding formats.
`
`
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`
`
`—36—
`
`
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 38 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`In order to choose the correct decoding process to use, the Accused Instrumentalities must necessarily
`determine input stream encoding description data for the encoded digital input stream.
`
`The Accused Instrumentalities select one of a plurality of different power consumption states for the
`video decoder based on that data. For example, the i.MX 8QuadMax Applications Processor selects a
`different clock (corresponding to a different power consumption state) based on the input stream
`encoding description data.
`
`
`
`
` See i.MX 8QuadMax Applications Processor Reference Manual, § 8.18.4, Document No.:
`IMX8QMRM, Rev 0, 9/2021 (downloaded from nxp.com).
`
`As a further example, the i.MX 8M Applications Processors use different decoder blocks (VPU G1 or
`VPU G2) corresponding to different clocks and clocking frequencies (corresponding to different power
`consumption states) based on the input stream encoding description data.
`
`
`
`
`—37—
`
`
`
`
`
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 39 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`
`
`
`i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, § 1.4.10, Document
`No.: IMX8MDQLQRM, Rev. 3.1, 06/2021 (downloaded from nxp.com).
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties uniquely possess
`information showing infringement of this claim limitation, including source code. AST thus cannot
`provide its complete and final contentions as to this limitation until discovery as to the Accused
`Instrumentalities, including inspection and source code review, takes place.
`
`The Accused Instrumentalities vary power consumption of at least one operational portion of the video
`decoder, as described with reference to element [1d] of claim 1 above.
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties uniquely possess
`information showing infringement of this claim limitation, including source code. AST thus cannot
`provide its complete and final contentions as to this limitation until discovery as to the Accused
`Instrumentalities, including inspection and source code review, takes place.
`
`
`
`
`[9c] in response to the
`determination, varying
`power consumption of at
`least one operational
`portion of the video
`decoder.
`
`—38—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 40 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Claim 12
`[12a] The method of claim 9 wherein
`
`[12b] varying power consumption
`includes varying a parametric value of
`at least one operating portion of the
`video decoder.
`
`Evidence of Infringement
`The Accused Instrumentalities perform the method of claim 9, as described above with
`reference to claim 9.
`
`The Accused Instrumentalities meet this limitation by varying power consumption by
`varying clocking frequencies, as described above with reference to element [9c] of claim
`9.
`
`AST’s factual investigation remains ongoing, and AST believes NXP and third parties
`uniquely possess information showing infringement of this claim limitation, including
`source code. AST thus cannot provide its complete and final contentions as to this
`limitation until discovery as to the Accused Instrumentalities, including inspection and
`source code review, takes place.
`
`
`
`
`
`
`
`
`
`
`—39—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-2 Filed 09/12/22 Page 41 of 51
`
`Exhibit A – AST’s Preliminary Infringement Contentions
`Claim Chart of Asserted Claims – U.S. Patent No. 7,804,435
`
`Claim 13
`[13a] The method of claim 12
`wherein
`[13b] the parametric value is from
`the group of clocking frequency,
`power supply voltage, and transistor
`back bias voltage.
`
`Evidence of Infringement
`The Accused Instrumentalities perform the method of claim 12, as described above with
`reference to claim 12.
`The Accused Instrumentalities meet this limitation by varying power consumption by
`varying clocking frequencies. See discussion of element [12b] above.
`
`AST’s factual investigation remains ongoing, an
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