Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 1 of 31
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`UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
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`Plaintiff,
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`Defendant.
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`Plaintiff,
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`Plaintiff,
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`Defendants.
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`Plaintiff,
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`v.
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`v.
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`v.
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`v.
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`Case No. 6:21-cv-0263-ADA
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`JURY TRIAL DEMANDED
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`Case No. 6:21-cv-0264-ADA
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`JURY TRIAL DEMANDED
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`Case No. 6:21-cv-0265-ADA
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`JURY TRIAL DEMANDED
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`Case No. 6:21-cv-0363-ADA
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`JURY TRIAL DEMANDED
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`FUTURE LINK SYSTEMS, LLC,
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`APPLE INC.,
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`FUTURE LINK SYSTEMS, LLC,
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`BROADCOM INC.; BROADCOM CORP.,
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`Defendants.
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`FUTURE LINK SYSTEMS, LLC,
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`QUALCOMM INCORPORATED;
`QUALCOMM TECHNOLOGIES, INC.,
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`FUTURE LINK SYSTEMS, LLC,
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`REALTEK SEMICONDUCTOR
`CORPORATION,
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`Defendant.
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`PLAINTIFF FUTURE LINK SYSTEMS, LLC’S RESPONSE TO CRSR
`DEFENDANTS’ OPENING CLAIM CONSTRUCTION BRIEF
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 2 of 31
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`TABLE OF CONTENTS
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`
`INTRODUCTION ...................................................................................................... 1
`I.
`II. THE ’804 PATENT .................................................................................................... 1
`A. “A circuit arrangement for interfacing a plurality of functional blocks to one
`another in an integrated circuit device, the circuit arrangement comprising”
`(claim 1) .......................................................................................................................... 1
`B. “functional block[s]” (claims 1, 2, 9, 10, 17, 40) .................................................... 4
`C. “serial port” (claims 1-5, 8-10, 14, 17, 40) ............................................................. 6
`D. “serial command, data and clock interconnects” (claims 1, 40) ........................... 11
`E.
`“selectively couple” (claims 1, 9, 17) ................................................................... 12
`III.
`THE ’680 PATENT .............................................................................................. 14
`A. “packet” (claims 1, 7, 8, 20) ................................................................................. 14
`B. “packet-based communications” (claim 1) / “communicating packet data” (claim
`8) / “communicate the packets” (claim 20) ................................................................... 17
`C. “performance-based communications order” (claim 1) / “order . . . as a function of
`the communications priority and performance rules” (claim 8) / “order to the packets
`based upon the generated protocol-based ordering data and performance-based rules”
`(claim 20) ...................................................................................................................... 18
`D. “[internal] CPU-based link” ’680 Patent, Cl. 15 ................................................... 23
`IV.
`CONCLUSION ..................................................................................................... 26
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`i
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 3 of 31
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`TABLE OF AUTHORITIES
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`
`Cases
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`
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`Bd. Of Trs. Of Leland Stanford Junior Univ. v. Roche Molecular Sys., Inc.,
`528 F. Supp. 2d 967 (N.D. Cal. 2007) .......................................................................... 12
`Becton, Dickinson & Co. v. Tyco Healthcare Grp., LP,
`616 F.3d 1249 (Fed. Cir. 2010)..................................................................................... 19
`BookIT Oy v. Bank of Am. Corp.,
`817 F. App'x 990 (Fed. Cir. 2020) .................................................................................. 5
`Catalina Mktg. Int'l, Inc. v. Coolsavings.com, Inc.,
`289 F.3d 801 (Fed. Cir. 2002)..................................................................................... 1, 4
`Cordis Corp. v. Bos. Sci. Corp.,
`658 F.3d 1347 (Fed. Cir. 2011)..................................................................................... 14
`Cordis Corp. v. Medtronic Ave, Inc.,
`339 F.3d 1352 (Fed. Cir. 2003)................................................................................. 7, 13
`Data Engine Techs. LLC v. Google LLC,
`10 F.4th 1375 (Fed. Cir. 2021) ....................................................................................... 5
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005)..................................................................................... 12
`Poly-Am., L.P. v. GSE Lining Tech., Inc.,
`383 F.3d 1303 (Fed. Cir. 2004)....................................................................................... 3
`Proveris Sci. Corp. v. Innovasystems, Inc.,
`739 F.3d 1367 (Fed. Cir. 2014)....................................................................................... 3
`
`
`
`
`ii
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 4 of 31
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`I.
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`INTRODUCTION
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`Plaintiff Future Link Systems, LLC (“FLS”) submits this response to CRSR
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`Defendants’ (“Defendants”) Opening Claim Construction Brief (“Op. Br.”). As set forth
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`below, the disputed terms have a plain and ordinary meaning to a POSA, and Defendants’
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`attempts to rewrite the claims or hold them indefinite should be rejected.
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`II.
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`THE ’804 PATENT
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`A. “A circuit arrangement for interfacing a plurality of functional blocks to
`one another in an integrated circuit device, the circuit arrangement
`comprising” (claim 1)
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`FLS’s Proposed Construction
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`Defendants’ Proposed Construction
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`Limiting
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`Not limiting
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`As Defendants acknowledge, a preamble may be limiting when it recites “essential
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`structure or steps, or is ‘necessary to give life, meaning, and vitality to the claim.” Op. Br.
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`at 3. What Defendants do not acknowledge, however, is that preambles may also be
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`limiting “when reciting additional structure or steps underscored as important by the
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`specification.” Catalina Mktg. Int'l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed.
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`Cir. 2002).
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`Here, the preamble is limiting because the preamble recites structure underscored
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`as important by the specification—that the claimed “circuit arrangement” is “in an
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`integrated circuit device.” The specification repeatedly teaches the importance of
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`implementing the invention within an integrated circuit device, starting with the title of the
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`’804 Patent: “Concurrent serial interconnect for integrating functional blocks in an
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`integrated circuit device.” Likewise, the field of the invention states:
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`1
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 5 of 31
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`The invention is generally related to integrated circuit device design and
`architecture, and in particular, to an interface for interconnecting multiple
`functional blocks together in an integrated circuit device.
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`’804 Patent at 1:6-9. Likewise, the background of the invention repeatedly emphasizes
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`the importance of advances in integrated circuit design, as well as the difficulties that
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`arise within the specific field of integrated circuit architecture. See, e.g., id. at 1:12-42,
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`2:21-23, 2:58-64:
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`Computer technology has advanced a great deal over the last several
`decades. Whereas computers once filled entire rooms, and were constructed
`using individually packaged transistors and/or vacuum tubes to perform
`different logical functions, innovations in semiconductor manufacturing
`techniques have enabled multiple transistors, or logic gates, to be
`integrated together on a single integrated circuit device, or “chip” to
`perform a greater number of logical functions. The size and number of logic
`gates that can be integrated together on a chip continues to improve, and
`whereas early chips had at most only a few hundred gates, more recent
`chips have been developed that incorporate more on the order of millions
`of gates. Furthermore, advances in integration have permitted designs that
`were at one time implemented using multiple chips to be implemented in a
`single chip.
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`As chip designs become more complex, however, the design and
`development process becomes more expensive and time consuming. To
`alleviate this difficulty, design tools have been developed that enable
`developers to build custom chips by assembling together smaller, generic
`components that perform basic functions required for the design.
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`…
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`The ability to integrate greater numbers of gates onto a chip has also
`permitted the complexity of the generic components used by design tools
`to increase.
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`…
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`However, bus-type interconnections suffer from a number of drawbacks
`that limit their usefulness in interconnecting multiple functional blocks in
`a chip.
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`…
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`Therefore, a significant need exists in the art for an improved manner of
`interconnecting components such as functional blocks and the like in an
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`2
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 6 of 31
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`integrated circuit design, and in particular, for a manner of interconnecting
`components that is more flexible, compact, fast, reusable, and expandible
`than conventional designs.
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`The patent makes clear that certain prior art problems of prior art circuit devices
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`are generally solved by the inventive “circuit arrangement and method that interface
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`multiple functional blocks within an integrated circuit device.” Id. at 2:66-3:4.
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`Furthermore, every embodiment of the ’804 Patent connects functional blocks
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`together within an integrated circuit device. See id. at 4:28-31 (“The illustrated
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`embodiments of the invention generally rely on a concurrent serial interconnect to
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`interface a plurality of functional blocks together in an integrated circuit device
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`arrangement.”).
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`Accordingly,
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`the specification clearly and unmistakably underscores
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`the
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`importance of interfacing a plurality of functional blocks together in an integrated circuit
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`device. Defendants do not contest this fact, and tellingly they do not even acknowledge
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`that their primary cited legal authority teaches that under such circumstances a preamble
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`may be limiting. Because the preamble is the only portion of independent claim 1 that
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`recites the important concept of interfacing functional blocks together in an integrated
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`circuit device, the preamble is limiting. See Proveris Sci. Corp. v. Innovasystems, Inc., 739
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`F.3d 1367, 1373 (Fed. Cir. 2014) (where the preamble is “the only reference in any
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`independent claim to the inventive concept [highlighted as important by the specification],”
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`that “fact alone is likely sufficient to support a conclusion that the preamble is limiting”);
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`Poly-Am., L.P. v. GSE Lining Tech., Inc., 383 F.3d 1303, 1310 (Fed. Cir. 2004) (finding
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`preamble to be limiting when the “specification is replete with references to” the limitation,
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`“including the title of the patent itself and the ‘Summary of the Invention’”).
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`3
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 7 of 31
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`Finally, Defendants’ case law is distinguishable. The claim in Catalina recited “a
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`shoe polish for shining shoes,” and the claim in Arctic Cat recited a “power distribution
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`module for a personal recreational vehicle.” Op. Br. at 4. Each of these claims recited
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`what the invention was for, not what the invention was structurally comprised in, as does
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`Claim 1 of the ’804 Patent. Specifically, if the “for interfacing a plurality of functional
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`blocks to one another” were removed from the preamble of the ’804 Patents Claim 1, the
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`preamble would still recite “a circuit arrangement . . . in an integrated circuit device . . . .”
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`Thus, the “in an integrated circuit device” portion of the preamble does not merely recite
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`an intended purpose, as did the claims in Defendants’ cited cases.
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`B. “functional block[s]” (claims 1, 2, 9, 10, 17, 40)
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`FLS’s Proposed Construction
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`Defendants’ Proposed Construction
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`Plain and ordinary meaning
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`“logic circuitry configured to perform
`one or more high level functions in an
`integrated circuit device design, such as
`that of microprocessors, memory
`controllers, communications interface
`controllers, etc.”
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`Functional block has a plain and ordinary meaning, e.g., a logical block that
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`performs a particular function.
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`Defendants allege that the patent provides an “explicit definition” to the contrary.
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`Op. Br. at 5-6 (citing ’804 Patent at 4:40-51, and alleging that “[t]his explicit definition
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`controls”). But the portion of the specification that defendants recite is plainly not a
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`definition, but rather an example of what a functional block may include, and provides
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`explicitly non-limiting examples of functional blocks:
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`A functional block may be considered to include any logic circuitry
`configured to perform one or more high level functions in an integrated
`circuit device design. Most functional blocks are “portable”, whereby they
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 8 of 31
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`are reusable in different designs. Moreover, many functional blocks are also
`“autonomous”, and
`thus capable of operating
`independently and
`concurrently with other components in a design. Examples of functional
`blocks include, but are not limited to processors, controllers, external
`interfaces, encoders, decoders, signal processors, and any other analog
`and/or digital circuitry performing a particular function or set of
`functions.
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`’804 Patent at 4:40-51. Furthermore, the fact that “functional blocks include . . . any other
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`analog and/or digital circuitry performing a particular function or set of functions” makes
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`abundantly clear that functional blocks are not limited to so-called “high level functions,”
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`but rather include components that perform any “function or set of functions.”
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`Other statements in the specification and prosecution history are consistent with
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`this description, because they provide examples of what the inventive functional blocks
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`“typically” are, not what they necessarily are. See ‘’804 Patent at 1:41-55 (explaining that
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`functional blocks “typically replicate higher level functions”); Ex. A to Op. Br. at
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`FLS_APPLE_00000130 (“functional blocks are typically high-level circuit components
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`that perform relatively advanced functions”).
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`Furthermore, Defendants’ cited cases do not support deriving a definition from such
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`exemplary language, because in those cases, the intrinsic record either provided
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`definitional (rather than exemplary) statements, amounted to disclaimer, or both. See Data
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`Engine Techs. LLC v. Google LLC, 10 F.4th 1375, 1382 (Fed. Cir. 2021) (distinguishing
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`prior art because it did not disclosure a particular requirement of a “3D spreadsheet”);
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`BookIT Oy v. Bank of Am. Corp., 817 F. App'x 990, 993–94 (Fed. Cir. 2020) (providing
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`expressly definitional statements).
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`Finally, Defendants allege that “[i]f functional blocks were not devices performing
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`‘high level functions,’ then they would not require various interconnections to
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`communicate information.” See Op. Br. at 7. However, this allegation is entirely
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 9 of 31
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`unsupported and overreaching because components of varying complexity need to
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`communicate information through interconnections. Furthermore, there would be no need
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`to construe “functional blocks” as performing “high-level functions” if interconnections
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`between blocks implies the existence of high-level functions, because the claims already
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`recite
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`interconnections between
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`functional blocks. Under Defendants’
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`theory,
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`interconnections necessarily imply high-level functions, so adding a “high level function”
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`requirement to the “functional block” terms would be redundant with the surrounding claim
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`language.
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`C. “serial port” (claims 1-5, 8-10, 14, 17, 40)
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`FLS’s Proposed Construction
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`Defendants’ Proposed Construction
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`a “port that transfers information
`sequentially”
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`“port that transfers data one bit at a
`time”
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`Defendants argue that a “serial port” must be a port that transmits information “one
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`bit at a time.” Op. Br. at 7. However, Defendants’ proposal is inconsistent with a prior
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`claim construction order, as well as the intrinsic record and accepted usage of what
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`constitutes “serial” transfer of data in the art.
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`Defendants’ proposal actually describes a specific type of serial port (bit-serial), in
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`contrast to serial ports that transmit units of information sequentially using more than one
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`bit at a time (such as, e.g., a “byte-serial” port). See generally Ex. 2 at 187-88 (describing
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`a “Byte-Serial Implementation” that “has a one byte wide data path” as distinct from
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`“Semi-Parallel” and “Fully Parallel Implementations”).
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`Defendants’ primary argument for their improperly narrow construction relies upon
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`the patent’s discussion of “parallel” and “serial” transmissions. But that discussion is an
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`explanation of the physical differences between a type of parallel bus that requires one wire
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 10 of 31
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`for each bit in a word, and a type of serial port that uses fewer physical wires to transmit
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`information units sequentially. Specifically, the ’804 Patent teaches that some parallel ports
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`require as many as 64 bits to be transmitted simultaneously, whereas serial ports can reduce
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`“routing congestion” because “a reduced number of wire[s] are required to interconnect
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`functional blocks.” See ‘804 Patent at 2:23-32, 21:39-59. But the patent goes on to describe
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`other potential differences between serial and parallel ports, such as that “only one
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`component can transmit information over a parallel bus at a time,” and that “control
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`information and data typically share the same lines in a parallel bus.” Id. at 2:33-45.
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`Defendants do not contend that these potential differences between the claimed serial port
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`and parallel ports justify defining “serial port” in a manner that also incorporates these
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`distinctions. Accordingly, the potential distinctions between serial and parallel interfaces
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`discussed in the patent do not constitute disclaimer, much less an unambiguous disclaimer
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`as required to limit the claims to “bit-serial” ports as proposed by Defendants. See Cordis
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`Corp. v. Medtronic Ave, Inc., 339 F.3d 1352, 1359 (Fed. Cir. 2003) (noting that any
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`statement “amenable to multiple reasonable interpretations . . . does not constitute a clear
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`and unmistakable surrender”).
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`Instead, the patent contemplates any approach that transmits information
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`sequentially, even if that sequential approach might involve transmitting more than one bit
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`of information at a time. For instance, the specification states that “serial data lines are
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`used to transmit serial encoded data.” ’804 Patent at 5:45-51. The fact that the patent
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`contemplates transmission of data along more than one data line per port is confirmed by
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`the patent’s teaching that when a “port status” command is issued, “an indication of the
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`identity of each port connected to the port being polled is provided on the data lines.” Id.
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`7
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 11 of 31
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`at 14:45-51. Thus, Defendants’ characterization of a “serial port” being “like a one-lane
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`street for data bits” (Op. Br. at 9) is inconsistent with the embodiments, and the claims
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`certainly should not be limited to Defendants’ incorrect reading of those embodiments.
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`Extrinsic evidence further confirms that serial transmissions can involve more than
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`one bit at a time. Although Defendants cite to a variety of dictionary definitions that they
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`do not establish were authored by persons of skill in the art, numerous examples of “serial”
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`transmissions in patents, published papers, and industry specifications confirms that
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`“serial” transmission is not limited to bit-serial transmission.
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`For example, the PCI Express (“PCIE”) specification1 shows that skilled artisans
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`would not have interpreted “serial port” so restrictively. The PCIE specification teaches “a
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`highly scalable, fully serial interface,” which can transmit many bits at once over multiple
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`“lanes” of a single link. See, e.g., Ex. 3 at 30 (“To scale bandwidth, a Link may aggregate
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`multiple lanes denoted by xN where N may be any number of supported Link widths,”
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`including “x1, x2, x4, x8, x12, x16, and x32.”). Thus, the “fully serial” PCI Express
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`interface can sequentially transmit information in data units that are as small as 1 or as
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`large as 32 bits.
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`Likewise, the DVI specification describes providing “serial” communication that
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`transmits multiple bits at the same time. For instance, the DVI specification teaches that a
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`“T.M.D.S. transmitter encodes and serially transmits an input data stream over a T.M.D.S.
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`Link to a T.M.D.S. receiver (Figure 3-1).” Ex. 4 at 24. Figure 3-1 of the DVI Specification
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`is reproduced below.
`
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`1 The PCIE specification is particularly relevant to the ’804 Patent, because it describes an
`advancement over the original PCI specification, which is referred to throughout the ’804
`Patent. See Ex. 3 at 27; ’804 Patent at 2:15-20, 20:18-20, 20:43-46.
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`8
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 12 of 31
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`As shown above, a “Single T.M.D.S. Data Link” is comprised of three channels,
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`which are capable of “transmitting an R-pel, G-pel, and B-pel data in unison.” Id. at 8.
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`These “pels” are each “a pixel element, i.e., the singular red value or green value or blue
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`value of an RGB pixel.” Id. Thus, the DVI specification teaches that a T.M.D.S. Link sends
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`data in a serial fashion, even though three channels within the T.M.D.S. Link are
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`transmitting bits simultaneously, contrary to Defendants’ proposed construction.
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`Indeed, the inventor of the ’804 Patent, Paul Levy, was a sole inventor of U.S.
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`Patent No. 7,802,049 (the “’049 Patent”), which uses the term “serial” in a way that is
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`consistent with FLS’s proposed construction, and contrary to Defendants’ proposed
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`construction. The ’049 Patent describes “techniques for establishing links comprising one
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`or more lanes between devices,” Ex. 5 at 1:58-59, and Claim 1 of that patent recites in part:
`
`“a plurality of ports comprising a first port, a second port, a third port, and a fourth port to
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`serially transmit symbols over lanes of a plurality of links and to serially receive symbols
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`from lanes of the plurality of links.” Thus, the ’049 Patent states that its serial transmission
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`takes place over a plurality of lanes, consistent with the serial transmission taught by the
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`PCI Express and DVI specifications.
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 13 of 31
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`Defendants criticize much of the evidence above as irrelevant, because it is
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`allegedly “highly specific to Intel.” However, none of the above evidence is actually
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`specific to Intel; rather, it reflects a general understanding in the art that a “serial port” need
`
`not convey bits sequentially, but can instead convey units of information sequentially. See
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`also, e.g., Ex. 2 at 7, 8-9 (teaching “a simple byte-serial implementation that has a one byte
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`wide data path,” and contrasting that approach with “Parallel Implementations”).
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`Furthermore, Judge Stark for the District of Delaware relied on additional information
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`about how Intel engineers understood the term “serial port,” which is plainly relevant to
`
`how a POSA would understand the term. See generally Op. Br. at 35 n.6 (dismissing as
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`irrelevant Intel admissions about the PCI Express standard).
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`For the reasons set forth above, this Court should reject Defendants’ attempt to
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`improperly narrow “serial” to mean “bit-serial,” contrary to how a POSA would have
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`understood the term. Rejection of Defendants’ improperly narrow construction is also fully
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`consistent with the conclusion that Judge Stark reached in the Delaware case.
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`Defendants do not purport to put forth any extrinsic evidence that is not redundant
`
`with the evidence considered by the Delaware Court. Furthermore, Defendants’ criticism
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`of Judge Stark’s order is unfounded. For instance, Defendants’ primary criticism of that
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`order is based on the premise that “control information” and “data” are necessarily sent
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`over separate interconnects within the system. Op. Br. at 10-11 (criticizing the Delaware
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`order because the ’804 Patent “distinguishes prior approaches that communicated ‘control
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`information’ and ‘data’ over the same lines”). But Defendants’ premise is incorrect—for
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`instance, when a “Port Status Command” is issued from an interface controller to a
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`functional block, both the data and command lines supply data regarding one or more “Port
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 14 of 31
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`IDs.” See ’804 Patent at 14:32-49 (explaining that the CMD lines transmit the “Port ID of
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`Responding Port,” whereas the DATA lines transmit “Port ID’s of Ports Connected to the
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`Responding Port”). Thus, Judge Stark correctly acknowledged that the ’804 Patent
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`contemplates sending data over multiple lines simultaneously.
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`D. “serial command, data and clock interconnects” (claims 1, 40)
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`FLS’s Proposed Construction
`
`Defendants’ Proposed Construction
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`Plain and ordinary meaning.
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`In the alternative, “serial command, serial
`data, and serial clock interconnects.”
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`“serial command interconnect, serial
`data interconnect, and serial clock
`interconnect”
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`Defendants do not dispute that, in the plain and ordinary meaning of “serial
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`command, data and clock interconnects,” the adjective “serial” modifies each of the
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`“command, data, and clock” interconnects. Although the term need not be rewritten,2
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`because the plain and ordinary meaning of the term is clear, the term could accurately be
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`construed as “serial command, serial data, and serial clock interconnects.”
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`Defendants assert that FLS’s proposed alternative construction “suggests that each
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`serial port includes multiple command, data, and clock interconnects.” Op. Br. at 14. That
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`is not accurate—FLS’s alternative construction requires the presence of “serial command,
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`serial data, and serial clock interconnects,” but only requires one of each type of
`
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`2 Defendants assert that FLS proposed that this term be construed as “serial command,
`serial data, and serial clock interconnects.” That is incorrect. Rather, FLS proposed a “plain
`and ordinary meaning” construction, and in response to Defendants’ assertion during meet
`and confer that the dispute centered around whether the claimed “data and clock
`interconnects” must be “serial” interconnects, FLS asked Defendants if they would, “[a]s
`a compromise,” agree to a construction of “serial command, serial data, and serial clock
`interconnects.” Ex. 6 (Oct. 22, 2021 email from J. Milkey to counsel for Apple, Broadcom,
`and Qualcomm). Defendants never responded to this compromise construction, and FLS
`maintains its position that the term need not be rewritten.
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 15 of 31
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`interconnect such that the recited “interconnects” constitute “serial command, serial data,
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`and serial clock interconnects.”
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`Finally, Defendants’ proposed construction should be rejected because it is
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`nonsensical when considered in view of the remaining claim language. If Defendants’
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`construction were adopted, the claim language would be rewritten in relevant part as: “each
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`serial port including separate [serial command interconnect, serial data interconnect, and
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`serial clock interconnect].” The singular form of “interconnect” does not make
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`grammatical sense and would serve only to confuse a jury. Accordingly, Defendants’
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`attempt to rewrite this claim term should be rejected.
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`E. “selectively couple” (claims 1, 9, 17)
`
`FLS’s Proposed Construction
`
`Defendants’ Proposed Construction
`
`Plain and ordinary meaning
`
`“dynamically configure pathways between”
`
`“Selectively couple” is a straightforward phrase that a lay jury would readily
`
`understand. Accordingly, it needs no construction. See Bd. Of Trs. Of Leland Stanford
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`Junior Univ. v. Roche Molecular Sys., Inc., 528 F. Supp. 2d 967, 976 (N.D. Cal. 2007)
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`(“[T]he Federal Circuit has held that if commonly understood words are used, then . . .
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`claim construction in such cases involves little more than the application of the widely
`
`accepted meaning of commonly understood words.”) (quoting Phillips v. AWH Corp., 415
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`F.3d 1303, 1314 (Fed. Cir. 2005) (en banc)).
`
`Defendants do not allege that “selectively couple” does not have a plain meaning
`
`in the context of the ’804 Patent. Rather, Defendants’ proposed construction is based solely
`
`on the premise that Applicant “unequivocally defined selectively couple to mean
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`‘dynamically configure pathways between.’” Op. Br. at 15. However, the Applicant’s
`
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 16 of 31
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`statements that Defendants cite is not a “definition” of “selectively couple,” but rather, at
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`most, defines the term “selectable.” See Op. Br. at 15 (citing Ex. A to Op. Br. at
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`FLS_Apple_00000133).
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`The fact that Defendants’ proposed construction is not, in fact, a “definition” of the
`
`term “selectively couple” is confirmed by the claim language itself, which does not allow
`
`for Defendants’ insertion to be logically inserted into the surrounding claim language in
`
`the proposed manner. For instance, claim 1 recites, in part:
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`[T]he interface controller configured to selectively couple at least two of the
`plurality of serial ports to one another to define a logical communications
`channel . . . .
`
`But if Defendants’ proposed construction were adopted, this portion of the claim would be
`
`rewritten as:
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`[T]he interface controller configured to [dynamically configure pathways
`between] at least two of the plurality of serial ports to one another to define
`a logical communications channel . . . .
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`Defendants’ proposed construction is plainly inconsistent with the surrounding claim
`
`language, which already recites that the coupling is “between” two elements (due to the
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`recitation that the serial ports are coupled “to one another”) and further recites that a
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`“logical communications channel” is established (which Defendants do not allege to be
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`different than the proposed “pathway[s]” language).
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`Furthermore, Defendants do not explain how their construction substantively limits
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`the plain meaning of “selectively couple.” Indeed, “dynamically” is in some respects
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`broader than “selectively,” because “dynamic” coupling does not suggest that the coupling
`
`must be done “selectively.” While Defendants rely on the Cordis case to argue that a claim
`
`can be limited based on Applicant statements in traversing a rejection, they cite no authority
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`Case 6:21-cv-00263-ADA Document 39 Filed 11/17/21 Page 17 of 31
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`for broadening a limitation based on such a traversal. See Op. Br. at 17 (citing Cordis
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`Corp. v. Bos. Sci. Corp., 658 F.3d 1347, 1356-57 (Fed. Cir. 2011)).
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`In sum, the intrinsic record does not define “selectively couple,” Defendants’
`
`allegation regarding the “definition” of that term is inconsistent with the surrounding claim
`
`language, and Defendants’ construction mischaracterizes Applicant’s discussion of the
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`prior art to improperly broaden the claim language. Furthermore, Defendants do not
`
`contest that “selectively couple” has a plain meaning. Accordingly, no construction is
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`necessary, and Defendants’ confusing and inaccurate construction should be rejected.
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`III. THE ’680 PATENT
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`A. “packet” (claims 1, 7, 8, 20)
`
`FLS’s Proposed Construction
`
`Defendants’ Proposed Construction
`
`Plain and ordinary meaning
`
`“fundamental unit of information transfer
`consisting of a header that, in some cases, is
`followed by a data payload”
`
`The term “packet” has a plain and ordinary meaning as, for example, a group of
`
`data that is transmitted as a group from one node to another over a network. See, e.g., Ex.
`
`7 (Dictionary of Computing, 2004) (“packet”: “a group of data bits which can be
`
`transmitted as a group from one node to another over a network”); Ex. 8 (Dictionary of
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`Science and Technology, 2003) (same); Ex. 9 (Dictionary of the World Wide Web, 1998)
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`(“packet”: “A generic term used to describe a unit of data sent across a network.”); Ex. 10
`
`(Dictionary of Computer Terms, 1989) (“A packet is a group of consecutive characters
`
`sent from one computer to another over a network.”).
`
`Def