Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 1 of 38
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`FUTURE LINK SYSTEMS, LLC
`
`
`
`Plaintiff,
`
`Civil Action No. 6:21-cv-00263-ADA
`
`v.
`
`APPLE INC.,
`
`Defendant.
`
`FUTURE LINK SYSTEMS, LLC
`
`Plaintiff,
`
`v.
`
`BROADCOM INC., BROADCOM
`CORP.,
`
`Defendants.
`
`FUTURE LINK SYSTEMS, LLC
`
`Plaintiff,
`
`v.
`
`QUALCOMM INCORPORATED,
`QUALCOMM TECHNOLOGIES, INC.,
`
`Defendants.
`
`FUTURE LINK SYSTEMS, LLC
`
`Plaintiff,
`
`v.
`
`REALTEK SEMICONDUCTOR
`CORPORATION,
`
`Defendant.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`JURY TRIAL DEMANDED
`
`Civil Action No. 6:21-cv-00264-ADA
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`JURY TRIAL DEMANDED
`
`Civil Action No. 6:21-cv-00265-ADA
`
`JURY TRIAL DEMANDED
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`Civil Action No. 6:21-cv-00363-ADA
`
`JURY TRIAL DEMANDED
`
`APPLE INC., BROADCOM INC., BROADCOM CORP., QUALCOMM
`INCORPORATED, QUALCOMM TECHNOLOGIES, INC. AND REALTEK
`SEMICONDUCTOR CORPORATION’S OPENING CLAIM CONSTRUCTION BRIEF
`U.S. PATENT NOS. 7,917,680, 6,317,804, and 6,807,505
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 2 of 38
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`TABLE OF CONTENTS
`
`
`INTRODUCTION .......................................................................................................................... 1
`
`I.
`
`OVERVIEW OF THE TECHNOLOGY ............................................................................... 1
`
`A. The ’804 Patent .......................................................................................................... 1
`
`B. The ’680 Patent .......................................................................................................... 2
`
`II. APPLICABLE LEGAL PRINCIPLES .................................................................................. 2
`
`III. AGREED CONSTRUCTIONs .............................................................................................. 3
`
`A.
`
`“packet processor” ’680 Patent, Cls. 1, 8, 20 ............................................................. 3
`
`IV. DISPUTED CLAIM CONSTRUCTIONS ............................................................................ 3
`
`A.
`
`“A circuit arrangement for interfacing a plurality of functional blocks to one
`another in an integrated circuit device, the circuit arrangement comprising” ’804
`Patent, Cl. 1 ................................................................................................................ 3
`
`B.
`
`“functional block[s]” ’804 Patent, Cls. 1, 2, 9, 10, 17, 40 ......................................... 5
`
`C.
`
`“Serial Port[s]” ’804 Patent, Cls. 1-5, 8-10, 14, 17, 40 ............................................. 7
`
`D.
`
`“serial command, data and clock interconnects” ’804 Patent, Cls. 1, 40 ................ 12
`
`E.
`
`“selectively couple” ’804 Patent, Cls. 1, 9, 17 ......................................................... 14
`
`F.
`
`“packet” ’680 Patent, Cls. 1, 7, 8, 20 ....................................................................... 17
`
`G.
`
`H.
`
`“packet-based communications” (asserted claim 1) / “communicating packet data”
`(asserted claim 8) / “communicate the packets” (asserted claim 20) ’680 Patent, Cls.
`1, 8, 20...................................................................................................................... 20
`
`“performance-based communications order” (asserted claim 1) / “order . . . as a
`function of the communications priority and performance rules” (asserted claim 8) /
`“order to the packets based upon the generated protocol-based ordering data and
`performance-based rules” (asserted claim 20) ’680 Patent, Cls. 1, 8, 20 ................ 23
`
`I.
`
`“CPU-based link” ’680 Patent, Cl. 15 ..................................................................... 27
`
`CONCLUSION ............................................................................................................................. 29
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 3 of 38
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`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`Cases
`
`Anglefix, LLC v. Wright Med. Tech., Inc.,
`No. 2:13-CV-02407-JPM-TMP, 2015 WL 9581865 (W.D. Tenn. Dec. 30, 2015) .................24
`
`Arctic Cat Inc. v. GEP Power Prods.,
`919 F.3d 1320 (Fed. Cir. 2019)..............................................................................................4, 5
`
`Athur A. Collins, Inc. v. Northern Telecom Ltd.,
`216 F.3d 1042 (Fed. Cir. 2000)................................................................................................18
`
`BookIT Oy v. Bank of Am. Corp.,
`817 F. App’x 990 (Fed. Cir. 2020) ............................................................................................6
`
`Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc.,
`289 F.3d 801 (Fed. Cir. 2002)................................................................................................3, 4
`
`Cordis Corp. v. Bos. Sci. Corp.,
`658 F.3d 1347 (Fed. Cir. 2011)................................................................................................17
`
`Data Engine Techs. LLC v. Google LLC,
`10 F.4th 1375 (Fed. Cir. 2021) ..................................................................................................6
`
`Dyfan, LLC v. Target Corp.,
`No. W-19-CV-00179-ADA, 2020 WL 8617821 (W.D. Tex. Nov. 24, 2020) ...........................2
`
`Eaton Corp. v. Rockwell Int’l Corp.,
`323 F.3d 1332 (Fed. Cir. 2003)..................................................................................................4
`
`eCeipt, LLC v. Victoria’s Secret Stores, LLC,
`No. 6:20-CV-747-ADA, 2021 WL 4037599 (W.D. Tex. Sept. 3, 2021) ..................................2
`
`Honeywell Int’l, Inc. v. Universal Avionics Sys. Corp.,
`493 F.3d 1358 (Fed. Cir. 2007)..................................................................................................6
`
`Immunex Corp. v. Sanofi-Aventis U.S. LLC,
`977 F.3d 1212 (Fed. Cir. 2020)....................................................................................18, 19, 21
`
`Intel Corp. v. Future Link Systems, LLC,
`No. 14-377-LPS, 2016 WL 4162648 (D. Del. Aug. 2, 2016) .......................................... passim
`
`LG Elecs., Inc. v. Bizcom Elecs., Inc.,
`453 F.3d 1364 (Fed. Cir. 2006), rev’d on other grounds sub nom. Quanta Computer, Inc. v.
`LG Elecs., Inc., 553 U.S. 617 (2008) .......................................................................................18
`
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`ii
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 4 of 38
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`Nautilus, Inc. v. Biosig Instruments, Inc.,
`572 U.S. 898 (2014) .................................................................................................................27
`
`Rembrandt Wireless Techs., LP v. Samsung Elecs. Co.,
`853 F.3d 1370 (Fed. Cir. 2017)..........................................................................................15, 17
`
`Rexnord Corp. v. Laitram Corp.,
`274 F.3d 1336 (Fed. Cir. 2001)................................................................................................13
`
`SciMed Life Sys., Inc. v. Advanced Cardiovascular Sys., Inc.,
`242 F.3d 1337 (Fed. Cir. 2001)..................................................................................................6
`
`Seabed Geosolutions (US) Inc. v. Magseis FF LLC,
`8 F.4th 1285 (Fed. Cir. 2021) ..................................................................................................21
`
`SmileDirectClub, LLC v. Candid Care Co.,
`6:20-cv-01115-ADA, 2021 WL 3598287 (W.D. Tex. Jul. 1, 2021)........................................21
`
`Telemac Cellular Corp. v. Topp Telecom, Inc.,
`247 F.3d 1316 (Fed. Cir. 2001)................................................................................................24
`
`Teva Pharms. USA, Inc. v. Sandoz, Inc,
`789 F.3d 1335 (Fed. Cir. 2015)................................................................................................28
`
`Texas Instruments, Inc. v. Linear Techs. Corp.,
`182 F. Supp. 2d 580 (E.D. Tex. 2002) .....................................................................................11
`
`V-Formation, Inc. v. Benetton Grp. SpA,
`401 F.3d 1307 (Fed. Cir. 2005)................................................................................................18
`
`WiLan, Inc. v. Apple, Inc.,
`811 F.3d 455 (Fed. Cir. 2017)..................................................................................................14
`
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`iii
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 5 of 38
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`INTRODUCTION
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`Apple Inc. (“Apple”), Broadcom Inc., Broadcom Corp. (collectively “Broadcom”),
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`Qualcomm Incorporated, Qualcomm Technologies, Inc. (collectively “Qualcomm”), and Realtek
`
`Semiconductor Corporation (“Realtek”) (collectively, the “CRSR Defendants”) hereby jointly
`
`submit this opening claim construction brief pursuant to the Court’s Joint Agreed Scheduling
`
`Order, to construe terms of U.S. Patent Nos. 7,917,680 (the “’680 patent”); 6,317,804 (the “’804
`
`patent”); and 6,807,505 (the “’505 patent”).1 See Dkt. No. 29 (Joint Agreed Scheduling Order)
`
`at 3.
`
`I.
`
`OVERVIEW OF THE TECHNOLOGY
`
`A.
`
`The ’804 Patent
`
`The ’804 patent, entitled “Concurrent Serial Interconnect for Integrating Functional
`
`Blocks in an Integrated Circuit Device,” relates to an arrangement and method for arranging
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`functional blocks to interface via serial interconnects. ’804 Patent, Abstract. The patent
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`describes that functional blocks are associated with serial ports, which are, in turn, selectively
`
`coupled to each other by way of an interface controller. See id. at Abstract, 2:66-3:12, cl. 1.
`
`These functional blocks, according to the patent, can be “difficult” to implement as a result of
`
`their communication requirements. Id. at 1:48-65. The patent teaches that relying on parallel, or
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`bus-type, interconnections to solve this problem “suffer[s] from a number of drawbacks.” Id. at
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`2:21-23; see also id. at 2:32-57 (describing that parallel architectures are undesirable because,
`
`inter alia, they use additional space, can have slower transmission, and may allow transmission
`
`
`1 Future Link is asserting the ʼ505 patent against Apple alone. See Future Link Sys. v. Apple,
`Inc., Case No. 6:21-cv-00263-ADA (W.D. Tex. 2020), Dkt. No. 1. Neither Future Link nor
`Apple identified any term from the ʼ505 patent that required construction. As a result, there are
`no disputed claim constructions for the ʼ505 patent.
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`
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`1
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 6 of 38
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`of only one component at a time). Instead, the patent teaches using serial ports with serial
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`interconnects. See id. at 3:13-40 (detailing the purported advantages of using serial ports with
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`serial interconnects over the use of parallel, bus-type architecture).
`
`B.
`
`The ’680 Patent
`
`The ’680 patent, entitled “Performance Based Packet Ordering in a PCI Express Bus,”
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`relates to a specific method of solving performance problems when transferring packets over a
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`data bus, such as a PCI Express bus. When multiple data packet streams are communicated
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`simultaneously, they are often merged at some point in the system for transmission over a
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`particular datapath, and this merger can create bottlenecks. See ’680 Patent at 1:24-39. The
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`patent explains that bus protocols well known in the art, such as PCI Express, include packet-
`
`ordering rules that assign priorities to certain packets or types of packets. See, e.g., id. at 1:40-
`
`2:10. It also explains that “[c]ompliance with these types of protocols, while achieving desirable
`
`performance,” was challenging. Id. at 2:11-24. To address the challenges, the ’680 patent
`
`describes a two-step method. Id. at 2:40-49. First, the patent describes ordering the packets
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`according to the rules of a particular protocol. Id. at 2:43-46. Next, the packets are re-ordered a
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`second time based on separate performance-based rules, while still meeting the ordering rules
`
`specified by the protocol. Id. at 2:46-49. Through this approach, the patent purports to improve
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`performance beyond that achieved by the underlying protocol, while also satisfying protocol
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`requirements. Id. at 3:2-5.
`
`II.
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`APPLICABLE LEGAL PRINCIPLES
`
`The Court is intimately familiar with the legal principles of claim construction. E.g.,
`
`eCeipt, LLC v. Victoria’s Secret Stores, LLC, No. 6:20-CV-747-ADA, 2021 WL 4037599, at *1
`
`(W.D. Tex. Sept. 3, 2021); Dyfan, LLC v. Target Corp., No. W-19-CV-00179-ADA, 2020 WL
`
`8617821, at *2 (W.D. Tex. Nov. 24, 2020). CRSR Defendants identify additional relevant legal
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`
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`2
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 7 of 38
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`authority in-line below.
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`III. AGREED CONSTRUCTIONS
`
`A.
`
`“packet processor”
`’680 Patent, Cls. 1, 8, 20
`
`Qualcomm’s Proposed Construction
`Plain and ordinary meaning
`
`
`
`
`Future Link’s Proposed Construction
`Plain and ordinary meaning
`
`IV. DISPUTED CLAIM CONSTRUCTIONS
`
`A.
`
`“A circuit arrangement for interfacing a plurality of functional blocks to one
`another in an integrated circuit device, the circuit arrangement comprising”
`’804 Patent, Cl. 1
`
`CRSR Defendants’ Proposed Construction2
`Not Limiting
`Qualcomm
`
`
`
`Future Link’s Proposed Construction
`Limiting
`
`The preamble of claim 1 of the ’804 patent merely recites an intended use of a
`
`structurally complete invention recited in the body of claim 1. Nothing in the preamble is
`
`necessary to give life, meaning or vitality to the claims. Accordingly, the preamble is not
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`limiting.
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`“In general, a preamble limits the invention if it recites essential structure or steps, or if it
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`is “necessary to give life, meaning, and vitality to the claim.” See, e.g., Catalina Mktg. Int’l, Inc.
`
`v. Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002). The Federal Circuit considers a
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`number of factors to guide the analysis. Id. (“No litmus test defines when a preamble limits
`
`claim scope. Some guideposts, however, have emerged from various cases discussing the
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`preamble’s effect on claim scope.”).
`
`
`2 For each table of constructions identified in this brief, the construction present in the “CRSR
`Defendants’ Proposed Construction” column is proposed by only the Defendants identified
`below that construction. Other CRSR Defendants take no position regarding the construction.
`For example, Qualcomm argues that the preamble of claim 1 of the ’804 patent is not limiting
`and the other CRSR Defendants take no position.
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 8 of 38
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`For example, where the body of a claim “describes a structurally complete invention such
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`that deletion of the preamble phrase does not affect the structure . . . of the claimed invention”
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`the preamble is not limiting. Catalina, 289 F.3d at 809; see also Arctic Cat Inc. v. GEP Power
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`Prods., 919 F.3d 1320, 1328 (Fed. Cir. 2019); Eaton Corp. v. Rockwell Int’l Corp., 323 F.3d
`
`1332, 1339 (Fed. Cir. 2003) (explaining that “[i]f the body of the claim sets out the complete
`
`invention, then the language of the preamble may be superfluous” (internal citations omitted)).
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`That is the case here.
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`The body of claim 1, reproduced below, recites a structurally complete invention
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`comprising an interface controller for coupling functional blocks via a point-to-point connection:
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`(a) a plurality of serial ports, each serial port associated with and coupled to a
`functional block via a point-to point connection to permit external communication
`there with, and each serial port including separate serial command, data and clock
`interconnects, and
`
`(b) an interface controller, coupled to each of the plurality of serial ports, the
`interface controller configured to selectively couple at least two of the plurality of
`serial ports to one another to define a logical communications channel between
`the functional blocks associated there with.
`
`’804 Patent at Claim 1. The deletion of the preamble in no way affects the structure recited in
`
`the body, let alone “give[s] life, meaning and vitality” to the claim. Catalina, 289 F.3d at 808.
`
`The preamble merely references what the claimed structure can be used for: “A circuit
`
`arrangement for interfacing a plurality of functional blocks to one another in an integrated circuit
`
`device.” This recitation of intended use is precisely the type of language the Federal Circuit has
`
`found not limiting. For example, in Catalina, the court explained that where a claim’s preamble
`
`recited “a shoe polish for shining shoes” and the body of the claim recited the composition of
`
`the shoe polish, the preamble did not limit the claims. 289 F.3d at 809-10. Similarly, in Arctic
`
`Cat the Federal Circuit held that “[a] power distribution module for a personal recreational
`
`vehicle” was not limiting because it refers to merely an intended use of the structurally complete
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`apparatus recited in the body of the claims, namely, a use within a recreational vehicle. Arctic
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`Cat, 919 F.3d at 1328-29. Accordingly, claim 1’s recitation of a potential use for the structurally
`
`complete invention does not limit the claim.
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`In addition, where a preamble does not provide antecedent basis for a claim, this factor
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`suggests the preamble is not limiting. Id. at 1328. Here, none of the claim terms in the body of
`
`claim 1 of the ’804 patent rely on the preamble for antecedent basis. Indeed, the claim goes out
`
`of its way not to rely on the preamble for antecedent basis. For example, the preamble recites “a
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`plurality of functional blocks,” but then the first limitation in effect re-introduces the functional
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`blocks, recite “a plurality of serial ports, each serial port associated with and coupled to a
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`functional block.” Accordingly, this factor also suggests that the preamble is not limiting.
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`Finally, the preamble here merely adds structure (an integrated circuit) of which material
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`cited in the body (the interface and blocks) may be a part. As a result, the preamble here is
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`similar to the one in Arctic Cat, which the court found nonlimiting, inter alia, because it merely
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`“adds structure of which the body recited module is a part.” 919 F.3d at 1328.
`
`In view of the above, the preamble of claim 1 of the ’804 Patent is not limiting.
`
`B.
`
`“functional block[s]”
`’804 Patent, Cls. 1, 2, 9, 10, 17, 40
`
`CRSR Defendants’ Proposed Construction
`“logic circuitry configured to perform one or
`more high level functions in an integrated
`circuit device design, such as that of
`microprocessors, memory controllers,
`communications interface controllers, etc.”
`Apple, Qualcomm
`
`
`
`Future Link’s Proposed Construction
`Plain and ordinary meaning
`
`The ’804 patent sets forth a clear definition of functional block in the specification:
`
`A functional block may be considered to include any logic circuitry configured
`to perform one or more high level functions in an integrated circuit device
`design. Most functional blocks are “portable”, whereby they are reusable in
`different designs. Moreover, many functional blocks are also “autonomous”, and
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 10 of 38
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`thus capable of operating independently and concurrently with other components
`in a design. Examples of functional blocks include, but are not limited to
`processors, controllers, external interfaces, encoders, decoders, signal
`processors, and any other analog and/or digital circuitry performing a particular
`function or set of functions.
`
`’804 Patent, 4:40-51 (emphases added). This explicit definition controls. See Honeywell Int’l,
`
`Inc. v. Universal Avionics Sys. Corp., 493 F.3d 1358, 1362--64 (Fed. Cir. 2007); SciMed Life
`
`Sys., Inc. v. Advanced Cardiovascular Sys., Inc., 242 F.3d 1337, 1342-43 (Fed. Cir. 2001).
`
`Other portions of the specification and the prosecution history confirm that the patentee
`
`intended this definition of functional block. As background, the ’804 patent explains that
`
`functional blocks must perform high-level functions like those of microprocessors, memory
`
`controllers, and communications interface controllers:
`
`[M]ore advanced components typically replicate higher level functions such as
`that of microprocessors, memory controllers, communications interface
`controllers, etc. These more advanced components are referred to herein as
`functional blocks, insofar as they are configured to perform one or more high
`level functions in a design.”
`
`’804 Patent at 1:41-55 (emphases added). The patent expressly states that components “are
`
`referred to herein as functional blocks” when they are configured to perform “high level
`
`functions.” Id. During prosecution, the applicant reinforced this definition, explaining to the
`
`patent office that, “[a]s discussed in the background section of the application, functional blocks
`
`are typically high-level circuit components that perform relatively advanced functions, e.g.,
`
`microprocessors, memory controllers, etc.” Ex. A (’804 Patent Pros. History, 2001-05-18
`
`Amendment/Req. Reconsideration-After Non-Final Rejection) at 1-2. No use of the term
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`“functional block” in the ’804 patent or its prosecution history strays from this definition.
`
`Language like this, which definitively defines the scope of a term, is definitional. See,
`
`e.g., Data Engine Techs. LLC v. Google LLC, 10 F.4th 1375, 1382-83 (Fed. Cir. 2021); BookIT
`
`Oy v. Bank of Am. Corp., 817 F. App’x 990, 993-94 (Fed. Cir. 2020) (finding definitional
`
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`phrases “[a]s used in this application, the mediator is a network based service available to the
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`service provider booking services over the network,” and “service providers are those with
`
`whom clients want to make appointments, reservations, or other bookings and comprise the
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`resources for the booking system to allocate”).
`
`Allowing functional block to assume a contrary definition would be inconsistent with the
`
`’804 patent’s teachings. The ’804 patent purports to solve the “difficulty associated with the use
`
`of . . . functional blocks,” which “arises from the need for various components in a design to
`
`communicate with and transfer information among one another.” Id. at 1:56-59. If functional
`
`blocks were not devices performing “high level functions,” like microprocessors, memory
`
`controllers, or communications interface controllers, then they would not require various
`
`interconnections to communicate information. Such a result would rob the ’804 patent of its
`
`motivation: “a significant need exists in the art for an improved manner of interconnecting
`
`components such as functional blocks and the like in an integrated circuit design, and in
`
`particular, for a manner of interconnecting components that is more flexible, compact, fast,
`
`reusable, and expandible than conventional designs.” Id. at 2:58-64.
`
`CRSR Defendants propose that functional block be construed according to the ’804
`
`patent’s express definition. Because the patentee plainly intended to define functional blocks in
`
`this way, the Court should adopt this construction.
`
`C.
`
`“serial port[s]”
`’804 Patent, Cls. 1-5, 8-10, 14, 17, 40
`
` CRSR Defendants’ Proposed Construction
`“port[s] that transfer[s] data one bit at a time”
`
`Apple, Broadcom, Qualcomm
`
`Future Link’s Proposed Construction
`“a port that transfers information
`sequentially”
`
`
`The dispute for this term centers on which proposal more precisely captures the serial
`
`nature of the claimed serial port[s]. CRSR Defendants propose a definition that captures the true
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 12 of 38
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`nature of a serial port — one where data is transferred one bit at a time. Plaintiff’s proposal
`
`allows for bits to be spread across multiple lines such that these bits are transmitted
`
`simultaneously or at the same time, the precise oppose of a serial port.
`
`The alleged invention claims a serial port architecture and touts the benefits of that
`
`architecture over existing parallel bus technologies. Specifically, the ’804 Patent explains that
`
`“[t]ypically, a bus is parallel, incorporating multiple lines so that multiple bits of information can
`
`be transmitted simultaneously,” ’804 Patent at 2:9-11, but criticizes such parallel buses on
`
`several grounds. For example, “parallel bus architectures require a relatively large number of
`
`lines, or wires, to run between the various components connected to the bus. . . . Many parallel
`
`buses, for example, transmit data in 32- or 64-bit words, requiring at a minimum 32 or 64 lines to
`
`be routed to each component.” Id. at 2:23-32.
`
`To address these drawbacks of prior art parallel bus approaches, the ’804 Patent proposes
`
`an approach involving “serial interconnects.” “Through the use of serial interconnects, the
`
`number of lines required to be routed to and from individual functional blocks is reduced,
`
`thereby simplifying the integration of functional blocks into a design and reducing the routing
`
`congestion associated with inter-block communication.” Id. at 3:13-17. The approach of
`
`the ’804 Patent includes a “serial interconnection” between the interface controller and each of a
`
`number of functional blocks. Id. at Fig. 1. “Each serial interconnection 50-58 includes separate
`
`serial command, data and clock lines.” Id. at 5:42-43. The ’804 Patent discloses that “each line
`
`may be implemented using a bidirectional wire, or a pair of unidirectional wires may be
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`provided,” and that “lines may be implemented with single-ended wires, or may be implemented
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`8
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 13 of 38
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`by differential pairs of wires.” Id. at 5:63-6:2.3 Regardless, there is only a single signal
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`transmitted in a given direction.
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`These disclosures show that a serial port is like a one-lane street for data bits, in that the
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`data bits are transmitted one after the other. On the other hand, a parallel port is like a multi-
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`lane street because multiple data lines can transfer multiple data bits simultaneously. Consistent
`
`with the disclosures in the ’804 Patent, in the context of communications, “serial port” refers to a
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`port that transfers data one bit at a time, in contrast with a parallel port that can transfer multiple
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`data bits simultaneously by using multiple data interconnects per port. Technical dictionaries
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`routinely use “one bit at a time” to characterize serial connections:
`
`
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`IBM Dictionary of Computing (1994) (Ex. B)
`
`o “serial port”: “An access point through which a computer transmits or receives
`data, one bit at a time. Contrast with parallel port.” Id. at 612.
`
`
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`IEEE Standard Glossary of Computer Hardware Terminology, IEEE Std 610.10-1994
`(1995) (Ex. C)
`
`o “3.2016 serial port. A port that transfers data one bit at a time. Contrast with:
`parallel port.” Id. at 84
`
`o Contrast with “3.15694 parallel port. A port that transfers data one byte4 at a time,
`each bit over its own line. Contrast with: serial port.” Id. at 67
`
` Microsoft Press Computer Dictionary 2d Ed. (1994) (Ex. D)
`
`o “serial port An input/output location for serial data transmission.” Id. at 355
`
`o “serial transmission The transmission of discrete signals one after the other. In
`communications and data transfer, serial transmission involves sending
`information over a single wire one bit at a time.” Id. (emphasis added)
`
`o See “serial interface A data-transmission scheme that sends data and control bits
`sequentially over a single transmission line.” Id.
`
`
`3 “Differential” refers to the sending of a signal as the difference between signals carried over
`two wires. Ex. E (Microsoft Press Computer Dictionary 2d Ed. (1994))
`4 One “byte” of data comprises 8 data bits.
`
`
`
`9
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 14 of 38
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`o See “serial One by one. In reference to data transfer, In communications and
`data transfer, serial transmission involves sending information over a single
`wire one bit at a time.” Id. (emphasis added)
`
` Barron’s Dictionary of Computer and Internet Terms 7th Ed. (2000) (Ex. F)
`
`o “serial port a connection by which a computer can transmit data to another device
`using serial transmission - that is, one bit at a time.” Id. at 436.
`
`The technical dictionaries provide definitions precisely in line with Defendants’ construction
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`aimed at capturing the true meaning of a serial port.
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`Plaintiff’s construction relies on the sequential nature of the transmission, rendering the
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`construction imprecise and incomplete because it does not take into account the timing of the
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`data transfer. Although serial ports do transmit bits sequentially (i.e., one after the other), serial
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`ports do not transmit those bits simultaneously or at the same time. Given Plaintiff’s incomplete
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`definition, CRSR Defendants are concerned that Plaintiff will argue the term reads on parallel
`
`ports—a distinctly different kind of port. See, e.g., Ex. B (IBM Dictionary of Computing (1994))
`
`at 498 (defining “parallel port” as “An access point through which a computer transmits or
`
`receives data that consists of several bits sent simultaneously on separate wires. Contrast with
`
`serial port”). Although neither the claim language itself nor either proposed construction
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`explicitly covers a parallel architecture, CRSR Defendants’ construction is more precise and will
`
`avoid confusing the jury.
`
`Although the District of Delaware in a separate matter involving Intel previously
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`construed this term to mean “a port that transfers information sequentially,” as Future Link
`
`proposes here, the Delaware court’s construction was incorrect and based on a misunderstanding
`
`of Intel’s proposed construction. See Intel Corp. v. Future Link Systems, LLC, No. 14-377-LPS,
`
`
`
`10
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 15 of 38
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`2016 WL 4162648 (D. Del. Aug. 2, 2016).5 Intel proposed that the term be construed as “a port
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`that transfers data one bit at a time,” but the Delaware court premised its construction on the
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`basis that each “port” has three separate interconnects that are used concurrently: a clock
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`interconnect, a command interconnect, and a data interconnect. Id at 16. Under the assumption
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`that information can be sent along each interconnect (“information is ‘supplied on the data line
`
`concurrently with the read request command on the command line’”), the court determined that
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`Intel’s proposed “one bit at a time” construction was incorrect. Id. However, both Intel’s and
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`CRSR Defendants’ construction expressly focuses on the recited “data” that is sent over the
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`serial port (not “information” generally, including the read request sent over the command line in
`
`the court’s example) such that the Delaware court’s concern should have been appeased. The
`
`’804 Patent draws a clear distinction between, on one hand, “data” (communicated over the data
`
`interconnect) and “command” or “control” information (communicated over the command
`
`interconnect). For example, it distinguishes prior approaches that communicated “control
`
`information” and “data” over the same lines. Id. at 2:11-15; see id. at 5:43-51 (explaining which
`
`information is sent over the command versus data interconnects). The specification’s description
`
`of the relationship between the serial port, and the three different types of serial interconnects
`
`that it contains, informs the proper construction.
`
`Consistent with these disclosures, the specification portion upon which the Delaware
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`court relied is entirely consistent with CRSR Defendants’ construction, which requires only
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`transfer of data over the data interconnect one bit at time. ’804 Patent at 9:65-67. Indeed, a
`
`
`5 This Court is not bound by the prior construction from the District of Delaware because the
`Defendants here were not party to that litigation. Texas Instruments, Inc. v. Linear Techs. Corp.,
`182 F. Supp. 2d 580, 589-90 (E.D. Tex. 2002). Moreover, the case settled and the construction
`was not subject to appellate review.
`
`
`
`11
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`Case 6:21-cv-00263-ADA Document 35 Filed 10/28/21 Page 16 of 38
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`command for reading data in is shown in Figure 7B, which shows a read of 16 bits of da