Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 1 of 14
`
`
`
`
`
`
`
` Exhibit 6
`
`
`
`
`
`
`
`
`
`
`
` Exhibit 6
`
`
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 2 of 14
`
`U.S. Patent No. 6,807,505 (“’505 Patent”)
`
`Accused Products
`Apple products including computers containing JEDEC DDR4 SDRAM and related versions, such as the Apple Mac Pro
`(“Apple Mac Pro”) infringe at least Claim 1 of the ’505 Patent.
`
`Claim 1
`
`Claim 1
`1[pre]. An electronic circuit comprising:
`
`Apple Mac Pro
`To the extent the preamble is limiting, the Apple Mac Pro comprises an electronic
`circuit as claimed.
`For example, the Apple Mac Pro includes at least 32GB of 2666MHz DDR4 ECC
`memory compliant to DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`See, e.g.:
`
`
`
`1
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 3 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`1[a] a plurality of input/output (I/O)
`nodes for connecting the electronic
`circuit to a further electronic circuit via
`interconnects,
`
`https://www.apple.com/mac-pro/specs/
`The Apple Mac Pro comprises a plurality of input/output (I/O) nodes for connecting the
`electronic circuit to a further electronic circuit via interconnects.
`For example, the DDR4 memory within the Apple Mac Pro includes a plurality of I/O
`pins/nodes, such as BA0-1, BG0-1, A0-A9, A10/AP, A11, A12/BC_n, A13,
`
`
`
`
`
`2
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 4 of 14
`
`Claim 1
`
`Apple Mac Pro
`WE_n/A14, CAS_n/A15, RAS_n/A16, RESET_n, CKE, ACT_n, ODT, CLK_t,
`CLK_c, DML_n, DBIL_n, DMU_n/DBIU_n, Parity, and Alert_n, that are used to
`connect the DDR4 SDRAM to a further electronic circuit (e.g., memory controller or
`processor chip) via interconnecting wires between the I/O pins and pins of the further
`electronic circuit.
`See, e.g.:
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`
`
`
`
`3
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 5 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`
`
`
`
`
`
`4
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 6 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`1[b] a main unit for implementing a
`normal mode function of the electronic
`circuit,
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`The Apple Mac Pro comprises a main unit for implementing a normal mode function of
`the electronic circuit.
`For example, in the DDR4 memory within the Apple Mac Pro, during normal operation
`data transfer occurs between the internal DRAM core and the 8 DQs.
`See, e.g.:
`
`
`
`
`
`5
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 7 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`1[c] and a test unit for testing the
`interconnects,
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`The Apple Mac Pro comprises a test unit for testing the interconnects.
`For example, in the DDR4 memory within the Apple Mac Pro, the DDR4 memory
`device supports a connectivity test mode, in which circuitry generates MT[9:0] internal
`signals and generates, from the MT[9:0] signals, output signals.
`See, e.g.:
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`
`
`
`
`
`
`6
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 8 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`1[d] the electronic circuit having a
`normal mode in which the I/O nodes are
`logically connected to the main unit and
`a test mode in which the I/O nodes are
`logically connected to the test unit,
`
`
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`In the Apple Mac Pro, the electronic circuit has a normal mode in which the I/O nodes
`are logically connected to the main unit and a test mode in which the I/O nodes are
`logically connected to the test unit.
`For example, in the DDR4 memory within the Apple Mac Pro, in the normal mode of
`the DDR4 SDRAM, the I/O pins are connected to the main unit. The DDR4 CT mode is
`enabled through the Test Enable pin, entering a test mode in which the I/O pins (nodes)
`function as a set of test input and output pins and the normal memory function is
`bypassed.
`See, e.g.:
`
`
`
`7
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 9 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`
`
`
`
`
`
`
`
`8
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 10 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`
`
`
`
`
`
`9
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 11 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`In the Apple Mac Pro, the test unit comprises at least one combinatorial circuit
`implementing at least one of an XNOR function and an XOR function with at least two
`function inputs and a function output, the function inputs being connected to particular
`I/O nodes arranged to operate as input nodes of the test circuit and the function output
`being connected to a particular I/O node arranged to operate as output node of the test
`circuit.
`For example, the DDR4 SDRAM in the Apple Mac Pro has combinatorial circuits
`implementing XOR functions with three inputs connected to I/O pins and one output.
`See, e.g.:
`
`1[e] wherein the test unit comprises at
`least one combinatorial circuit
`implementing at least one of an XNOR
`function and an XOR function with at
`least two function inputs and a function
`output, the function inputs being
`connected to particular I/O nodes
`arranged to operate as input nodes of the
`test circuit and the function output being
`connected to a particular I/O node
`arranged to operate as output node of the
`test circuit.
`
`
`
`10
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 12 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`
`
`11
`
`
`
`
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 13 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`
`
`
`
`
`
`
`
`12
`
`
`
`Case 6:21-cv-00263-ADA Document 1-6 Filed 03/16/21 Page 14 of 14
`
`Claim 1
`
`Apple Mac Pro
`
`DDR4 JEDEC Standard JESD79-4, Sep. 2012.
`
`
`
`
`
`
`
`13
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
