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` Exhibit 4
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 2 of 12
`
`U.S. Patent No. 6,622,108 (“’108 Patent”)
`
`Accused Products
`Apple Products including GDDR5 RAM, including without limitation the MacBook Pro (“MacBook Pro”) infringe at least
`Claim 11 of the ’108 Patent.
`
`Claim 11
`
`Claim 11
`11[pre]. A method of testing
`interconnects between a first electronic
`circuit and a second electronic circuit, the
`first electronic circuit comprising a main
`unit implementing a normal mode
`function of the first electronic circuit, and
`a test unit for testing the interconnects,
`the method comprising the steps of
`
`MacBook Pro
`To the extent the preamble is limiting, the MacBook Pro practices the claimed method
`of testing interconnects between a first electronic circuit and a second electronic circuit,
`the first electronic circuit comprising a main unit implementing a normal mode function
`of the first electronic circuit, and a test unit for testing the interconnects.
`
`For example, the MacBook Pro tests interconnects between its CPU/GPU and its
`GDDR5 SGRAM, as described in more detail below. Among other things, the
`MacBook Pro is designed to operate its GDDR5 memory at a data rate of 4.8 Gbps,
`which requires use of the GDDR5 memory’s write training functionality.
`
`See, e.g.:
`
`
`
`
`1
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 3 of 12
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`Claim 11
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`MacBook Pro
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`https://www.ifixit.com/Teardown/MacBook+Pro+15-
`Inch+Unibody+Early+2011+Teardown/4990
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`2
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 4 of 12
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`Claim 11
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`MacBook Pro
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`https://www.ifixit.com/Teardown/MacBook+Pro+15-
`Inch+Touch+Bar+Teardown/73395
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`3
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 5 of 12
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`Claim 11
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`MacBook Pro
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`JEDEC Standard JESD212, Dec 2009
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`4
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 6 of 12
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`JEDEC Standard JESD212, Dec 2009
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`5
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 7 of 12
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`Claim 11
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`MacBook Pro
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`JEDEC Standard JESD212, Dec 2009
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`6
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 8 of 12
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`Claim 11
`11[a] logically connecting the test unit to
`the interconnects, and
`
`MacBook Pro
`The MacBook Pro logically connects the test unit to the interconnects.
`For example, during write training, the read FIFO of the GDDR5 SGRAM is connected
`to the DQ input/output lines.
`See, e.g.:
`
`
`
`7
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`
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 9 of 12
`
`Claim 11
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`MacBook Pro
`
`JEDEC Standard JESD212, Dec 2009
`
`
`8
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 10 of 12
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`Claim 11
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`MacBook Pro
`
`11[b] putting test data on the
`interconnects by the second electronic
`circuit,
`
`JEDEC Standard JESD212, Dec 2009
`The MacBook Pro performs putting test data on the interconnects by the second
`electronic circuit.
`For example, the GPU/CPU puts write training data on the DQ interconnects with the
`WRTR command.
`See, e.g.:
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`9
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 11 of 12
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`Claim 11
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`MacBook Pro
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`JEDEC Standard JESD212, Dec 2009
`
`
`11[c] wherein the putting step comprises
`operating the first electronic circuit as a
`low complexity memory by the second
`electronic circuit.
`
`JEDEC Standard JESD212, Dec 2009
`
`As performed by the MacBook Pro, the putting step comprises operating the first
`electronic circuit as a low complexity memory by the second electronic circuit.
`For example, during write training with the WRTR command, the data is written to an
`internal READ FIFO, not the array.
`See, e.g.:
`
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`JEDEC Standard JESD212, Dec 2009
`
`
`10
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`Case 6:21-cv-00263-ADA Document 1-4 Filed 03/16/21 Page 12 of 12
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`Claim 11
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`MacBook Pro
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`JEDEC Standard JESD212, Dec 2009
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`11
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