Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 1 of 31
`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 1 of 31
`
`EXHIBIT 3
`EXHIBIT 3
`
`
`
`
`
`

`

`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 2 of 31
`I 1111111111111111 11111 1111111111 1111111111 111111111111111 1111111111 11111111
`US007080330Bl
`
`c12) United States Patent
`Choo et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,080,330 Bl
`Jul. 18, 2006
`
`(54) CONCURRENT MEASUREMENT OF
`CRITICAL DIMENSION AND OVERLAY IN
`SEMICONDUCTOR MANUFACTURING
`
`6,650,424 Bl* 11/2003 Brill et al. .................. 356/601
`2002/0018217 Al*
`2/2002 Weber-Grabau et al. .... 356/601
`2002/0158193 Al* 10/2002 Sezginer et al. ........ 250/237 G
`
`(75)
`
`Inventors: Bryan Choo, Mountain View, CA (US);
`Bharath Rangarajan, Santa Clara, CA
`(US); Bhanwar Singh, Morgan Hill,
`CA (US); Carmen Morales, San Jose,
`CA (US)
`
`OTHER PUBLICATIONS
`
`Kynett et al.,"A in-system reprogrammable 32 Kx8 CMOS
`Flash Memory", Oct. 1988, IEEE Jpurnal of Solid-State
`Circuits, vol. 23, iss. 5, pp. 1157-1163.*
`
`* cited by examiner
`
`(73) Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, CA (US)
`
`Primary Examiner-Sun James Lin
`(74) Attorney, Agent, or Firm-Amin & Turocy, LLP
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 433 days.
`
`(57)
`
`ABSTRACT
`
`(21) Appl. No.: 10/379,738
`
`(22) Filed:
`
`Mar. 5, 2003
`
`(51)
`
`Int. Cl.
`G06F 17150
`(2006.01)
`(52) U.S. Cl. ............................... 716/4; 716/19; 716/21
`(58) Field of Classification Search .................... 716/4,
`716/19, 20, 21
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`A system and methodology are disclosed for monitoring and
`controlling a semiconductor fabrication process. One or
`more structures formed on a wafer matriculating through the
`process facilitate concurrent measurement of critical dimen(cid:173)
`sions and overlay via scatterometry or a scanning electron
`microscope (SEM). The concurrent measurements mitigate
`fabrication inefficiencies, thereby reducing time and real
`estate required for the fabrication process. The measure(cid:173)
`ments can be utilized to generate feedback and/or feed(cid:173)
`forward data to selectively control one or more fabrication
`components and/or operating parameters associated there(cid:173)
`with to achieve desired critical dimensions and to mitigate
`overlay error.
`
`5,042,009 A *
`
`8/1991 Kazerounian et al.
`
`. 365/185.18
`
`25 Claims, 18 Drawing Sheets
`
`START
`
`✓ 1400
`
`GENERAL INITIALIZATIONS
`
`GENERATE GRID MAP
`
`FORM STRUCTURE AT GRID
`MAPPED LOCATIONS
`
`1402
`
`1404
`
`1406
`
`MEASURE CRITICAL DIMENSIONS
`AND OVERLAY CONCURRENTLY
`
`1408
`
`COMPARE MEASUREMENTS TO
`ACCEPTABLE VALUES
`
`1412
`
`1420
`
`ADJUST PER FEED FORWARD
`
`1422
`
`PROCEED AS NORMAL
`
`ADJUST PER FEEDBACK
`
`1418
`
`END
`
`

`

`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 3 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 4 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 5 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 6 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 7 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 8 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 10 of 31
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`Jul. 18, 2006
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 11 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 12 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 13 of 31
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`U.S. Patent
`
`Jul. 18, 2006
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`Sheet 11 of 18
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`US 7,080,330 Bl
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`START
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`

`

`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 14 of 31
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`Jul. 18, 2006
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 15 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 17 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 18 of 31
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`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 19 of 31
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`

`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 20 of 31
`
`U.S. Patent
`
`Jul. 18, 2006
`
`Sheet 18 of 18
`
`US 7,080,330 Bl
`
`0.9 - - -
`
`Measured TanPsi signal
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`Fig. 21
`
`

`

`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 21 of 31
`
`US 7,080,330 Bl
`
`1
`CONCURRENT MEASUREMENT OF
`CRITICAL DIMENSION AND OVERLAY IN
`SEMICONDUCTOR MANUFACTURING
`
`TECHNICAL FIELD
`
`The present invention generally relates to monitoring
`and/or controlling a semiconductor fabrication process, and
`in particular to a system and methodology for concurrently
`measuring critical dimensions and overlay during the fab(cid:173)
`rication process and controlling operating parameters to
`refine the process in response to the measurements.
`
`BACKGROUND
`
`5
`
`2
`etry or a scanning electron microscope (SEM). The concur(cid:173)
`rent measurements mitigate fabrication inefficiencies as two
`operations are combined into one. The combined measure(cid:173)
`ments facilitate a reduction in, among other things, time and
`real estate required for the fabrication process. The mea(cid:173)
`surements can be utilized to generate control data that can be
`fed forward and/or backward to selectively adjust one or
`more fabrication components and/or operating parameters
`associated therewith to bring critical dimensions within
`10 acceptable tolerances and to mitigate overlay errors.
`To the accomplishment of the foregoing and related ends,
`certain illustrative aspects of the invention are described
`herein in connection with the following description and the
`annexed drawings. These aspects are indicative, however, of
`but a few of the various ways in which one or more of the
`principles of the invention may be employed and the present
`invention is intended to include all such aspects and their
`equivalents. Other advantages and novel features of the
`invention will become apparent from the following detailed
`description of the invention when considered in conjunction
`with the drawings.
`
`15
`
`20
`
`In the semiconductor industry, there is a continuing trend
`toward higher device densities. To achieve these high den(cid:173)
`sities, there has been and continues to be efforts toward
`scaling down device dimensions (e.g., at submicron levels)
`on semiconductor wafers. In order to accomplish such high
`device packing density, smaller and smaller feature sizes are
`required in integrated circuits (I Cs) fabricated on small
`rectangular portions of the wafer, commonly known as dies.
`This may include the width and spacing of interconnecting
`lines, spacing and diameter of contact holes, the surface 25
`geometry such as corners and edges of various features as
`well as the surface geometry of other features. To scale down
`device dimensions, more precise control of fabrication pro(cid:173)
`cesses are required. The dimensions of and between features
`can be referred to as critical dimensions (CDs). Reducing 30
`CDs, and reproducing more accurate CDs facilitates achiev(cid:173)
`ing higher device densities through scaled down device
`dimensions and increased packing densities.
`The process of manufacturing semiconductors or ICs
`typically includes numerous steps (e.g., exposing, baking, 35
`developing), during which hundreds of copies of an inte(cid:173)
`grated circuit may be formed on a single wafer, and more
`particularly on each die of a wafer. In many of these steps,
`material is overlayed or removed from existing layers at
`specific locations to form desired elements of the integrated
`circuit. Generally, the manufacturing process involves cre(cid:173)
`ating several patterned layers on and into a substrate that
`ultimately forms the complete integrated circuit. This lay(cid:173)
`ering process creates electrically active regions in and on the
`semiconductor wafer surface. The layer to layer alignment 45
`and isolation of such electrically active regions depends, at
`least in part, on the precision with which features can be
`placed on a wafer. If the layers are not aligned within
`acceptable tolerances, overlay errors can occur compromis(cid:173)
`ing the performance of the electrically active regions and 50
`adversely affecting chip reliability.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram schematically illustrating at a
`high level a system for monitoring and controlling a semi(cid:173)
`conductor fabrication process in accordance with one or
`more aspects of the present invention.
`FIG. 2 is a cross sectional side view of a structure in
`accordance with one or more aspects of the present inven(cid:173)
`tion that facilitates concurrent measurement of critical
`dimensions and overlay with scatterometry.
`FIG. 3 is a top view of a structure, such as that depicted
`in FIG. 2, that can be utilized to concurrently measure
`critical dimensions and overlay with scatterometry.
`FIG. 4 is a cross sectional side view of a structure in
`accordance with one or more aspects of the present inven(cid:173)
`tion that facilitates concurrent measurement of critical
`40 dimensions and overlay with a scanning electron microscope
`(SEM).
`FIG. 5 is a top view of a structure, such as that depicted
`in FIG. 4, that can be utilized to concurrently measure
`critical dimensions and overlay with SEM.
`FIG. 6 is a cross sectional side view of an alternative
`structure that facilitates concurrent measurement of critical
`dimensions and overlay with SEM.
`FIG. 7 illustrates a portion of a system for monitoring a
`semiconductor fabrication process with scatterometry
`according to one or more aspects of the present invention.
`FIG. 8 illustrates a system for monitoring and controlling
`a semiconductor fabrication process according to one or
`more aspects of the present invention.
`FIG. 9 illustrates a portion of a system for monitoring a
`semiconductor fabrication process with SEM according to
`one or more aspects of the present invention.
`FIG. 10 illustrates another system for monitoring and
`controlling a semiconductor fabrication process according to
`one or more aspects of the present invention.
`FIG. 11 illustrates a perspective view of a grid mapped
`wafer according to one or more aspects of the present
`invention.
`FIG. 12 illustrates plots of measurements taken at grid
`mapped locations on a wafer in accordance with one or more
`aspects of the present invention.
`
`SUMMARY OF THE INVENTION
`
`The following presents a simplified summary of the 55
`invention in order to provide a basic understanding of some
`aspects of the invention. This summary is not an extensive
`overview of the invention. It is intended to neither identify
`key or critical elements of the invention nor delineate the
`scope of the invention. Its purpose is merely to present some 60
`concepts of the invention in a simplified form as a prelude
`to the more detailed description that is presented later.
`According to one or more aspects of the present invention,
`one or more structures formed on a wafer matriculating
`through a semiconductor fabrication process facilitate con- 65
`current measurement of overlay and one or more critical
`dimensions in the fabrication process with either scatterom-
`
`

`

`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 22 of 31
`
`US 7,080,330 Bl
`
`3
`FIG. 13 illustrates a table containing entries correspond(cid:173)
`ing to measurements taken at respective at grid mapped
`locations on a wafer in accordance with one or more aspects
`of the present invention.
`FIG. 14 is flow diagram illustrating a methodology for
`monitoring and controlling an IC fabrication process accord(cid:173)
`ing to one or more aspects of the present invention.
`FIG. 15 illustrates an exemplary scatterometry system
`suitable for implementation with one or more aspects of the
`present invention.
`FIG. 16 is a simplified perspective view of an incident
`light reflecting off a surface in accordance with one or more
`aspects of the present invention.
`FIG. 17 is another simplified perspective view of an
`incident light reflecting off a surface in accordance with one
`or more aspects of the present invention.
`FIG. 18 illustrates a complex reflected and refracted light
`produced when an incident light is directed onto a surface in
`accordance with one or more aspects of the present inven(cid:173)
`tion.
`FIG. 19
`illustrates another complex reflected and
`refracted light produced when an incident light is directed
`onto a surface in accordance with one or more aspects of the
`present invention.
`FIG. 20 illustrates yet another complex reflected and
`refracted light produced when an incident light is directed
`onto a surface in accordance with one or more aspects of the
`present invention.
`FIG. 21 illustrates phase and/or intensity signals recorded
`from a complex reflected and refracted light produced when
`an incident light is directed onto a surface in accordance
`with one or more aspects of the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The present invention is now described with reference to
`the drawings, wherein like reference numerals are used to
`refer to like elements throughout. In the following descrip(cid:173)
`tion, for purposes of explanation, numerous specific details
`are set forth in order to provide a thorough understanding of
`the present invention. It may be evident, however, to one
`skilled in the art that one or more aspects of the present
`invention may be practiced with a lesser degree of these
`specific details. In other instances, well-known structures
`and devices are shown in block diagram form in order to
`facilitate describing one or more aspects of the present
`invention.
`The term "component" as used herein includes computer(cid:173)
`related entities, either hardware, a combination of hardware
`and software, software, or software in execution. For
`example, a component may be a process running on a
`processor, a processor, an object, an executable, a thread of
`execution, a program and a computer. By way of illustration, 55
`both an application running on a server and the server can be
`components. By way of further illustration, both a stepper
`and a process controlling the stepper can be components.
`It is to be appreciated that various aspects of the present
`invention may employ technologies associated with facili(cid:173)
`tating unconstrained optimization and/or minimization of
`error costs. Thus, non-linear training systems/methodologies
`(e.g., back propagation, Bayesian, fuzzy sets, non-linear
`regression, or other neural networking paradigms including
`mixture of experts, cerebella model arithmetic computer
`(CMACS), radial basis functions, directed search networks
`and function link networks) may be employed.
`
`25
`
`4
`FIG. 1 illustrates a system 100 for monitoring and con(cid:173)
`trolling an integrated circuit (IC) fabrication process accord(cid:173)
`ing to one or more aspects of the present invention. The
`system 100 includes a control system 102, fabrication com-
`5 ponents 104 of the process, a measurement system 106 and
`a wafer 108 undergoing the fabrication process. The wafer
`108 has one or more structures 110 formed therein according
`to one or more aspects of the present invention. The control
`system 102 is operatively coupled to the measurement
`10 system 106 and the fabrication components 104 and selec(cid:173)
`tively controls of the fabrication components 104 and/or one
`or more operating parameters associated therewith ( e.g., via
`feed forward and/or feedback) based upon readings taken by
`the measurement system 106. The measurement system 106
`15 includes either a scatterometry system or a scanning electron
`microscope (SEM) system (not shown) which interacts with
`the structure 110 to concurrently measure critical dimen(cid:173)
`sions and overlay. These concurrent measurements can be
`utilized to monitor and control the fabrication process while
`20 mitigating the amount oftest equipment, real estate and time
`required for the fabrication process. The measurements can,
`in particular, be utilized for generating feedback and/or
`feed-forward data for mitigating overlay and/or bringing
`critical dimensions within acceptable tolerances.
`It is to be appreciated that any of a variety of fabrication
`components and/or operating parameters associated there(cid:173)
`with can be selectively controlled based upon the readings
`taken by the measurement system 106. By way of example
`and not limitation, this can include, but is not limited to,
`30 temperatures associated with the process, pressures associ(cid:173)
`ated with the process, concentration of gases and chemicals
`within the process, composition of gases, chemicals and/or
`other ingredients within the process, flow rates of gases,
`chemicals and/or other ingredients within the process, tim-
`35 ing parameters associated with the process and excitation
`voltages associated with the process. By way of further
`example, parameters associated with high-resolution photo(cid:173)
`lithographic components utilized to develop IC's with small
`closely spaced apart features can be controlled to mitigate
`40 overlay errors and achieve desired critical dimensions. In
`general, lithography refers to processes for pattern transfer
`between various media and in semiconductor fabrication, a
`silicon slice, the wafer, is coated uniformly with a radiation(cid:173)
`sensitive film, the photoresist. The photoresist coated sub-
`45 strate is baked to evaporate any solvent in the photoresist
`composition and to fix the photoresist coating onto the
`substrate. An exposing source (such as light, x-rays, or an
`electron beam) illuminates selected areas of the surface of
`the film through an intervening master template for a par-
`50 ticular pattern. The lithographic coating is generally a radia(cid:173)
`tion-sensitized coating suitable for receiving a projected
`image of the subject pattern. Once the image from the
`intervening master template is projected onto the photore-
`sist, it is indelibly formed therein.
`Light projected onto the photoresist layer during photo-
`lithography changes properties (e.g., solubility) of the layer
`such that different portions thereof (e.g., the illuminated or
`un-illuminated portions, depending upon the photoresist
`type) can be manipulated in subsequent processing steps.
`60 For example, regions of a negative photoresist become
`insoluble when illuminated by an exposure source such that
`the application of a solvent to the photoresist during a
`subsequent development stage removes only non-illumi(cid:173)
`nated regions of the photoresist. The pattern formed in the
`65 negative photoresist layer is, thus, the negative of the pattern
`defined by opaque regions of the template. By contrast, in a
`positive photoresist, illuminated regions of the photoresist
`
`

`

`Case 6:20-cv-01216-ADA Document 41-3 Filed 10/06/21 Page 23 of 31
`
`US 7,080,330 Bl
`
`5
`become soluble and are removed via application of a solvent
`during development. Thus, the pattern formed in the positive
`photoresist is a positive image of opaque regions on the
`template. Controlling the degree to which a photoresist is
`exposed to illumination (e.g., time, intensity) can thus affect
`the fidelity of pattern transfer and resulting critical dimen(cid:173)
`sions and overlay. For example, overexposure can create
`features that are too thin, resulting in spaces which are larger
`than desired, while underexposure can create features that
`are too wide, resulting in spaces which are smaller than
`desired.
`The type of illumination utilized to transfer the image
`onto a wafer can also be controlled to affect critical dimen-
`sions. For instance, as feature sizes are driven smaller and
`smaller, limits are approached due to the wavelengths of the 15
`optical radiation. As such, that type of radiation and thus the
`wavelengths of radiation utilized for pattern transfers can be
`controlled to adjust critical dimensions and mitigate overlay.
`For instance, radiation having more conducive wavelengths
`( e.g., extreme ultraviolet (EUV) and deep ultraviolet (DUY) 20
`radiation having wavelengths within the range of 5-200 nm)
`can be utilized for lithographic imaging in an effort to
`accurately achieve smaller feature sizes. However, such
`radiation can be highly absorbed by the photoresist material.
`Consequently, the penetration depth of the radiation into the 25
`photoresist can be limited. The limited penetration depth
`requires use of ultra-thin photoresists so that the radiation
`can penetrate the entire depth of the photoresist in order to
`effect patterning thereof. The performance of circuits formed
`through photolithographic processing is, thus, also affected 30
`by the thickness of photoresist layers. The thickness of
`photoresist
`layers can be reduced
`through chemical
`mechanical polishing (CMP). In general, CMP employs
`planarization techniques wherein a surface is processed by a
`polishing pad in the presence of an abrasive or non-abrasive 35
`liquid slurry. The slurry employed reacts with the photoresist
`at the surface/subsurface range. Preferably the degree of
`reaction is not great enough to cause rapid or measurable
`dissolution ( e.g., chemical etching) of the photoresist, but
`merely sufficient to cause a minor modification of chemical 40
`bonding in the photoresist adequate to facilitate surface layer
`removal by applied mechanical stress ( e.g., via use of a CMP
`polishing pad). Thus, critical dimensions and overlay can be
`affected by controlling the concentration, rate of flow and
`degree of abrasiveness of slurry applied during the CMP 45
`process as well as the amount of pressure applied between
`the polishing pad and water during the process.
`Depending upon the resist system utilized, post exposure
`baking may also be employed to activate chemical reactions
`in the photoresist to affect image transfer. The temperatures 50
`and/or times that portions of the wafer are exposed to
`particular temperatures can be controlled to regulate the
`uniformity of photoresist hardening ( e.g., by reducing stand(cid:173)
`ing wave effects and/or to thermally catalyze chemical
`reactions that amplify the image). Higher temperatures can 55
`cause faster baking and faster hardening, while lower tem(cid:173)
`peratures can cause slower baking and correspondingly
`slower hardening. The rate and uniformity of photoresist
`hardening can affect critical dimensions and overlay, such
`as, for example, by altering the consistency of a line width. 60
`Accordingly, time and temperature parameters can be con(cid:173)
`trolled during post exposure baking to affect critical dimen(cid:173)
`sions and overlay.
`Operating parameters of an etching stage can similarly be
`controlled to achieve desired critical dimensions and to 65
`mitigate overlay. After illumination, the pattern image is
`transferred into the wafer from the photoresist coating in an
`
`6
`etching stage wherein an etchant, as well as other ingredi(cid:173)
`ents, are applied to the surface of the wafer by an excitation
`voltage or otherwise. The etchant removes or etches away
`portions of the wafer exposing during the development
`5 process. Portions of the wafer under less soluble areas of the
`photoresist are protected from the etchants. The less soluable
`portions of the photoresist are those portions that are not
`affected by the developer during the development process
`and that are not affected by the etchant during the etching
`10 process. These insoluble portions of the photoresist are
`removed in subsequent processing stage(s) to completely
`reveal the wafer and the pattern(s) formed therein. The
`concentration of materials utilized in etching can thus be
`controlled to achieve desired critical dimensions and to
`mitigate overlay for instance by affecting the accuracy with
`which selected portions of the wafer are etched away.
`Parameters relating to the type of template utilized to
`transfer an image onto a wafer can also be controlled to
`affect critical dimensions, layer to layer aligriment and
`overlay. Where the template is a reticle, the pattern is
`transferred to only one (or a few) die per exposure, as
`opposed to where the template is a mask and all ( or most) die
`on the wafer are exposed at once. Multiple exposures
`through a reticle are often performed in a step and scan
`fashion. After each exposure, a stage to which the wafer is
`mounted is moved or stepped to align the next die for
`exposure through the reticle and the process is repeated. This
`process may need to be performed as many times as there are
`die in the wafer. Thus, stepper movement can be controlled
`to mitigate overlay error ( e.g., by feeding fed forward and/or
`backward measurements to a stepper motor). The pattern
`formed within the reticle is often an enlargement of the
`pattern to be transferred onto the wafer. This allows more
`detailed features to be designed within the reticle. Energy
`from light passed through the reticle can, however, heat the
`reticle when the image is exposed onto the wafer. This can
`cause mechanical di