Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 1 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 1 of 13
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`EXHIBIT 17
`EXHIBIT 17
`
`
`
`
`
`

`

`case 620-cv-01216-a08 Document MUIETAATEATITITTAME
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 2 of 13
`US006566214B1
`
`US 6,566,214 B1
`(10) Patent No.:
`a2) United States Patent
`Lyonsetal.
`(45) Date of Patent:
`May20, 2003
`
`
`(54) METHOD OF MAKING A SEMICONDUCTOR
`DEVICE BY ANNEALING A METAL LAYER
`TO FORM METALSILICIDE AND USING
`THE METALSILICIDE AS A HARD MASK
`TO PATTERN A POLYSILICON LAYER
`.
`Inventors:
`(US);RemkumaeSubramantagCA
`
`(75)
`
`>
`>
`Sunnyvale, CA (US); Scott A. Bell, San
`Jose, CA (US); Todd P. Lukanc, San
`Jose, CA (US); Marina V. Plat, San
`Jose, CA (US)
`
`7/1992 Gilgen et al. oo. 437/52
`5,134,085 A *
`.......... 156/656
`5,160,407 A * 11/1992 Latchford et al.
`
`ee A :
`s\1008 Poke rennerran
`
`ee
`:
`oe
`COE Meee
`:
`5,498,555 A *
`3/1996 Lin veecscessesseseen 437/35
`
`5,605,854 A *
`2/1997 Yoo veces 437/44
`5,955,761 A *
`9/1999 Yoshitomiet al.
`........... 257/336
`
`4/2000 Tyer weeessseessseeeeeee
`ee 438/622
`6,046,098 A *
`
`
`wee 438/299
`5/2000 Wu.......
`6,069,044 A *
`wee 438/583
`6,127,249 A * 10/2000 Hu wu...
`w 438/683
`6,159,856 A * 12/2000 Nagano.....
`6,204,105 B1 *
`3/2001 Jung «oe 438/238
`OTHER PUBLICATIONS
`
`(73) Assignee: Advanced Micro Devices,Inc.,
`Sunnyvale, CA (US)
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`(*) Notice:
`
`Stanley Rolf: “Silicon Processing for the VLSI Era, vol. 2:
`Process Integration,” 1990, pp. 144-152, Lattice Press,
`Sunset Beach, California.
`* cited by examiner
`
`22)
`
`Filed:
`
`Jan. 17, 2002
`
`Primary Examiner—Carl Whitehead, Jr.
`Assistant Examiner—Stephen W. Smoot
`(74) Attorney, Agent, or Firm—Foley & Lardner
`(57)
`ABSTRACT
`
`(21) Appl. No.: 10/047,036
`(22)
`Int. Ch? we HOLL 21/3213; HO1L 21/336
`(51)
`
`(52) US. Ch. ceeccccccccccccsssee 438/305; 438/592; 438/655,|Amethod of making a semiconductor device is provided. A
`438/682; 438/683
`polysilicon layeris formed overa substrate and a metal layer
`(58) Field of Search oo...eee 438/301, 303,
`1S formed on the polysilicon layer. The metal layer and the
`438/306, 586, 592, 595, 648, 649, 655,
`polysilicon layer are annealed to form a metal silicide layer
`682. 683, 305
`on the polysilicon layer. The metal silicide layer is patterned
`,
`,
`and the polysilicon layer is then patterned using the pat-
`terned metal silicide layer as a mask. The patterned metal
`silicide and polysilicon layers may be used as a gate elec-
`trode of a MOSFET.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,460,435 A *
`4,818,715 A *
`
`7/1984 Maa oo... ceese eee 156/643
`4/1989 Chao wc cesses 437/44
`
`28 Claims, 5 Drawing Sheets
`
`25 =
`
`35C
`
`25C
`
`26A6
`
`23
`
`35
`25
`
`22
`
`21
`
`26A
`
`35C
`
`25
`
`22
`
`2
`
`1
`
`

`

`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 3 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 3 of 13
`
`U.S. Patent
`
`May20, 2003
`
`Sheet 1 of 5
`
`US 6,566,214 B1
`
`FIG. 1A
`PRIOR ART
`
`KY2
`
`1
`
`FIG. 1B
`PRIOR ART
`
`7A
`
`3A 5A
`
`_ogDiS
`
`FIG. 1C
`PRIOR ART
`p11A 118
`
`7
`
`op
`
`2
`
`1
`
`FIG. 1D
`PRIOR ART
`
`5A
`
`13pA
`
`1
`
`FIG. 1E
`PRIOR ART
`17.
`15 19
`
`7B 7A 9A 9p
`
`

`

`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 4 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 4 of 13
`
`U.S. Patent
`
`May20, 2003
`
`Sheet 2 of 5
`
`US 6,566,214 B1
`
`FIG. 2A
`
`33
`
`23
`
`FIG. 2B 3
`
`25
`
`25
`
`FIG. 2C
`26
`
`FIG. 2D
`26A
`
`35Sas
`
`FIG. 2E
`
`26A
`
`35A
`
`29
`
`

`

`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 5 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 5 of 13
`
`U.S. Patent
`
`May20, 2003
`
`Sheet 3 of 5
`
`US 6,566,214 B1
`
`FIG. 2F
`26A
`
`25A
`
`35A
`
`

`

`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 6 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 6 of 13
`
`U.S. Patent
`
`May20, 2003
`
`Sheet 4 of 5
`
`US 6,566,214 B1
`
`FIG. 3A
`
`26A
`
`23
`
`
`
`35
`25
`
`22
`
`21
`
`30B
`
`FIG. 3D
`
`35B
`
`29B
`
`

`

`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 7 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 7 of 13
`
`U.S. Patent
`
`May20, 2003
`
`Sheet 5 of 5
`
`US 6,566,214 B1
`
`FIG. 4A
`
`26A
`
`23
`
`35
`25
`
`22
`
`21
`
`FIG. 4B
`
`FIG. 4D
`
`35C
`
`25C
`
`

`

`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 8 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 8 of 13
`
`US 6,566,214 B1
`
`1
`METHOD OF MAKING A SEMICONDUCTOR
`DEVICE BY ANNEALING A METAL LAYER
`TO FORM METALSILICIDE AND USING
`THE METALSILICIDE AS A HARD MASK
`TO PATTERN A POLYSILICON LAYER
`
`BACKGROUND OF THE INVENTION
`A. Field of the Invention
`
`2
`ductor device, comprising forming a polysilicon layer over
`a substrate, forming a metal layer on the polysilicon layer,
`annealing the metal layer and the polysilicon layer to form
`a metal silicide layer on the polysilicon layer, forming a
`photoresist layer on the metal silicide layer, exposing the
`photoresist
`layer to radiation, patterning the photoresist
`layer to form a photoresist etching mask havinga first width,
`etching the metalsilicide layer using the photoresist etching
`mask as a mask to form a patterned metal silicide layer
`having a second width less than the first width, and etching
`the polysilicon layer using the patterned metalsilicide layer
`as a mask.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1A-1Eare side cross sectional views of a prior art
`salicide method.
`FIGS. 2A-2J are side cross sectional views of a method
`
`of making a MOSFETaccordingto a first preferred embodi-
`ment of the present invention.
`FIGS. 3A-3D areside cross sectional views of a method
`
`of patterning a gate electrode of a MOSFETaccording to a
`second preferred embodiment of the present invention.
`FIGS. 4A-4Dareside cross sectional views of a method
`
`10
`
`20
`
`25
`
`35
`
`40
`
`The invention relates generally to semiconductor device
`manufacturing and, more particularly,
`to using a silicide
`hard mask to pattern a gate electrode.
`B. Description of the Related Art
`According to another preferred aspect of the present
`In a conventional metal oxide semiconductorfield effect
`invention, there is provided a method of making a MOSFET,
`transistor (MOSFET), the gate electrode includes a lower
`comprising forming a gate insulating layer on a substrate,
`layer of doped polysilicon and an upper layer of metal
`forming a polysilicon layer on the gate insulating layer,
`silicide, such as titanium silicide. The metalsilicide layer is
`forming a metal
`layer on the polysilicon layer prior to
`conventionally formed by the salicide process illustrated in
`patterning the polysilicon layer, annealing the metal layer
`FIGS. 1A-E.Field oxide regions 2 and gate oxide layer 3 are
`and the polysilicon layer to form a metalsilicide layer on the
`formed on a silicon substrate 1. A polysilicon layer 5 is then
`polysilicon layer, forming a photoresist layer on the metal
`formed on the gate oxide layer 3, as illustrated in FIG. 1A.
`silicide layer, exposing the photoresist layer to radiation,
`The polysilicon layer 5 and the gate oxide layer 3 are then
`patterning the photoresist layer to form a photoresist etching
`patterned by conventional photolithography to form a lower
`mask havinga first width, patterning the metal silicide layer
`gate electrode layer 5A and a gate oxide 3A. Lightly doped
`using the photoresist etching mask as a mask to form an
`source and drain regions 7A, 9A are then implanted into the
`upper layer of a gate electrode, patterning the polysilicon
`substrate 1, using the gate electrode layer 5A as a mask, as
`layer using the patterned metal silicide layer as a mask to
`shown in FIG. 1B. A silicon oxide layer is then deposited
`form a lower gate electrode layer, doping the substrate to
`over the lower gate electrode layer 5A and anisotropically
`form first doped source and drain regions havingafirst
`etched to form sidewall spacers 11A and 11B. Heavily doped
`doping concentration using the gate electrode as a mask, and
`30
`source and drain regions 7B, 9B are then implanted into the
`forming conductive contacts on the first doped source and
`substrate 1 using the lower gate electrode layer 5A and the
`drain regions.
`sidewall spacers 11A, 11B as a mask, as shown in FIG. 1C.
`A metal layer 13, such as a titanium layer, is then deposited
`on the polysilicon gate electrode layer 5A,
`the sidewall
`spacers 11A, 11B and the exposed doped silicon source 7B
`and drain regions 9B, as illustrated in FIG. 1D. The resulting
`device is then annealed to react the metal layer 13 with the
`exposed polysilicon lowergate electrode layer 5A to form an
`upper metal silicide gate electrode layer 15 on the lower
`polysilicon gate electrode layer 5A and metalsilicide contact
`layers 17, 19 on the source 7B and drain regions 9B. The
`metal layer 13 does not substantially react with the oxide
`sidewall spacers 11A, 11B. The portions of the metal layer
`13 remaining over the spacers 11A, 11B are removed by a
`selective etch, which does not removethesilicide layers 15,
`17 and 19, as shown in FIG. 1E.
`The above described salicide process works well for wide
`gate electrodes. However, the present inventors have deter-
`mined that whenthe salicide process is used to form narrow
`gate electrodes, for example gate electrodes having a width
`of less than 0.25 microns, such gate electrodes suffer from
`poor conductivity and poor contact resistance. Thus, it is
`desirable to improve the conductivity and contact resistance
`of a narrow gate electrode containing a lower polysilicon
`layer and an upper metal silicide layer.
`SUMMARYOF THE INVENTION
`
`45
`
`of patterning a gate electrode of a MOSFETaccording to a
`third preferred embodiment of the present invention.
`
`DETAILED DESCRIPTION OF SPECIFIC
`EMBODIMENTS
`
`The present inventors have realized that the poor conduc-
`tivity and contact resistance of narrow polysilicon/metal
`silicide gate electrodes made bythe salicide method is due
`to poor alloying of the metal layer to the narrow patterned
`polysilicon lowergate electrode layer. Therefore, the present
`inventors have realized that the conductivity and contact
`resistance of a polysilicon/metal silicide gate may be
`improved by forming the metal layer on the polysilicon layer
`and annealing the two layers to form the metalsilicide layer
`According to one preferred aspect of the present
`prior to patterning the polysilicon layer. Subsequently, the
`invention, there is provided a method of making a semicon-
`metalsilicide layer may be patterned and then used as a hard
`ductor device, comprising forming a polysilicon layer over
`mask for patterning the polysilicon layer.
`a substrate, forming a metal layer on the polysilicon layer,
`annealing the metal layer and the polysilicon layer to form
`FIGS. 2A-2J illustrate a method of making a MOSFET
`a metalsilicide layer on the polysilicon layer, patterning the
`according to a first preferred embodiment of the present
`metal silicide layer, and patterning the polysilicon layer
`invention. Field oxide regions 22 and a gate insulating layer
`using the patterned metal silicide layer as a mask.
`23 are formed on a substrate 21, as shown in FIG. 2A. The
`substrate 21 is preferably a silicon substrate, but may
`According to another preferred aspect of the present
`
`invention, there is provided a method of making a semicon- comprise other materials, such as GaAs, InP orasilicon
`
`60
`
`65
`
`55
`
`

`

`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 9 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 9 of 13
`
`US 6,566,214 B1
`
`10
`
`15
`
`25
`
`35
`
`40
`
`45
`
`3
`4
`layer on a glass substrate (i.e., for a thin film transistor,
`layer 35A of a gate electrode, as shown in FIG. 2E. For
`TFT). The gate insulating layer 23 may comprise any one or
`example, the metal silicide layer 35 may be anisotropically
`moredesired insulating layers, such as silicon oxide, silicon
`etched using a chlorine or a fluorine based plasma, such as
`nitride or silicon oxynitride.
`SF,, SF,, Cl, and/or CF. The patterned metal silicide layer
`A polysilicon layer 25 is then formed on the gate insu-
`35A can act as a hard mask for the subsequent patterning of
`lating layer 23, as shown in FIG. 1A. Preferably,
`the
`the underlying polysilicon layer 25.
`polysilicon layer 25 is formed to a sufficient thickness and
`The polysilicon layer 25 is then patterned using the
`doped p or n type to a sufficient concentration to act as a
`patterned metal silicide layer 35A as a mask to form a lower
`lower layer of a gate electrode. The polysilicon layer is
`gate electrode layer 25A, as shown in FIG. 2F. Thestep of
`preferably 2000 to 5000 Angstroms, more preferably 3000
`patterning the polysilicon layer 25 preferably comprises
`to 4000 Angstromsthick and has a sheet resistance of 10-40
`anisotropically etching the polysilicon layer 25 using the
`ohms/sq, more preferably 15-20 ohms/sq.
`patterned metal silicide layer 35A and the photoresist etch-
`A metal layer 33 is then formed on the polysilicon layer
`ing mask 26A layer as a mask. Any etching gas or liquid
`25 prior to patterning the polysilicon layer 25 to form the
`which etches polysilicon, such as CF,, SF, or other plasma
`lower layer of a gate electrode, as shown in FIG. 2A. The
`may be used to anisotropically etch the polysilicon layer 25.
`metal layer 33 may comprise any metal which can form a
`If desired, the metal silicide layer 35 and the polysilicon
`metalsilicide by reacting with the polysilicon layer 25. For
`layer 25 may be anisotropically, sequentially etched during
`example, the metal layer 33 preferably comprises titanium,
`a single etching step using the same etching gas, such as CF,
`nickel or cobalt. However, any other metal which is capable
`plasma, using the photoresist etching mask 26A as a mask.
`20
`of formingasilicide, such as tungsten, platinum or tantalum,
`However, the metal silicide layer 35 and the polysilicon
`may be used instead. Preferably, the metal layer 33 has a
`layer 25 may also be etched during separate etching steps,
`thickness of 50 to 1000 Angstroms, most preferably,
`using a different etching gas or liquid.
`100-300 Angstroms. Layers 23, 25 and 33 may be formed
`the
`invention,
`In an alternative aspect of the present
`by any conventional deposition method, such as by chemical
`photoresist etching mask 26A is removedafter the step of
`vapor deposition (CVD) or by sputtering.
`patterning the metal silicide layer 35 but before the step of
`The metal layer 33 and the polysilicon layer 25 are then
`patterning the polysilicon layer 25. In this aspect of the
`annealed to form a metal silicide layer 35 on the polysilicon
`present invention, the metal silicide layer 35 is anisotropi-
`layer 25, as shown in FIG. 2B. For example, the annealing
`cally etched inafirst etching step, and the polysilicon layer
`may becarried out at 700° C. orless, such as at 650° C. for
`25 is etched using only the patterned metal silicide layer 35A
`30
`20-60 minutes in a furnace, or for less than a minute in a
`as a hardmask in a second etching step. In this case, the
`rapid thermal annealing apparatus. The anneal may be
`portions of the polysilicon layer 25 that are uncovered by the
`carried out
`in argon or nitrogen ambient,
`if desired.
`patterned metalsilicide layer 35A are anisotropically etched
`Furthermore,
`a second annealing step at a higher
`by an etching gas or liquid that selectively etches polysilicon
`temperature, such as 700° C. to 800° C. may be added to
`compared to metal silicide.
`decrease the metal silicide layer 35 sheet resistance. During
`If desired, the gate insulating layer 23 that is not covered
`the annealing step, the entire metal layer 33 and a portion of
`by the patterned polysilicon layer 25A is subsequently
`the polysilicon layer 25 are reacted to form the metalsilicide
`optionally etched. The insulating material of the gate insu-
`layer 35. The preferred thickness of the resulting metal
`lating layer may be etched away by an etching gas or liquid
`silicide layer 35 is 50 to 1000 Angstroms, most preferably,
`that preferentially removes the insulating material (ie.,
`100-300 Angstroms, such as 200 Angstroms.Preferably, the
`silicon oxide, nitride or oxynitride) but not the metalsilicide
`sheet resistivity of the metal silicide layer 35 is 0.5 to 2
`layer 35A.
`ohms/sq. The preferred metal silicide layers comprise tita-
`nium sicide, nickel silicide or cobalt silicide. However, other
`After patterning the gate electrode which comprises the
`metal silicide layers, such as tungsten, platinum or tantalum
`upper metal silicide layer 35A and the lower polysilicon
`silicide layers may be formed.
`layer 25A,the substrate 21 may be optionally doped to form
`lightly doped source 27A and drain 29A regions,if a lightly
`A photoresist layer 26 is then formed on the metalsilicide
`doped drain (LDD) MOSFETconfiguration is required, as
`layer 35, as shown in FIG. 2C. The photoresist layer 26 may
`shownin FIG. 2G. Otherwise, this step may be omitted. The
`have a thickness of 4000 to 6000 Angstroms for 193 nm or
`lightly doped source and drain regions may be formed by
`248 nm exposing radiation. However, if desired, the photo-
`self aligned ion implantation of p or n type ions into an
`resist layer 26 may comprise an ultra thin resist (UTR)
`oppositely doped substrate 21 using the patterned polysili-
`having a thickness of 2500 Angstromsor less, such as 1000
`con 25A and metalsilicide layers 35A of the gate electrode
`to 2000 Angstroms. Such UTR layers are especially advan-
`as a mask.If the gate insulating layer 23 is not etched away,
`tageous for low wavelength (i.e., 13 to 157 nm)lithography
`then the ion implantation is conducted through the exposed
`and for forming features having a linewidth of 2500 Ang-
`stroms or less on the substrate.
`portions of the gate insulating layer.
`After the first ion implantation step, sidewall spacers 31A
`and 31B are formed on the gate electrode 25A/35A, as
`shown in FIG. 2H. The sidewall spacers 31A, 31B may be
`formed by depositing an insulating layer, such as a silicon
`oxide layer, over the gate electrode 25A/35A and anisotro-
`pically etching the insulating layer.
`After forming the sidewall spacers 31A, 31B, the sub-
`strate 21 is doped to form heavily doped source 27B and
`drain 29B regions having a doping concentration higher than
`that of the lightly doped source 27A and drain 29Aregions.
`The heavily doped source and drain regions may be formed
`by self aligned ion implantation using the gate electrode
`
`50
`
`55
`
`60
`
`65
`
`The photoresist layer 26 is then selectively exposed to
`radiation (i.e., 157, 193 or 248 nm UV radiation,
`for
`example). For example,
`the photoresist layer 26 may be
`selectively exposed to radiation through a maskorreticle or
`by scanning a laser or electron beam in a pattern over the
`photoresist layer 26. The exposed photoresist layer 26 is
`then patterned (i.e., developed) to form a photoresist etching
`mask 26A having a first width, as shown in FIG. 2D.
`Preferably, the first width is 2500 Angstroms or less, most
`preferably 1000 to 2000 Angstroms.
`The metal silicide layer 35 is then patterned using the
`photoresist etching mask 26A as a mask to form an upper
`
`

`

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`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 10 of 13
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`US 6,566,214 B1
`
`5
`25A/35A and the sidewall spacers 31A, 31B as a mask, as
`shown in FIG. 21.
`
`After the source 27A/27B and drain 29A/29B regionsare
`formed in the substrate 21, conductive contacts 37, 39 are
`formed on the source 27B and drain 29B regions,
`respectively, as shown in FIG. 2J. The conductive contacts
`37,39 may comprise any one or more conductive materials,
`such as aluminum, doped polysilicon, titanium nitride, tita-
`nium and/or metal silicide.
`
`10
`
`6
`patterned metal silicide layer 35B which acts as an upper
`layer of a gate electrode, as shown in FIG. 3C. As shown in
`FIG. 3D, the patterned metal silicide layer 35B is then used
`as a mask to pattern the polysilicon layer 25 to form the
`lower layer 25B of the gate electrode, as described above.
`The photoresist etching mask 26B may be removed before
`or after the polysilicon layer 25 etching step shown in FIG.
`3D. The gate electrode 25B/35B of the second preferred
`embodiment has a narrower width than the gate electrode
`25A/35A of the first preferred embodiment. For example,
`the width of the gate electrode 25B/35B may be 0.25
`microns or less, preferably, 0.06 to 0.14 microns, most
`preferably 0.07 to 0.1 microns. The MOSFET is then
`completed, as shown in FIGS. 2G—2J and as described
`above.
`
`FIGS. 4A—4D illustrate a method of making a MOSFET
`using a silicide hardmasktrim process, according to a third
`preferred embodiment of the present invention. FIG. 4A
`illustrates the device shown in FIG. 2D. The device shown
`
`FIG. 4A is formed by the method of FIGS. 2A-2D, as
`described above.
`
`If desired, the contacts 37, 39 may comprise metalsilicide
`contacts made bythe salicide process. The salicide process
`includes forming a second metal layer, such as titanium, on
`the heavily doped source 27B and drain 29B regions, on the
`sidewall spacers 31A and 31B and over the metal silicide
`layer 35. If desired, an additional, second polysilicon layer
`may optionally be formed and patterned over the patterned
`metal silicide layer 35A prior to forming the sidewall
`spacers 31A, 31B in order to improve the conductivity of the
`gate electrode. The second metal layer is annealed to form
`metal silicide contacts 37, 39 on the heavily doped source
`27B and drain 29B regions. Preferably, the second metal
`
`layer comprises the same metal as the first metal layer 33, In FIG. 4A, the photoresist etching mask havingafirst
`such that it is at least partially integrated into the metal
`width 26A is formed on the metal silicide layer 35 and the
`silicide layer 35A or forms a second metal silicide layer by
`polysilicon layer 25. However, instead of using the photo-
`reaction with the optional second polysilicon layer, if the
`resist etching mask 26A as a maskto anisotropically etch the
`second polysilicon layer is present. The portions of the
`metalsilicide layer 35, metal silicide layer 35 is isotropically
`second metal layer remaining on the sidewall spacers 31A,
`over-etched. During the isotropic over-etching, the mask
`31B and/or the metal silicide layer 35A are then selectively
`26A is undercut, to form a patterned metalsilicide layer 35C,
`etched away using a selective etching liquid, such as dis-
`as shownin FIG. 4B. For example, the width of the patterned
`tilled water/H,0.,/NH,OH (5:1:1) to form the contacts 37,
`metalsilicide layer 35C is preferably 0.06 to 0.14 microns,
`39.
`most preferably 0.07 to 0.1 microns. Preferably, an etching
`liquid is used to preferentially etch the metal silicide layer 35
`to form the upper layer of the gate electrode 35C, such that
`the patterned metal silicide layer 35C has a third width
`whichis less than the first width of the photoresist etching
`mask 26A. Any suitable etching liquid capable of isotropi-
`cally etching the metal silicide layer may be usedto trim the
`silicide layer.
`By leaving the mask 26A on the metal silicide layer 35
`during the isotropic etching, the width, but not the thickness
`of the metal silicide layer is reduced. Therefore, the pat-
`terned metal silicide layer 35C has a sufficient thickness to
`act as a hardmask during the subsequent etching of the
`polysilicon layer 25. The mask 26A is then removed as
`shown in FIG. 4C.
`
`15
`
`30
`
`35
`
`40
`
`45
`
`FIGS. 3A-D and 4A-D illustrate alternative preferred
`embodiments of the present invention, where the photoresist
`layer is patterned to form a photoresist etching mask having
`a first width, and the metal silicide layer is patterned to form
`a patterned metal silicide hard mask having a second width
`less thanthe first width. All elements shown in FIGS. 3A—D
`and 4A—Dare the same as in FIGS. 2A—J, unless otherwise
`noted.
`
`FIGS. 3A-3Dillustrate a method of making a MOSFET
`using a photoresist
`trim process, according to a second
`preferred embodiment of the present invention. FIG. 3A
`illustrates the device shown in FIG. 2D. The device shown
`
`FIG. 3A is formed by the method of FIGS. 2A-2D, as
`described above.
`
`However, in an alternative aspect of the third preferred
`In FIG. 3A, the photoresist etching mask havingafirst
`embodiment,
`the photoresist etching mask 26 may be
`width 26A is formed on the metal silicide layer 35 and the
`removed before the isotropic etching of the metal silicide
`polysilicon layer 25. However, instead of using the photo-
`layer 35. In this case, the metal silicide layer 35 is first
`resist etching mask 26A as a maskto etch the metalsilicide
`anisotropically etched using the photoresist etching mask
`layer 35, the photoresist etching mask 26A is trimmed to
`26A, as shown in FIG. 2E. The mask 26A is then removed,
`form a second photoresist etching mask 26B having a
`narrower width than the first mask 26A. The mask 26A is
`and the exposed patterned metal silicide layer 35A of FIG.
`2E is isotropically etched to form the patterned metalsilicide
`layer 35C having a smaller width and thickness than layer
`35A, as shown in FIG. 4B. In this aspect of the third
`preferred embodiment, the metal silicide layer 35 should
`have a sufficient initial thickness such that the patterned
`metal silicide layer 35C has a sufficient thickness remaining
`after the isotropic etching to act as a hardmask during the
`etching of the polysilicon layer 25.
`After the hardmask trimming process, the patterned metal
`silicide layer 35C is then used as a hardmask to pattern the
`polysilicon layer 25 to form the lower layer 25C of the gate
`electrode, as shown in FIG. 4D. The gate electrode 25C/35C
`of the third preferred embodimenthas a narrower width than
`the gate electrode 25A/35A ofthe first preferred embodi-
`
`trimmed by isotropically etching it to form a photoresist
`etching mask 26B having the second widthless thanthe first
`width prior to the step of patterning the metal silicide layer
`35, as shown in FIG. 3B. During the isotropic etching, both
`the initial thickness and width of the mask 26A (shown by
`the dotted line in FIG. 3B) are reduced. For example, the
`width of the mask 26B is preferably 0.06 to 0.14 microns,
`most preferably 0.07 to 0.1 microns. Any suitable etching
`gas or liquid capable of isotropically etching photoresist,
`such as an oxygen containing plasma, may be used to trim
`the mask 26A.
`
`After the photoresist etching mask trimming process, the
`metal silicide layer 35 is anisotropically etched using the
`second photoresist etching mask 26B as a mask to form a
`
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`

`

`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 11 of 13
`Case 6:20-cv-01216-ADA Document 41-17 Filed 10/06/21 Page 11 of 13
`
`US 6,566,214 B1
`
`7
`ment. For example, the width of the gate electrode 25C/35C
`may be 0.25 microns or less, preferably, 0.06 to 0.14
`microns, most preferably 0.07 to 0.1 microns. The MOSFET
`is then completed, as shown in FIGS. 2G-—2J and as
`described above.
`
`The method of the preferred embodiments is advanta-
`geous because it allows the metal silicide layer to be used as
`a hardmaskduring the etching of the underlying polysilicon
`layer. The method of the preferred embodiments is espe-
`cially advantageous for forming small metal silicide/
`polysilicon features with high conductivity and low contact
`resistance. By forming the metalsilicide layer on the poly-
`silicon prior to patterning the polysilicon layer, a good
`quality silicide material may be obtained compared to form-
`ing a metalsilicide on a narrow, patterned polysilicon layer.
`Furthermore, since the silicide hardmask may be made
`thin, such as 100-300 Angstroms thick, a thin photoresist
`layer, such as a UTR layer, may be used as a mask in a
`preferred aspect of the present
`invention. Thus, a thin
`photoresist layer may be used to etch a thin underlying
`silicide layer because the thin photoresist layer would not
`significantly erode during the quick etching of the thin
`hardmask layer. In contrast, a thick photoresist
`layer is
`required to etch the thick polysilicon layer in the prior art
`salicide process because a thin photoresist layer, such as a
`UTRlayer, would erode away during the time consuming
`etching of the thick polysilicon layer. The thin photoresist
`allows the use of shorter wavelength exposing radiation
`compared to the thick 4000-5000 Angstrom photoresists,
`which allows the achievement of smaller mask widths and
`line widths of the conductive features comparedto the prior
`art salicide process. Furthermore, by using photoresist or
`hardmask trimming of the second and third preferred
`embodiments, even smaller mask widths and line widths of
`the conductive features may be achieved compared to the
`prior art salicide process.
`While the preferred embodiments have been described
`with respect to forming metal silicide/polysilicon gate elec-
`trodes for a MOSFET,the present inventionis not limited to
`forming gate electrodes. The metal silicide/polysilicon pat-
`tern described above may comprise any other conductive
`feature in a solid state device, such as electrodes which
`contact a doped region of a semiconductor device or inter-
`connects in upper level metallization of a semiconductor
`device. Furthermore, a single crystal silicon layer may be
`used instead of the polysilicon layer.
`While the invention has been described in detail and with
`reference to specific embodiments thereof, it will be appar-
`ent
`to one skilled in the art
`that various changes and
`modifications can be made therein without departing from
`8. The method of claim 1, wherein the step of etching the
`the scope of the invention. Thus, the breadth and scopeofthe
`metal silicide layer comprises:
`present
`invention should not be limited by any of the
`anisotropically etching the metal silicide layer using the
`above-described exemplary embodiments, but should be
`photoresist etching mask layer as a mask; and
`defined only in accordance with the following claims and
`isotropically etching the metal silicide layer after remov-
`their equivalents.
`Whatis claimedis:
`ing the photoresist etching mask.
`9. The method of claim 1, further comprising:
`1. A method of making a semiconductor device, compris-
`forming a gate insulating layer on the substrate prior to
`ing:
`forming the polysilicon layer;
`forming a polysilicon layer over a substrate;
`lightly doping the substrate to form lightly doped source
`forming a metal layer on the polysilicon layer;
`and drain regions using the patterned polysilicon layer
`annealing the metal layer and the polysilicon layer to form
`as a mask;
`a metal silicide layer on the polysilicon layer;
`forming sidewall spacers on the patterned polysilicon
`patterning the metalsilicide layer by:
`layer and the patterned metalsilicide layer;
`forming a photoresist layer on the metalsilicide layer;
`heavily doping the substrate to form heavily doped source
`exposing the photoresist layer to radiation;
`patterning the exposed photoresist
`layer to form a
`and drain regions using the patterned polysilicon layer
`
`photoresist etching mask havingafirst width; and and the sidewall spacers as a mask;
`
`8
`etching the metal silicide layer using the photoresist
`etching mask layer as a mask;
`patterning the polysilicon layer using the patterned
`metal silicide layer as a mask; and
`at least one of the following:
`(A) wherein the step of etching the metal silicide
`layer and the step of patterning the polysilicon
`layer comprise anisotropically etching the metal
`silicide layer and the polysilicon layer during a
`single etching step using the photoresist etching
`mask as a mask; or
`(B) further comprising removing the photoresist
`etching mask after the step of etching the metal
`silicide layer but before the step of patterning the
`polysilicon layer; or
`(C) wherein the step of etching the metal silicide
`layer comprises:
`anisotropically etching the metal silicide layer
`using the photoresist etching mask layer as a
`mask; and
`isotropically etching the metal silicide layer after
`removing the photoresist etching mask.
`2. The method of claim 1, wherein the step of patterning
`the polysilicon layer comprises etching the polysilicon layer
`using the patterned metal silicide layer and the photoresist
`etching mask layer as a mask.
`3. The method of claim 1, wherein the step of etching the
`metalsilicide layer and the step of patterning the polysilicon
`layer comprise anisotropically etching the metal silicide
`layer and the polysilicon layer during a single etching step
`using the photoresist etching mask as a mask.
`4. The method of claim 1, comprising removing the
`photoresist etching mask after the step of etching the metal
`silicide layer but before the step of patterning the polysilicon
`layer.
`5. The method of claim 1, wherein the step of etching the
`metalsilicide layer and the step of patterning the polysilicon
`layer comprise anisotropically