Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 1 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 1 of 19
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`EXHIBIT 11
`EXHIBIT 11
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`case 6:20-ev-01216-ADA DocumentMIIFMMHEIRUEAATA
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 2 of 19
`US006165695A
`
`United States Patent 55
`6,165,695
`[11] Patent Number:
`
` Yang etal. [45] Date of Patent: Dec. 26, 2000
`
`
`[54] THIN RESIST WITH AMORPHOUS SILICON
`HARD MASKFORVIA ETCH APPLICATION
`
`11/1999 Felter et al. wee 430/270.1
`5,989,776
`6,001,538 12/1999 Chen et al. o.eesecsseeneeeees 430/316
`6,025,117
`2/2000 Nakanoet al. oc eeeeeeeeeee 430/314
`
`[75]
`
`Inventors: Chih Yuh Yang, San Jose; Christopher
`F. Lyons, Fremont; Harry J. Levinson,
`Saratoga; Khanh B. Nguyen, San
`Mateo; Fei Wang; Scott A. Bell, both
`of San Jose, all of Calif.
`:
`:
`.
`[73] Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, Calif.
`
`FOREIGN PATENT DOCUMENTS
`62-128174
`6/1987
`Japan .
`
`Primary Examiner—MarkF. Huff
`Assistant Examiner—Saleha R. Mohamedulla
`Attorney, Agent, or Firm—Amin, Eschweiler & Turocy,
`LLP
`
`[21] Appl. No.: 09/203,150
`
`[57]
`
`ABSTRACT
`
`Filed:
`Dec. 1, 1998
`[22]
`7
`Tint, C1cceceeeseesecnsceneceneeeneesnes G03C 5/00
`[S51]
`[52] U.S. Ch. ceceeeeeeee 430/314; 430/316; 430/317;
`430/967
`[58] Field of Search o....c.cccccccceeeeee 430/311, 313,
`430/316, 314, 317, 967; 438/423, 424;
`216/39, 47, 72
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`11/1981 Ochi et al. eee teeee 430/286
`4,299,911
`8/1991 Rauschenbach et al.
`oe. 355/53
`5,040,020
`
`7/1996 Hill et al. we.
`« 427/533
`5,534,312
`
`5,580,687 12/1996 Leedy wo.ceeccessesessesestesesesesens 430/5
`5,757,077
`5/1998 Chunget al.
`eee 257/736
`5,786,262
`7/1998 Jang et al. occ 438/424
`5,817,567 10/1998 Jang et al. occ 438/427
`
`A method of forming a via structure is provided. In the
`method, a dielectric layer is formed on an anti-reflective
`coating (ARC) layer covering a first metal layer; and an
`amorphoussilicon layeris formed onthedielectric layer. An
`ultra-thin photoresist
`layer is formed on the amorphous
`silicon layer, and the ultra-thin photoresist layer is patterned
`with short wavelength radiation to define a pattern for a via.
`The patterned ultra-thin photoresist layer is used as a mask
`during a first etch step to transfer the via pattern to the
`amorphoussilicon layer. The first etch step includes an etch
`chemistry that is selective to the amorphoussilicon layer
`over the ultra-thin photoresist layer and the dielectric layer.
`The amorphoussilicon layer is employed as a hard mask
`during a second etch step to form a contact hole correspond-
`ing to the via pattern by etching portions of the dielectric
`layer.
`
`32 Claims, 9 Drawing Sheets
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 3 of 19
`20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 3 of 19
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 4 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 4 of 19
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`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 2 of 9
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 5 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 5 of 19
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`U.S. Patent
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`Dec. 26, 2000
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 6 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 6 of 19
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`U.S. Patent
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`Dec. 26, 2000
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 7 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 7 of 19
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`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 5 of 9
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 8 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 8 of 19
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`U.S. Patent
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`Dec. 26, 2000
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 9 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 9 of 19
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`U.S. Patent
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`Dec. 26, 2000
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`U.S. Patent
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`Sheet 8 of 9
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`6,165,695
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 10 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 10 of 19
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`Dec. 26, 2000
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 11 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 11 of 19
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`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 9 of 9
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`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 12 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 12 of 19
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`6,165,695
`
`1
`THIN RESIST WITH AMORPHOUS SILICON
`HARD MASKFOR VIA ETCH APPLICATION
`
`TECHNICAL FIELD
`
`2
`(EUV) radiation and/or deep UV radiation in fabricating
`vias. As noted above, EUV and deep UV radiation are
`preferred radiation sources in lithographic processes where
`fine resolution is desired. The short wavelengths of these
`types of radiation afford for fine patterning (e.g., critical
`feature sizes <0.25 um). However, these types of radiation
`are highly absorbed by photoresist material which conse-
`quently limits the depth of penetration by the radiation into
`the photoresist material.
`By employing an amorphoussilicon layer to be patterned
`as a hard mask for use in connection with etching the vias,
`In the semiconductor industry, there is a continuing trend
`the present invention affords for expanding available etch
`toward higher device densities. To achieve these high
`chemistries useable in EUV and/or deep UV lithographic
`densities, there has been and continues to be efforts toward
`processes. In particular,
`these types of lithographic pro-
`scaling down the device dimensions (e.g., at submicron
`cesses require the use of very thin photoresists as a result of
`levels) on semiconductor wafers. In order to accomplish
`the depth of penetration limitations of the short wavelength
`such high device packing density, smaller and smaller fea-
`radiation. Such very thin photoresists are limited in their
`ture sizes are required. This may include the width and
`capacity as etch barriers due to the thickness thereof.
`spacing of interconnecting lines, spacing and diameter of
`is
`In the present
`invention,
`the ultra-thin photoresist
`contact holes (vias), and the surface geometry such as
`employed in patterning and etching (e.g., with a high selec-
`comers and edges of various features.
`tivity fluorocarbon plasma) the amorphous silicon layer
`The requirement of small features with close spacing
`thereunder to form a hard mask. A via pattern formed in the
`between adjacent features requires high resolution photo-
`photoresist with the short wavelength radiation is transferred
`lithographic processes.
`In general,
`lithography refers to
`to the amorphoussilicon layer by a first etch step. The
`patterned amorphoussilicon layer is used as a hard mask for
`processes for pattern transfer between various media. It is a
`a subsequent secondetch step to etch a dielectric layer so as
`technique used for integrated circuit fabrication in which a
`to form contact holes therein corresponding to the via
`siliconslice, the wafer, 1s coated uniformly with a radiation-
`pattern. Thereafter, standard via formation processes are
`sensitive film, the photoresist, and an exposing source (such
`performed to fill
`the contact holes, planarize the filler
`as optical light, x-rays, or an electron beam) illuminates
`material, etc. to form the via having a cross-section with a
`selected areas of the surface through an intervening master
`largest transverse dimension less than 0.25 um. Thus, the
`template, the mask, for a particular pattern. The photoresist
`present invention affords for taking advantage of the fine
`receives a projected image of the subject pattern. Once the
`resolution patterning available from EUV and deep UV
`imageis projected, it is indelibly formed in the photoresist.
`lithographic processes and mitigates the limitations associ-
`The projected image may beeither a negative or a positive
`ated therewith with respect to etch chemistry.
`image of the subject pattern. Exposure of the photoresist
`One specific aspect of the present invention relates to a
`through a photomask causes the image area to becomeeither
`method of forminga via structure. In the method,a dielectric
`more or less soluble (depending on the coating) in a par-
`layer is formed on an anti-reflective coating (ARC) covering
`ticular solvent developer. The more soluble areas are
`a first metal layer. An amorphoussilicon layer is formed on
`removed in the developing process to leave the pattern
`the dielectric layer. An ultra-thin photoresist layer is formed
`image in the photoresist as less soluble polymer.
`on the amorphoussilicon layer, and the ultra-thin photoresist
`Projection lithography is a powerful and essential tool for
`layer is patterned with short wavelength radiation to define
`microelectronics processing. As feature sizes are driven
`a pattern for the via structure. The patterned ultra-thin
`smaller and smaller, optical systems are approaching their
`photoresist layer is used as a mask duringafirst etch step to
`limits caused by the wavelengths of the optical radiation. A
`transfer the via pattern to the amorphoussilicon layer. The
`recognized way of reducing the feature size of circuit
`first etch step includes an etch chemistry that is selective to
`elements is to lithographically image the features with
`the amorphoussilicon layer over the ultra-thin photoresist
`radiation of a shorter wavelength. “Long” or “soft” x-rays
`layer. The amorphoussilicon layer is employed as a hard
`(a.k.a, extreme ultraviolet (EUV)), wavelength range of
`lambda=50 to 700 Angstroms(A)are nowatthe forefront of
`mask during a second etch step to form a contact hole
`research in an effort to achieve the smaller desired feature
`corresponding to the via pattern by etching portions of the
`sizes.
`dielectric layer.
`Another aspect of the present invention relates to a via
`structure having a largest transverse dimension below about
`0.18 um. In formning the structure, In the method, a dielec-
`tric layer is formed on an anti-reflective coating covering a
`first metal layer. An amorphoussilicon layer is formed on
`the dielectric layer. An ultra-thin photoresist layer is formed
`on the amorphoussilicon layer. The ultra-thin photoresist
`layer is patterned with short wavelength radiation to define
`a pattern for the via structure. The ultra-thin photoresist
`layer is used as a mask duringa first etch step to transfer the
`via pattern to the amorphoussilicon layer, the first etch step
`including an etch chemistry that is selective to the amor-
`phoussilicon layer over the ultra-thin photoresist layer and
`the dielectric layer. The amorphoussilicon layer is used as
`a hard mask during a secondetch step to form a contact hole
`corresponding to the via pattern by etching portions of the
`dielectric layer.
`
`invention generally relates to photo-
`The present
`lithography, and moreparticularly relates to a method of
`forming sub-micron vias using short wavelength radiation
`and ultra-thin photoresists.
`BACKGROUND OF THE INVENTION
`
`Although EUV lithography provides substantial advan-
`tages with respect to achieving high resolution patterning,
`the shorter wavelength radiation is highly absorbed by the
`photoresist material. Consequently, the penetration depth of
`the radiation into the photoresist is limited. The limited
`penetration depth of the shorter wavelength radiation
`requires the use of ultra-thin photoresists so that the radia-
`tion can penetrate the entire depth of the photoresist in order
`to effect patterning thereof. However, the thinness of such
`ultra-thin photoresists results in the etch resistance thereof to
`be relatively low.
`In other words,
`the etch protection
`afforded by ultra-thin photoresists is limited which in turn
`limits the EUV lithographic process.
`SUMMARYOF THE INVENTION
`
`The present invention relates to a method to facilitate
`lithographic processes employing extreme ultra-violet
`
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`6,165,695
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`dielectric layer formed over the ARC layer of FIG. 4 in
`accordance with one aspect of the present invention;
`FIG. 6 is a schematic cross-sectional illustration of an
`
`3
`4
`FIG. 4 is a schematic cross-sectional illustration of a
`invention relates to a
`Another aspect of the present
`methodof forminga via structure. In the method,a dielectric
`metal layer having an anti-reflective coating (ARC) formed
`layer is formed on an anti-reflective coating coveringafirst
`thereon in accordance with one aspect of the present inven-
`metal layer. An amorphoussilicon layer is formed on the
`tion;
`dielectric layer, the amorphoussilicon layer having a thick-
`FIG. 5 is a schematic cross-sectional illustration of a
`ness within the range of 50 A-2000 A.An ultra-thin photo-
`resist layer is formed on the amorphoussilicon layer, the
`ultra-thin photoresist layer having a thickness within the
`range of 50 A-2000 A. Theultra-thin photoresist layer is
`amorphoussilicon layer formed over the dielectric layer of
`patterned with short wavelength radiation to define a pattern
`FIG. 5 in accordance with one aspect of the present inven-
`for the via structure, the short wavelength radiation falling
`tion;
`within the range of about 11 nm to 13 nm. The ultra-thin
`FIG. 7 is a schematic cross-sectional illustration of an
`photoresist layer is used as a mask duringafirst etch step to
`ultra-thin photoresist
`layer formed over the amorphous
`transfer the via pattern to the amorphoussilicon layer, the
`silicon layer of FIG. 6 in accordance with one aspect of the
`first etch step including an etch chemistry that is selective to
`present invention;
`the amorphous silicon layer over the ultra-thin photoresist
`FIG. 8 is a schematic cross-sectional illustration of the
`layer and the dielectric layer. The amorphoussilicon layeris
`ultra-thin photoresist layer of FIG. 7 undergoing a patterning
`used as a hard mask during a second etch step to form a
`step in accordance with one aspect of the present invention;
`contact hole corresponding to the via pattern by etching
`FIG. 9 is a schematic cross-sectional illustration of the
`portions of the dielectric layer.
`Yet another aspect of the present invention relates to a
`ultra-thin photoresist layer of FIG. 8 after the patterning step
`method of forming a multi-layered interconnect structure. In
`is substantially complete in accordance with one aspect of
`the method, a first dielectric layer is formed on an anti-
`the present invention;
`FIG. 10 is a schematic cross-sectional illustration of the
`reflective coating covering a first metal layer. An amorphous
`silicon layer is formed onthe dielectric layer, the amorphous
`silicon layer having a thickness within the range of 50
`A-2000 A. An ultra-thin photoresist layer is formed on the
`amorphous silicon layer,
`the ultra-thin photoresist, layer
`having a thickness within the range of 50 A-2000 A. The
`ultra-thin photoresist layer is patterned with short wave-
`length radiation to define a pattern for a via,
`the short
`wavelength radiation falling within the range of about 11 nm
`amorphoussilicon layer and dielectric layer of FIG. 11
`to 13 nm. Theultra-thin photoresist layer is used as a mask
`undergoing an etching step in accordance with one aspect of
`during a first etch step to transfer the via pattern to the
`the present invention;
`amorphoussilicon layer. The first etch step includes an etch
`FIG. 13 is a schematic cross-sectional illustration of the
`chemistry that is selective to the amorphoussilicon layer
`amorphoussilicon layer and dielectric layer of FIG. 12 after
`over the ultra-thin photoresist layer. The amorphoussilicon
`the etching step is substantially complete to form a contact
`layer is employed as a hard mask during a second etch step
`hole in accordance with one aspect of the present invention;
`to form a contact hole corresponding to the via pattern by
`FIG. 14 is a schematic cross-sectional illustration of the
`etching portions of the dielectric layer. The contact hole is
`filled with a conductive material so as to form the via. The
`contact hole of FIG. 13 undergoingafilling (plugging) step
`with a conductive material to form a via in accordance with
`hard mask is removed and the conductive material pla-
`narized via CMP. A second metal layer is formed over the
`via, and a second dielectric layer is formed over the second
`metal layer.
`To the accomplishmentof the foregoing and related ends,
`the invention, then, comprises the features hereinafter fully
`described and particularly pointed out in the claims. The
`following description and the annexed drawingsset forth in
`detail certain illustrative embodiments of the invention.
`These embodimentsare indicative, however, of but a few of
`the various ways in which the principles of the invention
`may be employed. Other objects, advantages and novel
`features of the invention will become apparent from the
`following detailed description of the invention when con-
`sidered in conjunction with the drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
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`amorphoussilicon layer of FIG. 9 undergoing an etching
`step in accordance with one aspect of the present invention;
`FIG. 11 is a schematic cross-sectional illustration of the
`
`amorphoussilicon layer of FIG. 10 after the etching step is
`substantially complete in accordance with one aspect of the
`present invention;
`FIG. 12 is a schematic cross-sectional illustration of the
`
`one aspect of the present invention;
`FIG. 15 is a schematic cross-sectional illustration of a via
`after the filling step of FIG. 14 is substantially complete in
`accordance with one aspect of the present invention;
`FIG. 16 is a schematic cross-sectional illustration of the
`conductive material of FIG. 15 undergoing a planarization
`process in accordance with one aspect of the present inven-
`tion;
`FIG. 17 is a schematic cross-sectional illustration of the
`
`via substantially complete in accordance with one aspect of
`the present invention;
`FIG. 18 is a schematic cross-sectional illustration of a
`
`second metal layer being formed over the via structure in
`accordance with one aspect of the present invention;
`FIG. 19 is a schematic cross-sectional illustration of the
`
`FIG. 1 is a prior art schematic cross-sectional illustration
`of a conventional patterned resist used in the formation of
`vias;
`FIG. 2 is a perspective illustration of a multi-layered
`interconnectstructure employing vias formed in accordance
`with one aspect of the present invention;
`FIGS. 3a—3e illustrate representative filled via structures
`which may be formed in accordance with the present inven-
`tion
`
`60
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`65
`
`second metal layer formed in substantial part in accordance
`with one aspect of the present invention;
`FIG. 20 is a schematic cross-sectional
`
`illustration of
`
`second dielectric layer being formed over the second metal
`layer in accordance with one aspect of the present invention;
`FIG. 21 is a schematic cross-sectional illustration of the
`
`second dielectric layer formed in substantial part so as to
`form a multi-layered interconnect structure in accordance
`with one aspect of the present invention; and
`
`

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`6,165,695
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`5
`FIG. 22 is a perspective illustration of the multi-layered
`interconnect structure of FIG. 21 in accordance with one
`
`aspect of the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The present invention will now be described with refer-
`ence to the drawings, wherein like reference numerals are
`usedto refer to like elements throughout. The method of the
`present invention will be described with reference to the
`formation of vias using a photolithographic process employ-
`ing radiation of short wavelength (e.g., EUV radiation
`and/or deep UVradiation) and an ultra-thin photoresist. The
`following detailed description is of the best modes presently
`contemplated by the inventors for practicing the invention.
`It should be understood that the description of these pre-
`ferred embodiments are merely illustrative and that they
`should not be taken in a limiting sense.
`FIG. 1 is a cross-sectional illustration of a conventional
`photoresist layer 20 being used in the formationof via(s). As
`shown, the photoresist layer 20 is substantially thick (e.g.,
`5,000-10,000 A). The photoresist layer 20 is shown pat-
`terned so as to define a via which will be etched into an
`
`underlying dielectric layer 22 so as to form a contact hole to
`an underlying anti-reflective coating layer 24 and a metal
`layer 26 However, the thickness of the photoresist layer 20
`is not conducive for use with short wavelength radiation
`because these types of radiation would be highly absorbed
`by the photoresist layer 20 and not penetrate the entire
`thickness “t” of the layer 20. As a result, such a conventional
`scheme for forming a via would not be able to take advan-
`tage of the improved resolution of patterning offered by the
`short wavelength radiation.
`Turning now to the present invention in detail, FIG. 2
`illustrates an interconnect structure 30 having vias 32
`formed in accordance with the present invention. The vias
`32 are filled with a suitable material (e.g., tungsten, copper)
`to form plugs which provide conductive pathways through
`an insulating dielectric medium 40 to connect interconnects
`of different conductor layers 50, 52. Although, the present
`invention is described with respect to forming only two
`conductive layers 50, 52 for ease of understanding,it is to be
`appreciated that many more conductive layers (selectively
`electrically isolated with the dielectric material 40) may be
`formed, and suchstructures are intended to fall within the
`scope of the hereto appended claims.
`The vias 32 are formed employing photolithographic
`techniques utilizing short wavelength radiation and ultra-
`thin photoresists. Accordingly, substantially smaller dimen-
`sions of the vias 32 are achieved as compared to vias formed
`in accordance with the prior art technique discussed with
`respect
`to FIG. 1. For example,
`the vias 32 may have
`respectively a critical feature dimension of less than about
`0.25 um, and such small dimension is not typically obtain-
`able using conventional lithographic processes. In another
`embodiment, the vias may have respectively a critical fea-
`ture dimension of less than about 0.18 um.
`FIGS. 3a—3e illustrate representative filled via structures
`which may be formed in accordance with the present inven-
`tion. FIG. 3a depicts a via structure 32, which is substan-
`tially cylindrical and has a substantially circular cross-
`section 34. A diameter “d,,” of the cross-section 34a in one
`particular embodimentis less than about 0.25 um. In another
`embodiment, the d, is less than about 0.18 um.
`FIG. 35 depicts a via structure 32, which is substantially
`cylindrical and has a substantially elliptical cross-section
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`34,. A length dimension for a major axis “d,” of the
`cross-section 34, in one particular embodimentis less than
`about 0.25 wm. In another embodiment, the d, is less than
`about 0.18 um.
`FIG. 3c depicts a via structure 32, which is substantially
`cylindrical and has a substantially square cross-section 34...
`A diagonal length dimension “d,.”of the cross-section 34, in
`one particular embodiment is less than about 0.25 wm. In
`another embodiment, the d, is less than about 0.18 um.
`FIG. 3d depicts a via structure 32,, which is substantially
`cylindrical and has a substantially rectangular cross-section
`34,. A diagonal length dimension “d,” of the cross-section
`34d in one particular embodimentis less than about 0.25 um.
`In another embodiment, the d, is less than about 0.18 um.
`FIG. 3e depicts a via structure 32, which is substantially
`cylindrical and has a substantially irregular shaped cross-
`section 34,. A largest transverse dimesion “d,” of the cross-
`section 34, in one particular embodimentis less than about
`0.25 um. In another embodiment, the d, is less than about
`0.18 um.
`The various aforementioned dimensions (d,, d,, d., dy,
`and d,) will be referred to as the largest
`transverse
`dimensions, which are respectively the maximum length
`dimension of a transverse cross-section of the via 32 with
`
`respect to a y-axis as shown in FIGS. 3a-3e.
`Turning now to FIGS. 421, the fabrication of the vias 32
`is discussed in greater detail. FIG. 4 is a cross-sectional
`illustration of a first metal layer 60, which is part of the
`conductive layer 50 (FIG. 2) and a graded anti-reflective
`coating (ARC) 62 formed thereon. Although not shown,it is
`to be appreciated that the first metal layer 60 may be formed
`over a substrate, for example. The first metal layer 60 may
`comprise any suitable conductive material employable for
`forming conductive patterns in the semiconductor industry.
`Preferably,
`the conductive material
`includes a member
`selected from the group consisting of refractory materials,
`such as titanium and titanium alloys, tungsten and tungsten
`alloys, aluminum and aluminum alloys, copper and copper
`alloys and polycrystalline silicon. The ARC 62 is left over
`from a previous patterning of the first metal layer 60 (e.g.,
`to pattern metal lines). The ARC 62 preferably comprises
`titanium nitride (TiN), however, any like material may be
`employed. The ARC 62 serves as an etch stop layer for a
`dielectric etch step discussed in greater detail below. The
`ARC 62 is conductive and thus if remaining after the
`dielectric etch, the ARC 62 will not inhibit an electrically
`conductive connection between the first metal layer 60 and
`the via 32 which mayserve as an electrically conductive link
`to another metal layer or element(e.g., conductive line).
`Furthermore, the ARC 62 serves as an etch stop region
`during the dielectric etch to provide for a margin of error in
`the dielectric etch so as to mitigate damageto the first metal
`layer 60 by the dielectric etch. The thickness of the ARC
`layer 62 is preferably within the range of 300 A-1500 A,
`however, any thickness suitable for carrying out the afore-
`mentioned functions of the ARC 62 may be employed.
`FIG. 5 illustrates a dielectric layer 66 formed over the
`ARClayer 62. The dielectric layer 66 is part of the dielectric
`40. The dielectric layer provides for insulating conductive
`elements (e.g., adjacent metal lines) from each other so as to
`mitigate electrical shorting and/or capacitive crosstalk there
`between. Preferably, the dielectric layer 66 includestetra-
`ethyorthosilicate (TEOS) However, and suitable insulating
`material (e.g., phosphosilicate glass (PSG), borophospho-
`silicate glass (BPSG), any suitable spin-on glass (SOG), or
`polyimides having a suitably low dielectric constant) may be
`
`

`

`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 15 of 19
`Case 6:20-cv-01216-ADA Document 41-11 Filed 10/06/21 Page 15 of 19
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`6,165,695
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`7
`employed. The dielectric layer 66 may be deposited by any
`suitable process (e.g., Low Pressure Chemical Vapor Depo-
`sition (LPCVD), Plasma Enhanced Chemical Vapor Depo-
`sition (PECVD), or High Density Plasma Chemical Vapor
`Deposition (HDPCVD)) to a desired thickness.
`Next, as shown in FIG. 6, an amorphoussilicon layer 70
`is formedoverthe dielectric layer 66. The amorphoussilicon
`layer 70 will serve as a hard mask during etching of the
`underlying dielectric layer 66. Any suitable technique for
`forming the amorphoussilicon layer 70 may be employed
`such as LPCVD, PECVD, HDCVD, sputtering or high
`density plasma chemical vapor deposition (HDPCVD)tech-
`niques to a thickness suitable for serving as a hard mask for
`a selective etch of the dielectric layer 66. Thus, for example,
`in one aspect of the present invention the thickness of the
`amorphoussilicon layer 70 is between the range of about 50
`A-10,000 A. In another aspect, the thickness of the amor-
`phous silicon layer 70 is between the range of about 50
`A-5000 A. In another aspect, the thickness of the amor-
`phous silicon layer 70 is between the range of about 50
`A-3000 A. In another aspect, the thickness of the amor-
`phous silicon layer 70 is between the range of about 50
`A-2000 A. In another aspect, the thickness of the amor-
`phoussilicon layer 70 is between the range of about 50
`A-1500 A. In another aspect, the thickness of the amor-
`phoussilicon layer 70 is between the range of about 50
`A-1000 A. In still another aspect,
`the thickness of the
`amorphoussilicon layer 70 is betweenthe range of about 50
`A-500 A.
`FIG. 7 illustrates an ultra-thin photoresist layer 80 formed
`over the amorphoussilicon layer 70. The ultra-thin photo-
`resist layer 80 has a thickness of about 500 A-5000 A,
`however, it is to be appreciated that the thickness thereof
`may be of any dimension suitable for carrying out
`the
`present invention. Accordingly, the thickness of the ultra-
`thin photoresist 80 can vary in correspondence with the
`wavelength of radiation used to pattern the ultra-thin pho-
`toresist 80. One aspect of the present invention provides for
`formingthe ultra-thin photoresist layer 80 to have a thick-
`ness within the range of 1000 A to 4000 A. Another aspect
`of the present invention provides for forming the ultra-thin
`photoresist layer 80to have a thickness within the range of
`2000 A to 3000 A. Yet another aspect of the present
`invention provides for forming the ultra-thin photoresist
`layer 80 to have a thickness within the range of 500 Ato
`2000 A. The ultra-thin photoresist 80 may be formed over
`the amorphous silicon layer 70 via conventional spin-
`coating or spin casting deposition techniques.
`The ultra-thin photoresist layer 80 has a thickness suitable
`for functioning as a mask for etching the underlying amor-
`phoussilicon layer 70 and for forming patterns or openings
`in the developed ultra-thin photoresist layer 80 that are 0.25
`um or less. Since the ultra-thin photoresist
`layer 80 is
`relatively thin compared with I-line, regular deep UV, and
`other photoresists, improved critical dimension control is
`realized.
`
`Ultra-thin resists are processed using small wavelength
`radiation. Small wavelength radiation increases precision
`and thus the ability to improve critical dimension control.
`Specific examples of wavelengths to which the ultra-thin
`photoresist 80 is sensitive (undergo chemical transformation
`enabling subsequent development) include about 248 nm,
`about 193 nm, about 157 nm, about 13 nm and about 11 nm,
`and as low as 4 nm. Specific sourcesof radiation include KrF
`excimer lasers having a wavelength of about 248 nm, a
`XeHg vapor lamp having a wavelength from about 200 nm
`to about 250 nm, mercury-xenon arc lamps having a wave-
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`length of about 248 nm, an ArF excimer laser having a
`wavelength of about 193 nm, an F, excimer laser having a
`wavelength of about 157 nm, and EUV having a wavelength
`of about 15 nm to about 10 nm, and as low as 4 nm.
`Positive or negative ultra-thin photoresists may be
`employed in the methods of the present
`invention. An
`example of a deep UV chemically amplified photoresist is a
`partially t-butoxycarbonyloxy substituted poly-p-
`hydroxystyrene. Photoresists are commercially available
`from a number of sources,
`including Shipley Company,
`Kodak, Hoechst Celanese Corporation, Brewer and IBM.
`The scope of the present i