Case 6:20-cv-01216-ADA Document 41-1 Filed 10/06/21 Page 1 of 8
`Case 6:20-cv-01216-ADA Document 41-1 Filed 10/06/21 Page 1of8
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`EXHIBIT 1
`EXHIBIT 1
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`(12) United States Patent
`Pike et al.
`
`USOO6420097B1
`(10) Patent No.:
`US 6,420,097 B1
`(45) Date of Patent:
`Jul. 16, 2002
`
`(54) HARDMASK TRIM PROCESS
`
`(75) Inventors: Christopher L. Pike, Fremont; Scott
`A. Bell, San Jose, both of CA (US)
`s
`s
`(73) ASSignee: Advance Miyevices, Inc.,
`unnyvale, CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`- - -
`(*) Notice:
`
`(21) Appl. No.: 09/562,659
`1-1.
`(22) Filed:
`May 2, 2000
`(51) Int. Cl." .................................................. GO3F 7/36
`(52) U.S. Cl. ...
`... 430/313; 430/317; 430/322;
`430/328
`(58) Field of Search ................................. 430/313, 317,
`430/322,328
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,139.904 A 8/1992 Auda
`5,324,676 A
`6/1994 Guterman .................... 437/43
`
`5.431,770 A 7/1995 Lee
`5,804,088 A 9/1998 McKee
`5,885,887 A 3/1999 Hause et al. ................ 438/564
`5,930,634 A * 7/1999 Hause et al................. 438/307
`5,965,461. A 10/1999 Yang et al.
`6,020,111 A
`2/2000 Mihara ....................... 430/318
`6,121,123 A * 9/2000 Lyons et al. ................ 438/585
`6,156,485 A * 12/2000 Tang et al. ................. 430/313
`6,194,323 B1 * 2/2001 Downey et al. ............ 438/717
`6,277,750 B1 * 8/2001 Pawlowski et al. ......... 438/689
`6,281,130 B1
`8/2001 Pike ........................... 438/693
`* cited by examiner
`Primary Examiner Janet Baxter
`ASSistant Examiner Amanda C. Walke
`(74) Attorney, Agent, or Firm-Davis Chin
`(57)
`ABSTRACT
`
`An improved method of forming circuit Structures having
`linewidths which are smaller than what is achievable by
`conventional UV lithographic techniqueS on ultra-thin resist
`layers is provided. The method includes a hardmask which
`is patterned using an ultra-thin resist layer and is then
`trimmed to reduce the width of the hardmask before etching
`the underlying gate conductive layer.
`
`17 Claims, 3 Drawing Sheets
`
`RESIST
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`U.S. Patent
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`Jul. 16, 2002
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`Sheet 1 of 3
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`US 6,420,097 B1
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`Fig. 1 a
`(Prior Art)
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`1 O
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`Fig. 2a
`(Prior Art)
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`18a
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`18
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`SUBSTRATES
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`Jay Na.NSN
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`Fig. 1b
`(Prior Art)
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`(Prior Art)
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`22a
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`16a
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`14a
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`Fig. 1C
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`Fig. 2C
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`(Prior Art)
`V
`sistrate
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`FLM30a
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`U.S. Patent
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`Jul. 16, 2002
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`Sheet 2 of 3
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`US 6,420,097 B1
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`Fig. 3
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`3O2
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`3O4
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`3O6
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`31 O
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`312
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`DEPOST HARDMASKOVER FILM TO BEETCHED
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`DEPOSITRESISTLAYER OF LESS THAN 2500A OVER HARDMASK
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`IMAGE TRANSFER TO RESIST LAYER
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`ETCH HARDMASK TO WIDTH SMALLER THAN THE INTIAL WDTH
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`REMOVERESIST
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`ANSOTROPICALLY ETCH FILMUSINGHARDMASK
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`U.S. Patent
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`Jul. 16, 2002
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`Sheet 3 of 3
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`US 6,420,097 B1
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`'S HARDMASK 118
`i
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`Fig. 4e
`HARDMASK
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`HARDMASK
`126
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`1 14
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`Fig. 4d
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`US 6,420,097 B1
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`1
`HARDMASK TRIM PROCESS
`BACKGROUND OF THE INVENTION
`This invention relates generally to manufacturing pro
`ceSSes for fabricating Semiconductor integrated devices.
`More particularly, it relates to an improved method of
`forming circuit Structures having linewidths which are
`smaller than what is achievable by conventional UV litho
`graphic technology on ultra-thin resist layers.
`AS is generally known to those in the Semiconductor
`industries, there is a continuing trend of manufacturing
`Semiconductor integrated circuits with higher and higher
`densities on a Smaller chip area. As a consequence of this
`desire for large Scale integration, this has led to a continued
`Shrinking of the circuit dimensions and features of the
`devices So as to reduce manufacturing costs and to improve
`circuit functionality. The ability to reduce the size Structures
`Such as shorter gate lengths in field-effect transistorS is
`driven by lithographic technology which is, in turn, depen
`dent upon the wavelength of light used to expose the
`photoresist. Currently, optical StepperS eXpose the photore
`sist using light having a wavelength of 248 nm is widely
`used in manufacturing, but a radiation having a wavelength
`of 193 nm is being experimented in research and develop
`ment laboratories. Further, the next generation lithographic
`technologies will in all likelihood progreSS toward a radia
`tion having a wavelength of 157 nm and even shorter
`wavelengths, such as those used in Extreme Ultra-Violet
`(EUV) lithography (s13 nm).
`AS the wavelength of the radiation decreases, Such classic
`image exposure techniques cannot be used to Satisfactorily
`generate the pattern line widths in the photoresist of less than
`0.25 um (2500 A). This is due to the fact that the organic
`based photoresist materials will become increasingly opaque
`to the radiation. In order to overcome this drawback, there
`has been developed in recent years of using ultra-thin resist
`(UTR) coatings in order to maintain the desired character
`istics of the masked photoresist structures (e.g., near vertical
`Sidewalls for the resist profiles, maximum exposure/focus
`latitude). In the current state-of-the-art, integrated circuit
`manufacturers have been using in the resist process a resist
`coating having a Standard photoresist thickness of more than
`0.5um (5,000 A) for 248 nm lithography and 0.4 um (4,000
`A) for 193 nm lithography. Thus, a resist coating having an
`UTR thickness is considered to be resist films of less than
`0.25 um (2500 A) in thickness.
`However, the use of UTR coating is not without any
`problems. The use of UTR coating suffer from the disad
`Vantage that during the etch process the films being etched
`often do not Scale down as rapidly as the thickness of the
`resist coating. In addition, even when Such films can be
`Scaled down or the Selectivity of the etch proceSS can be
`improved, the increasing use of trim (controlled line width
`reduction) process can fully consume the etch process
`margin for the underlying film. Thus, it has been recognized
`that a major problem to date of using UTR coating is related
`to etching underlying films when used with trim processes.
`Accordingly, there is still a need of providing a fabrication
`proceSS for forming circuit Structures Smaller than the capa
`bility of the lithographic technology while using ultra-thin
`resist processes. This is achieved in the present invention by
`utilizing a hardmask which is patterned using resist and is
`then trimmed so as to reduce the linewidth of the hardmask
`before etching the underlying film.
`SUMMARY OF THE INVENTION
`Accordingly, it is a general object of the present invention
`to provide an improved method of forming circuit Structures
`
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`2
`having linewidths which are smaller than what is achievable
`by conventional UV lithographic technology on ultra-thin
`resist layers.
`In accordance with a preferred embodiment of the present
`invention, there is provided an improved method of forming
`circuit structures having line widths which are Smaller than
`the capabilities of typical UV lithographic techniqueS on
`ultra-thin resist layers. A Semiconductor wafer Stack is
`provided which is formed of a Substrate and a gate conduc
`tive layer above the Substrate. A hardmask layer is deposited
`over the gate conductive layer. An ultra-thin resist layer is
`then deposited over the hardmask layer.
`A resist mask is formed which has an initial linewidth.
`The hardmask layer is isotropically over-etched to form a
`hardmask having a final line width which is narrower than
`the initial linewidth of the resist mask and corresponds to a
`desired gate line width. The gate conductive layer as defined
`by the hardmask is anisotopically etched to form a gate
`having a width substantially equal to the final linewidth of
`the hardmask.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`These and other objects and advantages of the present
`invention will become more fully apparent from the follow
`ing detailed description when read in conjunction with the
`accompanying drawings with like reference numerals indi
`cating corresponding parts throughout, wherein:
`FIGS. 1(a)-1(d) illustrate cross-sectional views of a con
`ventional lithographic process utilizing a standard resist
`having a thickness of about 5000 A;
`FIGS. 2(a)-2(d) illustrate the problem of applying the
`conventional lithographic process of FIGS. 1(a)-1(d) to an
`UTR having a thickness of less than 2500 A;
`FIG. 3 is a process flow of the lithographic process in
`accordance with the principles of the present invention; and
`FIGS. 4(a)-4(f) illustrate cross-sectional views of the
`lithographic process of the present invention in FIG. 3.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`A major concern in the conventional UV lithographic
`process associated with ultra-thin resist layerS is that trim
`ming of Such resist films will not leave Sufficient amount of
`material to completely etch the underlying film. The purpose
`of this invention is to provide an improved method of
`forming circuit Structures having line widths which are
`smaller than what is achievable by the conventional UV
`lithographic techniques on ultra-thin resist layers.
`Before describing in detail the improved method of form
`ing circuit structures having Smaller linewidths of the instant
`invention, it is believed that it would be helpful in under
`Standing the principles of the present invention and to Serve
`as a background by first explaining the conventional litho
`graphic process used on a Standard resist having a thickness
`of about 5000 A for forming a gate conductor with reference
`to FIGS. 1(a) through 1(d). Further, the problem associated
`when the conventional lithographic proceSS is applied to an
`ultra-thin resist thickness of less than 2500 A will also be
`explained in connection with FIGS. 2(a) through 2(d).
`In FIG. 1(a), there is shown a portion 10 of a semicon
`ductor device being fabricated on a Semiconductor wafer.
`The portion 10 includes a semiconductor wafer stack or film
`Stack 12 formed of a Substrate 14 and a gate conductive layer
`or film 16. A resist layer 18 is deposited on top of the gate
`conductive layer 16. Typically, the gate conductive layer 16
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`3
`is a layer of polycrystalline silicon having a thickness
`between 500 A to 5000 A. The resist layer has a thickness
`of approximately 5000 A in the current art.
`In FIG. 1(b), the resist layer 18 is patterned to an initial
`resist mask 20 which has an initial linewidth 22. The initial
`linewidth 22 is assumed to be the Smallest dimension
`obtained by image transfer from the resist layer in the
`lithographic equipment. Since it is desired to define and
`control the gate linewidth to be smaller than this initial
`linewidth 22, a trim etch process is used So as to further
`reduce the initial linewidth 22 to match the desired gate line
`width.
`For example, a typical deep-UV Stepper can produce a
`reliable resolution capability down to approximately 0.25
`tim. In order to decrease the gate line width to be less than
`0.25 lum, the initial linewidth 22 is controllably etched until
`the desired gate line width is achieved. The trim etch proceSS
`includes isotopically etching away a portion (the area out
`side of the dotted line 24) of the resist mask 20 so as to
`reduce Simultaneously the thickness with the lateral dimen
`sion until a final resist mask 26 is obtained. This is depicted
`in FIG. 1(c) in which a final linewidth 28 is produced
`corresponding to approximately the desired gate line width.
`In FIG. 1(d), there is shown a gate conductive etching
`proceSS in which exposed portions of the gate conductive
`layer 16 are etched away. The gate conductive etching
`proceSS includes an anisotropical etching process with the
`resist as an etchmask So as to remove the exposed portions
`of the conductive layer 16 and is stopped on the Substrate 14.
`AS a result, after the isotropic etch and the removal of the
`final resist mask 26, a gate 30 is formed which has a width
`32 substantially equal to the final linewidth 28 of the resist.
`However, when the lithographic process described above
`in FIGS. 1(a)-1(d) is applied to an UTR thickness of less
`than 2500 A, there is created a Significant problem in the
`gate conductor etching process Since an excessive amount of
`resist will have been consumed during the trim process Step.
`As can be seen in FIG. 2(a), an UTR layer 18a has a
`thickness of less than 2500 A as compared to the thicker
`resist layer 18 of FIG. 1(a). In FIG.2(b), the UTR layer 18a
`is patterned to an initial resist mask 20a which has an initial
`linewidth 22a. It will be noted that the initial resist mask 20a
`has a thickneSS which is Substantially less than the resist
`mask 20 of FIG. 1(b).
`Thus, during the isotropic etching (trim process) of the
`UTR layer 18a in FIG. 2(b) so as to reduce the initial
`linewidth, an excessive amount of the resist will be con
`Sumed leaving a Smaller final resist mask 26a in FIG. 2(c)
`as compared to the resist mask 26 of FIG. 1(c). As a result,
`during the isotropic etch of the gate conductor layer 16a an
`undesired consumption of the same will occur leaving only
`a small gate 30a in FIG. 2(d) as compared to the gate 30 of
`FIG. 1(d).
`In order to solve this problem, the inventors of the present
`invention have developed an improved method of forming
`gates having linewidths which are Smaller than what is
`achievable by conventional UV lithographic techniques on
`ultra-thin resist layers. The present invention will now be
`described with respect to the process flow of FIG. 3 and the
`cross-sectional views of FIGS. 4(a)-4(f).
`In FIG. 4(a), there is shown a portion 110 of a semicon
`ductor device being fabricated on a Semiconductor wafer.
`The portion 110 includes a semiconductor wafer stack or
`film stack 112 formed of a substrate 114 and a gate conduc
`tive layer or device layer (film) 116. A hardmask layer 118
`is deposited on top of the gate conductive layer or device
`layer 116 in accordance with step 302 of FIG. 3.
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`US 6,420,097 B1
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`4
`In FIG. 4(b), an UTR layer 120 is deposited on top of the
`hardmask layer 118 in accordance with the step 304 of FIG.
`3. The gate conductive layer 116 is a layer of polycrystalline
`silicon having a thickness between 500 A to 5000 A. The
`materials for forming the hardmask layer 118 may be
`inorganic films Such as Silicon dioxide, Silicon nitride,
`Silicon oxynitride, and titanium nitride or organic films Such
`as a bottom anti-reflective coating (BARC). The BARC is
`typically a water Soluble fluoropolymer, Such as Shipley
`AR19 which is commercially available from Shipley Cor
`poration of Sunnyvale, Calif. The hardmask layer 118 has a
`thickness between 50 A and 500 A. The UTR layer 120 has
`a thickness of less than 2500 A.
`In FIG. 4(c), the UTR layer 120 is patterned to a resist
`mask 122 which has an initial linewidth 124. This corre
`sponds to step 306 in FIG. 3. This initial linewidth is
`assumed to be the Smallest dimension obtained by image
`transfer from the UTR layer in the lithographic equipment.
`In FIG. 4(d), corresponding to step 308 of FIG. 3, a
`hardmask trim etch proceSS is performed which includes
`isotopically over-etching away exposed portions of the
`hardmask layer 118 as well as portions underneath the resist
`mask 122 So as to produce a hardmask 126. The hardmask
`126 has a final linewidth 128 which is Smaller than the initial
`linewidth 124 of the resist mask 122 and corresponds
`approximately to the desired gate or Structure line width. By
`leaving the resist mask 122 during the hardmask trim, there
`is prevented the loss of material from the top of the hard
`mask 126.
`In FIG. 4(e), the resist mask 122 is optionally removed.
`This corresponds to step 310 of FIG. 3. In FIG. 4(f), there is
`shown a gate conductive etching proceSS in which exposed
`portions of the gate conductive layer or device layer 116 are
`etched away. The gate conductive etching proceSS includes
`an anisotropic etching proceSS which removes exposed
`portions of the conductive layer 116 and is stopped on the
`Substrate 114. As a result, after the anisotropic etching a
`structure or gate 130 is formed which has a width 132
`substantially equal to the hardmask final linewidth 128.
`Thus, the gate linewidth 132 is significantly smaller than
`what can be achieved by conventional UV lithographic
`equipment alone.
`There are many modifications and variations which could
`be made to the present method while retaining the use of a
`hardmask So as to improve integration characteristics. For
`example, Several modifications to the resist layer may
`include (1) a silylating resist layer could be used for improv
`ing Selectivity to the hardmask layer, (2) the resist layer may
`be exposed to a UV bake before the hardmasketch so as to
`enhance Selectivity to the hardmask layer, or (3) the resist
`layer could be cured by an electron beam before the hard
`masketch in order to enhance Selectivity to the hardmask
`layer. Electron beam and UV curing has the effect of
`breaking weak bonds in the polymer which will increase the
`etch resistance of the resist layer during the etching Step.
`Such curing would be performed between the Step of image
`transfer to the resist layer and the Step of etching of the
`hardmask/conductive layer.
`Further, variations to the hardmask layer could include (1)
`an organic or inorganic material may be used which mini
`mizes reflection of the incident radiation during patterning
`of the resist layer, Such as a bottom anti-reflective coating
`(BARC), (2) a composite (multi-layer) material may be used
`to absorb the incident radiation, or (3) a multi-layer material
`may be used consisting of a top anti-reflective layer Such as
`a nitride film and a bottom etchstop layer Such as an oxide
`film. In addition, modifications to the hardmasketch process
`
`

`

`US 6,420,097 B1
`
`S
`may include a two-step process where (a) an anisotropic etch
`is performed initially So as to remove the exposed portions
`of the hardmask and (b) an isotropic etch is performed
`Subsequently So as to reduce the lateral dimension of the
`hardmask underneath the resist mask. Moreover, the trim
`process could be provided into two parts: (a) isotropic
`etching is performed on the resist layer, and (b) etch and trim
`of the hardmask is then performed thereafter.
`From the foregoing detailed description, it can thus be
`Seen that the present invention provides an improved method
`of forming circuit structures having linewidths which are
`smaller than what is achievable by conventional UV litho
`graphic techniques on ultra-thin resist layers. The method
`utilizes a hardmask which is patterned using a resist layer
`and is then trimmed to reduce the width of the hardmask
`layer before etching the underlying gate conductive layer.
`While there has been illustrated and described what is at
`present considered to be a preferred embodiment of the
`present invention, it will be understood by those skilled in
`the art that various changes and modifications may be made,
`and equivalents may be Substituted for elements thereof
`without departing from the true Scope of the invention. In
`addition, many modifications may be made to adapt a
`particular situation or material to the teachings of the
`invention without departing from the central Scope thereof.
`Therefore, it is intended that this invention not be limited to
`the particular embodiment disclosed as the best mode con
`templated for carrying out the invention, but that the inven
`tion will include all embodiments falling within the scope of
`the appended claims.
`What is claimed is:
`1. A method of forming circuit Structures having lin
`ewidths which are smaller than what is achievable by
`conventional UV lithographic techniqueS on ultra-thin resist
`layers, Said method comprising the Steps of:
`providing a Semiconductor wafer Stack formed of a Sub
`Strate and a device layer above the Substrate;
`depositing a hardmask layer over the device layer;
`depositing an ultra-thin resist layer over the hardmask
`layer;
`forming a resist mask having an initial linewidth;
`anisotropically etching exposed portions of the hardmask
`layer;
`isotropically etching Subsequently the hardmask layer
`underneath the resist mask to form a hardmask having
`a final linewidth which is narrower than the initial line
`width of the resist mask and corresponds to a desired
`Structure linewidth; and
`anisotropically etching the device layer as defined by the
`hardmask to form a structure having a width Substan
`tially equal to the final linewidth of the hardmask.
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`2. A method of forming circuit Structures as claimed in
`claim 1, wherein the device layer is formed of Silicon.
`3. A method of forming circuit structures as claimed in
`claim 2, wherein the silicon has a thickness between 500 A
`to 5000 A.
`4. A method of forming circuit Structures as claimed in
`claim 1, wherein the ultra-thin resist layer has a thickness of
`less than 2500 A.
`5. A method of forming circuit Structures as claimed in
`claim 4, wherein the hardmask is made of an inorganic
`material.
`6. A method of forming circuit Structures as claimed in
`claim 5, wherein the inorganic material is one of Silicon
`dioxide, Silicon nitride, Silicon oxynitride, and titanium
`nitride.
`7. A method of forming circuit Structures as claimed in
`claim 4, wherein the hardmask material is made of an
`organic material.
`8. A method of forming circuit Structures as claimed in
`claim 7, wherein the organic material is a bottom anti
`reflective coating.
`9. A method of forming circuit Structures as claimed in
`claim 4, wherein the hardmask layer has a thickness between
`50 A to 500 A.
`10. A method of forming circuit structures as claimed in
`claim 1, further comprising the Step of exposing the resist
`layer to a UV bake prior to the Step of isotropic over-etching
`So as to enhance Selectivity to the hardmask layer.
`11. A method of forming circuit structures as claimed in
`claim 1, further comprising the Step of curing the resist layer
`by an electron beam prior to the Step of isotropic over
`etching So as to enhance Selectivity to the hardmask layer.
`12. A method of forming circuit structures as claimed in
`claim 1, wherein the hardmask layer is formed of a multi
`layer material.
`13. A method of forming circuit structures as claimed in
`claim 12, wherein the multi-layer material consists of a top
`anti-reflective layer and a bottom etchstop layer.
`14. A method of forming circuit structures as claimed in
`claim 13, wherein the top anti-reflective layer is formed of
`a nitride film.
`15. A method of forming circuit structures as claimed in
`claim 14, wherein the bottom etchstop layer is formed of an
`oxide film.
`16. A method of forming circuit structures as claimed in
`claim 1, wherein the resist mask used in the isotropic etching
`Step is removed prior to the anisotropic etching Step of the
`device layer.
`17. A method of forming circuit structures as claimed in
`claim 1, wherein the resist mask used in the isotropic etching
`Step is maintained on top of the hardmask during the
`anisotropic etching Step of the device layer.
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`k
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`k
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`k
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`k
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`k
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