`
`Case 6:20-cv-00636-ADA Document 1-4 Filed 07/14/20 Page 1 of 8Case 6:20-cv-00636-ADA Document 198-3 Filed 08/10/22 Page 1 of 8
`
`
`
`
`Exhibit 4
`
`
`
`
`
`
`
`
`

`

`V o l u m e 6 , I s s u e 2 , 2 0 0 8
`Case 6:20-cv-00636-ADA Document 1-4 Filed 07/14/20 Page 2 of 8Case 6:20-cv-00636-ADA Document 198-3 Filed 08/10/22 Page 2 of 8
`
`
`Serving
`Serving
`Semiconductor
`Semiconductor
`Manufacturers
`Manufacturers
`Worldwide With
`Worldwide With
`Enabling Process
`Enabling Process
`Technology
`Technology
`
`In This Issue:
`• Aerial Imaging,
`the Ultimate
`Defect Classifier
`• New Cleaning
`Technology
`for Advanced
`Photomasks
`• APC for
`32nm Double
`Patterning
`• Gridded
`Design Rules
`for Continued
`CMOS Scaling
`
`Through-Silicon
`Via Technology —
`Challenges and Solutions
`
`

`

`
`
`Case 6:20-cv-00636-ADA Document 1-4 Filed 07/14/20 Page 3 of 8Case 6:20-cv-00636-ADA Document 198-3 Filed 08/10/22 Page 3 of 8
`
`Publisher: Betty Newboe
`Email: Betty_X_Newboe@amat.com
`
`Chief Editor: Connie Duncan
`Email: Connie_Duncan@amat.com
`
`Editor: Richard Lewington
`Email: Richard_Lewington@amat.com
`
`Assistant Editor: Priya Gopalakrishnan
`
`Advisory Board: Rudi Hendel, Ph.D.,
`David Kyser, Ph.D., Omkaram Nalamasu, Ph.D.,
`Reza Arghavani, Ph.D.
`
`Nanochip Technology Journal is published
`by Applied Materials, Inc. in cooperation with
`United Business Media LLC © Copyright Applied
`Materials, Inc. 2008, for external use.
`
`Cover Art: Elements Group
`
`All trademarks so designated or otherwise
`indicated as product names or services are
`trademarks of Applied Materials, Inc. in the U.S.
`and other countries. All other product and service
`marks contained herein are trademarks of their
`respective owners.
`
`Front Cover: The industry is moving to 3-D
`packaging using through-silicon vias. Deep
`Reactive Ion Etch (DRIE) is the preferred
`technology for this etch application.
`
`To receive extra copies of the Nanochip
`Technology Journal or to add colleagues
`to the mailing list, please email the
`following information to:
`technical_public_relations@amat.com
`
`
`
` • Name
`• Title
`• Company
`• Business address
`
`A Message from
`Ken MacWilliams
`Vice President and General Manager of
`Applied Materials' Maydan Technology
`Center
`
`One of the most exciting developments taking place in the IC industry is the work
`being done on through-silicon via (TSV) technology, an emerging solution for inter-
`connecting 3-D chip stacks. This new approach promises better device performance,
`lower power consumption, reduced costs and the integration of heterogeneous devices.
`In this issue, we highlight the challenges and progress being made in TSV formation
`with an exclusive article featuring the viewpoints of some of Applied’s leading tech-
`nologists in this area.
`
`Applied is working on several different TSV approaches at its Maydan Technology
`Center (MTC), where we are focusing on unit process robustness, cost-effectiveness
`and integration. This effort leverages Applied’s broad range of process technologies and
`extends to several joint TSV projects with key industry partners and suppliers. Being
`able to use the MTC to leverage the broad range of Applied's process technologies,
`platforms and expertise gives us broader insight into overall manufacturability and the
`capability to deliver optimized and differentiated solutions.
`
`Our research at the MTC on TSV etch processes is featured in an article that reviews
`both via-first and via-last applications. Since each of these have very different process
`requirements, the etch reactor must be flexible enough to handle both approaches.
`We introduce a new hardware and process scheme that provides excellent sidewall
`roughness without any trade-off in silicon etch rate.
`
`Much of the other research discussed in this issue has also been conducted at the
`MTC, including the development of a new tantalum barrier process that addresses low
`k dielectric damage issues in advanced dual damascene interconnect structures and a
`demonstration of the use of integrated metrology to improve CD control in double
`patterning wafers.
`
`Representing groundbreaking work in inspection technology, an article from our
`engineering team in Israel demonstrates that aerial imaging detection technology is the
`ultimate classifer between printing and non-printing defects, since it allows a very high
`detection rate without nuisance effects. This property can enable a simple migration
`from the 65nm node to beyond 32nm by tuning the detection limit.
`
`In addition, we are pleased to present an article from Dr. Michael Smayling – an alum
`of Applied’s MTC and now of Tela Innovations – on one-dimensional gridded design
`rules (GDR). This approach has been shown to have a number of advantages over two
`dimensional cells, including smaller area, better gate CD control and the elimination
`of hotspots. The MTC scientists have also demonstrated 22nm logic cells with Tela by
`leveraging the emerging Self-Aligned Double Patterning process scheme at this year’s
`SPIE. Dr. Smayling predicts that 1-D GDR cells will enable continued simple scaling
`of CMOS logic to the 16nm node and beyond.
`
`I hope that you enjoy this issue of the Nanochip Technology Journal and find the
`articles interesting and informative. Please feel free to contact me or the authors if you
`have any questions. We appreciate your comments and feedback.
`
`www.appliedmaterials.com
`
`Ken MacWilliams
`
`

`

`
`
`Case 6:20-cv-00636-ADA Document 1-4 Filed 07/14/20 Page 4 of 8Case 6:20-cv-00636-ADA Document 198-3 Filed 08/10/22 Page 4 of 8
`
`Volume 6, Issue 2, 2008
`
`c o n t e n t s
`
`Special Focus: TSV
`
`14 Through-Silicon Via Technologies — Challenges and Solutions
`
`19 Deep Silicon Etch for TSV Increases Performance and Productivity
`
`
`2
`
`
`
`8
`
`
`
`Closed-Loop CD Control for
`SADP Scheme
`Integrated metrology improves wafer-to-wafer CD
`control and minimizes double patterning overlay
`errors.
`
`33 Gridded Design Rules – 1-D Design
`Enables Scaling of CMOS Logic
`Benefits of 1-D include smaller area requirement,
`better gate CD control, and elimination of
`hotspots.
`
`
`
`Photomask Cleaning for 45nm and
`Beyond
`Photoresist stripping without using haze-promoting
`sulfuric acid-based chemistries extends mask lifetime.
`
`38
`
`
`
`Innovative Endpoint Technology
`Optimizes CMP Process Control
`In situ film thickness monitoring optimizes
`manufacturing yield and device performance.
`
`23 Virtual Metrology Improves Thermal
`Uniformity for Critical Anneals
`Innovative approach can significantly reduce
`wafer processing errors, enhance yield and minimize
`production costs.
`
`
`
`28 Aerial Imaging – the Optimal Classifier
`of Photomask Defect Printability
`Breakthrough inspection technique filters out nuisance
`non-printing defects, allowing “true” defect detection.
`
`42 Novel Approach Extends PVD Ta
`
`Barrier Technology to 32nm and Below
`
`New process preserves delicate low k trench
`integrity, demonstrates excellent electrical and
`reliability performance.
`
`
`46 Reducing Low k Damage with CO 2
`Plasma Etch
`CO2 plasma has the potential to replace O2 plasma
`for the ashing process.
`
`
`
`
`
`Nanochip Technolog y Jour nal
`
`Issue Two 2008
`
`1
`
`

`

`
`
`Case 6:20-cv-00636-ADA Document 1-4 Filed 07/14/20 Page 5 of 8Case 6:20-cv-00636-ADA Document 198-3 Filed 08/10/22 Page 5 of 8
`
`P V D
`
`Novel Approach
`Extends PVD Ta
`Barrier Technology to 32nm
`and Below
`
`A new PVD tantalum (Ta) barrier process has
`been developed for 32nm and below copper/
`low k dual damascene interconnect structures.
`The novel process preserves the delicate low k
`trench integrity, while demonstrating excellent
`stability, manufacturability, electrical and reli-
`ability performance.
`
`Keywords: Ta, PVD, Barrier Process
`
`The punch-through process involves the
`removal of barrier material from the via
`bottom during the etch/re-sputter step,
`
`intentionally gouging into the underly-
`ing copper (Cu) line. This process has
`been widely used in Cu back-end-of-
`line (BEOL) 65nm production because
`it produces high performance devices
`with superior reliability, [1-5] especially
`compared to non-punch-through pro-
`cesses. [6] However, the conventional
`punch-through process can cause physi-
`cal damage to porous low k dielectrics,
`leading to reliability implications such as
`roughening of the trench bottom in dual
`damascene structures or microtrenching
`in the bottom of single trenches.
`
`Target
`
`Ar+
`
`Ta coil
`
`Ta
`
`Ta
`
`Ar+
`
`Ta
`
`Wafer
`
`Trench bottom
`Wafer bias
`
`Punchthrough
`
`Via bottom
`
`Figure 1. Diagram represents the new selective re-sputtering reactor and process. Increasing
`DC power on the Ta coil generates more off-angular neutral flux.
`
`42
`
`Issue Two 2008
`
`Nanochip Technolog y Jour nal
`
`This article reports on the use of off-
`angular Ta neutral f lux during the re-
`sputter process to improve the selectivity
`between the via and trench bottom. This
`protects the trench bottom and via bevel,
`while still allowing suff icient gouging
`into the underlying Cu line. In addition,
`the plasma density and ion energy are
`adjusted to further optimize selectivity
`and avoid micro-trenching. The result is
`a high deposit/etch selectivity PVD pro-
`cess, validated using TEM and electrical
`test results. This approach has extended
`the PVD Ta barrier process to at least
`the 32nm node.
`
`Experimental Work
`The structures used in this study were
`etched in a low k dielectric (k≈2.7) film.
`The structures contained dual dama-
`scene via chains and single trench lines
`with an approximate 2:1 aspect ratio.
`The structures were deposited with a
`TaN/Ta bilayer initially, followed by
`Ar+ sputtering on the bilayer and a final
`barrier layer deposition step. The PVD
`reactor used was able to achieve high-
`ionization deposition and in situ Ar+
`sputtering capability. The step coverage
`performance was evaluated using TEM
`cross-section images and reliability was
`evaluated using electrical test wafers.
`
`Results and Discussion
`Selectivity depends on the difference in
`aspect ratio between trenches and vias.
`
`

`

`
`
`Case 6:20-cv-00636-ADA Document 1-4 Filed 07/14/20 Page 6 of 8Case 6:20-cv-00636-ADA Document 198-3 Filed 08/10/22 Page 6 of 8
`
`■ PVD Barriers for 32nm
`
`High coil voltage (700V)
`Electron Density
`5E+11
`3.8E+11
`2.8E+11
`2.2E+11
`1.6E+11
`1.2E+11
`9.4E+10
`7.1E+10
`5.3E+10
`4.0E+10
`3.1E+10
`2.3E+10
`1.7E+10
`1.3E+10
`1E+10
`
`Plasma Density
`
`25
`
`20
`
`15
`
`10
`
`5 0
`
`Low coil voltage (200V)
`Electron Density
`5E+11
`3.8E+11
`2.8E+11
`2.2E+11
`1.6E+11
`1.2E+11
`9.4E+10
`7.1E+10
`5.3E+10
`4.0E+10
`3.1E+10
`2.3E+10
`1.7E+10
`1.3E+10
`1E+10
`
`0
`
`10
`
`20
`R (cm)
`
`30
`
`0
`
`Plasma Potential
`
`10
`
`20
`R (cm)
`
`30
`
`Vp
`50.0
`42.8
`35.7
`28.6
`21.4
`14.3
`7.1
`
`0-
`
`7.1
`-14.3
`-21.4
`-28.6
`-35.7
`-42.8
`-50.0
`
`Vp = 39V
`
`25
`
`20
`
`15
`
`10
`
`5 0
`
`Vp
`50.0
`42.8
`35.7
`28.6
`21.4
`14.3
`7.1
`
`0-
`
`7.1
`-14.3
`-21.4
`-28.6
`-35.7
`-42.8
`-50.0
`
`Vp = 38V
`
`25
`
`20
`
`15
`
`10
`
`5 0
`
`25
`
`20
`
`15
`
`10
`
`5 0
`
`Z (cm)
`
`Z (cm)
`
`0
`
`10
`
`R (cm)
`
`20
`
`30
`
`0
`
`10
`
`20
`
`30
`
`R (cm)
`
`Figure 2. Simulation of plasma density and plasma potential vs. coil voltage shows minimal
`effect of increased Ta coil voltage on plasma potential.
`
`effect on the via bottom, while high neutral
`fraction leads to a higher Ta net deposition
`rate on the trench bottom compared to the
`
`via bottom. Low Ta+ ion fraction also leads
`to lower line resistance (Figure 3) and good
`device yield (Figure 4).
`
`+
`
`+
`
`+
`
`+
`
`160
`
`140
`
`120
`
`100
`
`Line Resistance
`
`80
`Conventional
`
`High Source
`DC Power
`
`Low Source DC Power
`High Ta Coil DC Power
`
`Figure 3. Electrical results for different etch regimes show that low Ta+ ion fraction during
`the re-sputtering process reduces line resistance.
`
`During the deposition step, source DC
`power applied to the target and AC bias
`power applied to the pedestal were opti-
`mized to maximize the selectivity.
`
`Increasing the DC source power while
`keeping the AC bias power low increases
`the non-directional neutral f lux and min-
`imizes the directionality of the ion f lux
`at the wafer. This leads to higher bottom
`coverage in the trenches than in the vias
`and improves the deposition selectivity.
`High re-sputtering selectivity is more
`difficult to achieve since Ar+ ions arriv-
`ing normal to the substrate will affect the
`bottom of the trenches and vias equally,
`regardless of aspect ratio. Lower wafer
`bias power reduces Ar+ ion energy which
`allows re-sputtering of the via bottom,
`but with reduced bevel damage.
`
`Increasing the DC power on the Ta coil
`attached on the side of the reactor can
`generate more off-angular neutral f lux,
`as shown in Figure 1. The off-angular Ta
`neutral deposition protects the bevel area
`and enhances trench bottom coverage
`during the re-sputter etch step. The coil
`voltage will also increase proportionally,
`but, according to plasma simulations, this
`has no deleterious effect on the process
`(Figure 2). The DC coil power is the key
`parameter to increase the re-sputtering
`selectivity.
`
`During the re-sputtering process, the
`DC source power must be optim ized
`to maintain a stable plasma and to keep
`the Ta+ ion fraction as low as possible to
`minimize via bottom deposition. Plasma
`stability is also assisted by increasing the
`pressure in the reactor, which raises the
`plasma density and allows a lower coil
`voltage to be used.
`
`We define the net deposition rate during
`the sputtering step as the rate of Ta neutral/
`ion deposition minus the absolute rate of
`Ar/Ta ions sputtering away. This is always
`a minus number. Low Ta+ ion fraction dur-
`ing sputtering minimizes the net deposition
`
`
`
`Nanochip Technolog y Jour nal
`
`Issue Two 2008
`
`43
`
`

`

`
`
`Case 6:20-cv-00636-ADA Document 1-4 Filed 07/14/20 Page 7 of 8Case 6:20-cv-00636-ADA Document 198-3 Filed 08/10/22 Page 7 of 8
`
`■ PVD Barriers for 32nm
`
`Real Etch Rate (Å/s)
`
`9.00
`
`8.50
`
`8.00
`
`7.50
`
`7.00
`
`6.50
`
`Vbias
`Real Etch Rate
`
`160
`
`140
`
`120
`
`100
`
`80
`
`60
`
`Voltage (V)
`
`Low Source DC/High Coil
`DC power etch
`
`Conventional
`Etch
`High DC Etch
`
`1
`
`50
`
`100
`Line Resistance
`
`150
`
`200
`
`40
`500
`
`1000
`
`2000
`1500
`RF Power (W)
`
`2500
`
`6.00
`3000
`
`99.9
`
`99
`95
`90
`80
`70
`50
`30
`20
`10
`
`52
`
`.5
`.1
`
`Percent
`
`Figure 4. Electrical results show that low Ta+ ion frac-
`tion during the re-sputtering process produces good
`device yield.
`
`
`Figure 5. RF power vs. wafer bias voltage (proportional to ion energy) and real
`etch rate.
`
`With higher DC coil power, more off-
`angular Ta f lux from the coil strikes the
`wafer, possibly increasing overhang for-
`mation. Therefore, both target DC power
`and coil DC power need to be optimized
`for proper trade-off between overhang
`and selectivity. Increasing the RF coil
`power improves the plasma stability and
`decreases the re-sputtering energ y, as
`shown in Figure 5. Proper adjustment of
`the RF coil power and AC bias power can
`keep the re-sputter/deposition ratio close
`to 1 (net deposition rate during sputter-
`ing is close to 0), thereby maximizing the
`re-sputtering selectivity. Also, increasing
`Ar f low improves plasma stability and
`lowers the coil DC voltage, which is ben-
`eficial for hardware stability.
`
`In Fig ure 6, TEM i m ages f rom our
`st udy show that the dua l damascene
`bevel/trench bottom is damage-f ree
`with suff icient Cu gouging depth into
`the via after re-sputtering. In addition,
`there is no microtrenching in the single
`trench bottom and excellent center-to-
`edge uniformity is achieved, as seen in
`Figure 7.
`
`This new PVD tantalum barrier pro-
`cess has shown good manufacturability
`during an extended run (>1,900kWh),
`achieving good process stability and good
`defect performance.
`
`Figure 6. TEM cross-section of a dual damascene via with low k dielectric showing (left)
`trench bottom damage using the conventional process, while (right) the new selective etch
`preserves the trench bottom intact.
`
`Figure 7. TEM cross-section of a trench on low k dielectric showing no micro-trenching
`damage in the bottom and excellent center-to-edge uniformity.
`
`44
`
`Issue Two 2008
`
`Nanochip Technolog y Jour nal
`
`

`

`
`
`Case 6:20-cv-00636-ADA Document 1-4 Filed 07/14/20 Page 8 of 8Case 6:20-cv-00636-ADA Document 198-3 Filed 08/10/22 Page 8 of 8
`
`■ PVD Barriers for 32nm
`
`Conclusion
`A new Ta barrier process has been devel-
`oped to address low k dielectric damage
`issues in advanced dual damascene inter-
`connect structures. As well as preserving
`the delicate low k trench integrity, the
`process demonstrates excellent electrical
`and reliability performance. This approach
`has extended the PVD Ta barrier process
`to at least the 32nm node. ■
`
`Acknowledgments
`The authors would like to thank Applied’s
`Philip Wang for TEM support and Tza-
`Jing Gung for technical and management
`support. This work has been supported by
`Applied’s Maydan Technology Center.
`
`Authors
`
`Hsien-Lung Yang is a senior process
`e n g i n e e r w i t h A p p l i e d ’s Cu Ba r r i e r/
`Seed division, responsible for product
`development on the Endura system.
`He received his M.S. in electrical and
`co m p u te r e n g i n e e r i n g f ro m Co r n e l l
`University.
`
`Fuhong Zhang is a process engineer
`with Applied’s Silicon Systems Group,
`responsible for process development
`and improvement of metal deposition.
`He received his Ph.D. and M.S. degrees
`from Purdue University.
`
`Jennifer Tseng is a program manager
`w i t h A p p l i e d ’s M a y d a n Te c h n o l o g y
`Ce n te r B EO L i n te g ra t i o n g ro u p. S h e
`received her master’s degree from Utah
`State University and her B.S. degree
`from National Taiwan University.
`
`John Forster is a distinguished member
`of technical staff in the Metal Deposition
`Products (MDP) unit, specializing in
`R F/p l a s m a p r o c e s s i n g . H e h o l d s a
`Ph.D. in electrical engineering from
`Rensselaer Polytechnic Institute.
`
`A r v i n d S u n d a r ra j a n h e a d s PV D C u
`barrier seed process development in
`Applied’s MDP unit. He has a Ph.D. in
`materials science from MIT and a B.Tech.
`
`References
`[1] H. Yang et al., ”Off Angular Deposition
`Compensation for PVD Selective Re-Sputtering
`Process,” Materials Research Society
`Conference Proceedings, Volume1079E-N03-05,
`2008.
`
`[2] K. Ino et al., “Ion energy, ion flux, and ion spe -
`cies effects on crystallographic and electrical
`properties of sputter-deposited Ta thin films,”
`Journal of Vacuum Science & Technology A
`15(5), 2627, 1997.
`
`[3] P. Catania et al., “Low resistivity body-centered
`cubic tantalum thin films as diffusion barriers
`between copper and silicon,” Journal of Vacuum
`Science & Technology A 10, 3318, 1992.
`
`[4] C.-C Yang et al. Extendibility of PVD Barrier
`Seed for BEOL Cu Metallization,” Proceedings of
`the IEEE International Interconnect Technical
`Conference, p.135, 2005.
`
`[5] D. Edelstein et al. “ A High performance liner for
`Copper damascene interconnects,” Proceedings
`International Interconnect Technical
`Conference. p.9, 2001.
`
`[6] N. Kumar et al, “Improvement in Parametric
`and Reliability Performance of 90nm Dual-
`damascene Interconnects Using Ar+ Punch-
`Thru PVD Ta(N) Barrier Process,” Advanced
`Metallization Conf. 2004, p.247.
`
`in metallurgical engineering from IIT
`Bombay, India.
`
`Ajay Bhatnagar is a global product
`m a n a g e r w i t h A p p l i e d ’s D i e l e c t r i c
`Gapfill division. He was previously the
`GPM for the PVD division. He received
`his M.S. and Ph.D. degrees in materials
`science and engineering from Stanford
`University.
`
`Niranjan Kumar is a global product mar-
`ket i n g m a n a g e r w i t h A p p l i e d ’s M D P
`unit. He received his B.Tech. in electrical
`engineering from IIT Kanpur, India and a
`certificate degree in electrical engineer-
`ing from Stanford University.
`
`Prabu Gopalraja is the general manager
`of the MDP unit at Applied Materials. He
`has a Ph.D. in plasma physics.
`
`I n M e m o r i a m : The late Kim Nelson
`worked as a process engineer with the
`MDP productivity enhancement team
`responsible for the products on the
`Endura2 platform. She received her
`M.S. in materials science from Stanford
`University.
`
`Article Contact:
`Hsien-Lung_Yang@amat.com
`
`Process System
`Used in Study
`
`Applied Endura®
`CuBS PVD
`
`• PVD deposition of Ta(N)
`barrier and Cu seed
`
`• Ultra-thin and conformal barri-
`ers enable low line resistance
`with robust SM/EM performance
`
`• Robust integration with low k
`dielectrics
`
`• Aktiv Preclean delivers
`efficient removal of residue
`and CuO while minimizing
`ILD k value change
`
`(Republished from the Proceedings of the Materials Research Society, 2008 Spring Conference, Vol.1079E-N03-05)
`
`
`
`Nanochip Technolog y Jour nal
`
`Issue Two 2008
`
`45
`
`