`
`Exhibit ZTE-CC-C
`Samsung Case Preliminary Constructions
`
`
`
`
`
`Case 2:15-cv-00225-JRG-RSP Document 60-3 Filed 09/28/15 Page 2 of 3 PageID #: 1000
`
`U.S. Patent Nos. 5,812,789; 6,058,459; 6,427,19; 7,321,368; 7,542,045 ; 7,777,753 ; 8,054,315; 8,681,164
`& 5,960,464
`Parthenon Unified Memory Architecture, LLC v. Samsung Elecs. Co., Ltd. et al. , Case No. 2: 14-cv-902-
`JRG-RSP
`
`disputed term
`
`preliminary construction
`
`"bus"
`
`"memory bus"
`
`" real time"
`
`"fast bus"
`
`"a signal line or a set of associated signal
`lines to which a number of devices are
`coupled and over which information may be
`transferred between them"
`
`"bus [as construed] that is coupled with a
`memory"
`
`"fast enough to keep up with an input data
`stream"
`
`[agreed?]
`
`"arbiter" I "arbitration circuit" I "memory
`arbiter" I "arbiter circuit"
`
`"circuitry that uses a priority scheme to
`determine which requesting device will gain
`access"
`
`"control circuit"
`
`plain and ordinary meaning, no further
`construction necessary
`
`"directly supplied" I "directly supplies"
`
`"supplie[d, s] without being stored in [main,
`system] memory for purposes of decoding
`subsequent images"
`
`"monolithically integrated into" I
`"integrated into"
`
`"formed within"
`
`" [first, second, third] onboard memory" I
`" [first, second, third] onboard memories"
`
`" [first, second, third] memor[y, ies] within
`the decoder"
`
`
`
`Case 2:15-cv-00225-JRG-RSP Document 60-3 Filed 09/28/15 Page 3 of 3 PageID #: 1001
`
`U.S. Patent Nos. 5,812, 789; 6,058,459; 6,427, 19; 7,321 ,368; 7,542,045; 7, 777,753 ; 8,054,315; 8,681 , 164
`& 5,960,464
`Parthenon Unified Memory Architecture, LLC v. Samsung Elecs. Co., Ltd. et al., Case No. 2: 14-cv-902-
`JRG-RSP
`
`disputed term
`
`preliminary construction
`
`"contiguous" I "noncontiguous"
`
`plain and ordinary meaning
`
`"coupled" I "coupleable" I "coupling"
`
`"directly or indirectly connected"
`
`"directly or indirectly connectable"
`
`"directly or indirectly connecting"