(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2012/0152604 A1
`Ahn et al.
`(43) Pub. Date:
`Jun. 21, 2012
`
`US 20l20l52604Al
`
`(54) MOUNTING STRUCTURE OF CIRCUIT
`BOARD HAVING THEREON
`
`(30)
`
`Foreign Application Priority Data
`
`NIULTLLAYERED CERAMIC CAPACITOR,
`
`Dec. 21, 2010
`
`(KR) ...................... .. 10-2010-0131716
`Classification
`
`51
`
`(
`
`I t Cl
`
`)
`
`(2006 01)
`/18
`(2006.01)
`H05K 3/00
`(2006.01)
`H01G 4/30
`(52) U.S. Cl. ....................... .. 174/260; 361/301.4; 29/829
`
`CIRCUIT BOARD FOR THE SAME, PACKING
`UNIT FOR MULTI—LAYERED CERAMIC
`CAPACITOR TAPED HORIZONTALLY AND
`ALIGNING METHOD THEREOF
`
`(75)
`
`Inventors:
`
`Young Ghyu Ahn, Gyeonggi-do
`(KR); Byoung Hwa Lee,
`Gyeonggi-do (KR); Min Cheol
`Park, Gyeonggi-do (KR); Sang Soo
`Park, Gyeonggi-do (KR); Dong
`Seok Park, Seoul (KR)
`
`(73) Assigneez
`
`SAMSUNG
`
`LTD" Suwon (KR)
`
`(21) App]. No‘;
`
`13/331,619
`
`(22)
`
`Filed:
`
`Dec. 20, 2011
`
`(57)
`
`ABSTRACT
`
`The present invention provides a method of mounting a cir-
`cuit board having thereon a multi-layered ceramic capacitor
`and a land pattern of a circuit board for the same. The method
`of mounting a circuit board having thereon a multi-layered
`ceramic capacitor on which a plurality of dielectric sheet
`having internal electrodes formed thereon are stacked and the
`external terminal electrodes connected to the internal elec-
`
`nal terminal electrodes in such a way that internal electrode
`layers of the multi-layered ceramic capacitor and the circuit
`board are arranged in a horizontal direction, wherein a height
`TS of conductive material to conductively connect the exter-
`nal terminal electrodes to the lands is less than 1/3 of a thick-
`ness TMLCC of the multi-layered ceramic capacitor.
`
`10'
`
`
`
`°°°°°‘
`
`Exhibit 1007
`
`Exhibit 1007
`PGR2017-00010
`PGR201 7-0001 0
`AVX CORPORATION
`AVX CORPORATION
`
`000001
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 1 of 9
`
`US 2012/0152604 A1
`
`[FIG. 1]
`
`14a
`
`20
`
`000002
`
`000002
`
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 2 of 9
`
`US 2012/0152604 A1
`
`[FIG. 2B]
`
`
`
`[FIG 3]
`
`000003
`
`000003
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 3 of 9
`
`US 2012/0152604 A1
`
`[FIG 4]
`
`000004
`
`000004
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 4 of 9
`
`US 2012/0152604 A1
`
`[FIG. 6]
`
`
`
`[FIG. 7]
`
`44
`
`45
`
` O
`
`000005
`
`000005
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 5 of 9
`
`US 2012/0152604 A1
`
`[FIG. 8]
`
`[FIG. 9A]
`
`07/, _/12
`
`[FIG. 9B]
`
`
`
`000006
`
`000006
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 6 of 9
`
`US 2012/0152604 A1
`
`
`
`[FIG. 10]
`
`
`
`000007
`
`000007
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 7 of 9
`
`US 2012/0152604 A1
`
`[F|G.11]
`
`
`
`[FIG. 12]
`
`000008
`
`000008
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 8 of 9
`
`US 2012/0152604 A1
`
`[FIG. ‘l3A]
`
`
`
`
`[F|G. 133]
`
`000009
`
`000009
`
`

`

`Patent Application Publication
`
`Jun. 21, 2012 Sheet 9 of 9
`
`US 2012/0152604 A1
`
`
`
`SumofAcousticNoise(dB)
`
`-D-Hot izontai mouwt ing
`i
`3 —-<>—veriica| mcuiting
`
`
`
`1/3
`
`Relative height of solder(Ts/Tim)
`
`
`
`—i:i—Hor izontal mount ing
`—<>—-verticai mounting
`
`35~
`
`[FIG. 15]
`
`40
`
`
`
`SumofAcousticNoise(dB)
`
`30
`
`20
`
`
`
`
`
`“BEN
`
`[E131
`
`E011
`
`[
`
`1
`
`000010
`
`000010
`
`

`

`US 2012/0152604 A1
`
`Jun. 21,2012
`
`MOUNTING STRUCTURE OF CIRCUIT
`BOARD HAVING THEREON
`MULTI-LAYERED CERAMIC CAPACITOR,
`METHOD THEREOF, LAND PATTERN OF
`CIRCUIT BOARD FOR THE SAME, PACKING
`UNIT FOR MULTI-LAYERED CERAMIC
`CAPACITOR TAPED HORIZONTALLY AND
`ALIGNING METHOD THEREOF
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] Claim and incorporate by reference domestic prior-
`ity application and foreign priority application as follows:
`
`CROSS REFERENCE TO RELATED
`APPLICATION
`
`[0002] This application claims the benefit under 35 U.S.C.
`Section 1 19 of Korean Patent Application Serial No.
`10-2010-0131716, entitled filed Dec. 21, 2010, which is
`hereby incorporated by reference in its entirety into this appli-
`cation.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`[0003]
`[0004] The present invention relates to a mounting struc-
`ture of a circuit board having thereon a multi-layered ceramic
`capacitor, a method thereof, a land pattern of a circuit board
`for the same, a packing unit for a multi-layered ceramic
`capacitor taped horizontally and an aligning method thereof.
`The present invention enables a vibration noise caused by the
`multi-layered ceramic capacitor to drastically decrease by
`forming lands of a circuit board where the multi-layered
`ceramic capacitor is mounted and conductively connecting
`the lands to the external terminal electrodes of the multi-
`
`layered ceramic capacitor in such a way that internal elec-
`trode layers of the multi-layered ceramic capacitor and the
`circuit board are arranged in a horizontal direction as a
`method of mounting a circuit board having thereon a multi-
`layered ceramic capacitor on which a plurality of dielectric
`sheet having internal electrodes formed thereon are stacked
`and the external terminal electrodes connected to the internal
`
`electrodes in parallel are formed on both ends thereof,
`wherein a height T5 of conductive material to conductively
`connect the external terminal electrodes to the lands is less
`
`than 1/3 of a thickness TMLCC of the multi-layered ceramic
`capacitor.
`[0005]
`2. Description of the Related Art
`[0006]
`In general, a multi-layered ceramic capacitor is a
`SMD (surface mount device) type capacitor and plays an
`important role of charging or discharging in the circuit of
`various electronic products such as a mobile phone, a note-
`book, a computer, a personal digital assistant (PDA).
`[0007]
`In general, the multi-layered ceramic capacitor has a
`structure in which the inner electrodes connected to opposite
`polarities are alternately stacked with dielectric layers
`between them.
`
`Such multi-layered ceramic capacitor has been
`[0008]
`widely used as components ofvarious electronic products due
`to the advantages of easy mounting, high capacitance and
`miniaturization.
`
`[0009] A ferroelectric material such as barium titanate hav-
`ing a relatively high dielectric constant is usually used as a
`dielectric material of the multi-layered ceramic capacitor.
`
`However, since such ferroelectric material has a piezoelectric
`property and an electrostrictive property, the mechanical
`stress and deformation occur when an electric field is applied
`to such ferroelectric material. In the case that a periodic
`electric field is applied to the multi-layered ceramic capacitor,
`the multi-layered ceramic capacitor vibrates by the mechani-
`cal deformation due to the piezoelectric property of its ferro-
`electric material. Such vibrations of the multi-layered
`ceramic capacitor are transferred to the circuit board having
`the multi-layered ceramic capacitor thereon.
`[0010] That is, if an alternative voltage is applied to the
`multi-layered ceramic capacitor, the stresses Fx, Fy and Fz
`are generated at a device body of the multi-layered ceramic
`capacitor according to each direction of X, Y and Z and the
`vibrations are generated by such stresses. These vibrations
`are transferred from the multi-layered ceramic capacitor to
`the circuit board and the vibrations of the circuit board gen-
`erate acoustic noises.
`
`In the case that the vibration frequency ofthe circuit
`[0011]
`board is within audible frequency range (20~20,000 Hz),
`such vibration noises give people an unpleasant feeling and
`therefore it is required to solve these problems.
`[0012]
`In recent years, in order to solve such problems,
`there have been disclosed various technologies such as a
`technology to prevent the vibration using the elastic defor-
`mation of the external terminals of the multi-layered ceramic
`capacitor, a technology to supplement an additional element
`to suppress the propagation of vibration generated by the
`piezoelectric and electrostrictive properties, and a technology
`to form substrate holes around the multi-layered ceramic
`capacitor mounted on substrate to suppress the vibration
`transfer from the multi-layered ceramic capacitor to the sub-
`strate. However, they require additional processes and do not
`give enough effect to prevent vibration noise in comparison
`with the complexity of processes.
`[0013] On the other hands, in the multi-layered ceramic
`capacitors, there is a multi-layered ceramic capacitor having
`a width equal or similar to a thickness. When the multi-
`layered ceramic capacitors with the similar width and thick-
`ness are mounted on a printed circuit board, are mounted on
`the printed circuit board irrespective of the directionality of
`the inner conductors within them. The reason is because the
`
`directionality of the inner conductors of the multi-layered
`ceramic capacitor cannot be recognized from an external
`appearance of the multi-layered ceramic capacitor with the
`similar width and thickness.
`
`[0014] The difference in electrical and mechanical charac-
`teristics of the multi-layered ceramic capacitor can be gener-
`ated according to the directionality of the inner conductors of
`the multi-layered ceramic capacitor which is mounted on the
`printed circuit board; and, particularly, the great difference in
`the vibration noise can be represented according to its direc-
`tionality.
`Particularly, recent test results show that the corre-
`[0015]
`lation between the mounting direction of the multi-layered
`ceramic capacitor and the amount of conductive material to
`connect the external electrode terminals of the multi-layered
`ceramic capacitor to the lands of circuit board influences the
`vibration noise characteristics greatly.
`[0016]
`Particularly, the vibration noise can be drastically
`reduced in case when the inner electrode surface ofthe multi-
`
`layered ceramic capacitor is mounted horizontally on the
`surface of the printed circuit board and the height of the
`conductive material to connect the external electrode termi-
`
`000011
`
`000011
`
`

`

`US 2012/0152604 A1
`
`Jun. 21,2012
`
`external terminal electrodes connected to the internal elec-
`
`trodes in parallel are formed on both ends thereof, including
`conductively connecting lands of a circuit board to the exter-
`nal terminal electrodes in such a way that internal electrode
`layers of the multi-layered ceramic capacitor and the circuit
`board are arranged in a horizontal direction, wherein a height
`TS of conductive material to conductively connect the exter-
`nal terminal electrodes to the lands is less than 1/3 of a thick-
`
`ness TMLCC of the multi-layered ceramic capacitor.
`[0023] Herein, the multi-layered ceramic capacitor with
`equal or similarwidth WMLCC and thickness TMLCCis taped to
`be mounted horizontally on the circuit board.
`[0024] Also, as described above, the number of dielectric
`layers of the multi-layered ceramic capacitor may be more
`than 200 layers and the dielectric thickness of the dielectric
`layer may be less than 3 pm, wherein the dielectric thickness
`of the dielectric layer may be less than 3 pm simultaneously
`while the number of dielectric layers of the multi-layered
`ceramic capacitor may be more than 200 layers.
`[0025] Meanwhile, in accordance with still another aspect
`of the present invention to achieve the object, there is pro-
`vided a method of mounting a circuit board having thereon a
`multi-layered ceramic capacitor on which a plurality of
`dielectric sheet having internal electrodes formed thereon are
`stacked and external terminal electrodes connected to the
`
`nals of the multi-layered ceramic capacitor to the lands of
`circuit board is reduced. Therefore, there are needs for a
`mounting structure, a mounting method, a land pattern of a
`circuit board, a packing unit for a multi-layered ceramic
`capacitor taped horizontally and an aligning method thereof
`to implement these.
`
`SUMMARY OF THE INVENTION
`
`[0017] The present invention has been invented in order to
`overcome the above-described problems and it is, therefore,
`an object of the present invention to provide a mounting
`structure of a circuit board having thereon a multi-layered
`ceramic capacitor, a method thereof capable of reducing
`noises generated by vibrations due to a piezoelectric phenom-
`enon, a land pattern of a circuit board for the same, a packing
`unit for a multi-layered ceramic capacitor taped horizontally
`and a aligning method thereof.
`[0018]
`In accordance with one aspect of the present inven-
`tion to achieve the object, there is provided a mounting struc-
`ture of a circuit board having thereon a multi-layered ceramic
`capacitor on which a plurality of dielectric sheet having inter-
`nal electrodes formed thereon are stacked and external termi-
`
`internal electrodes in parallel are formed on both ends thereof
`including: forming lands to mount the multi-layered ceramic
`capacitor on a surface of the circuit board, wherein the lands
`ofthe circuit board are conductively connected to the external
`terminal electrodes in such a way that internal electrode lay-
`ers of the multi-layered ceramic capacitor and the circuit
`board are arranged in a horizontal direction; the lands are
`formed in a plural number on a surface of the circuit board by
`being separated so as to correspond to portions on which the
`external terminal electrodes of the multi-layered ceramic
`capacitor are formed; and if a width and a length of the
`multi-layered ceramic capacitor are defined as WMLCC and
`LMLCC respectively, and a WLAND@ and a LLAND(a) are
`defined as a width and a length occupied at the circuit board
`from an outside edge of any one land among separated lands
`to an outside edge of another land, it is preferable that a
`relationship among the WMLCC, the LMLCC, the WLANMG) and
`the LLAND(a)
`is as
`follows:
`0<LLAND(a)/LMLCC, §l.2,
`0<WLAND(a)/WMLCCE 1.2. Herein,
`the lands mean the
`exposed portion without covering with the solder resist.
`[0026] Meanwhile, in accordance with still another aspect
`of the present invention to achieve the object, there is pro-
`vided a mounting structure of a circuit board having thereon
`a multi-layered ceramic capacitor on which a plurality of
`dielectric sheet having internal electrodes formed thereon are
`stacked and external terminal electrodes connected to the
`
`nal electrodes connected to the internal electrodes in parallel
`are formed on both ends thereof, including lands of a circuit
`board which is conductively connected to the external termi-
`nal electrodes in such a way that internal electrode layers of
`the multi-layered ceramic capacitor and the circuit board are
`arranged in a horizontal direction, wherein a height T5 of
`conductive material to conductively connect the external ter-
`minal electrodes to the lands is less than 1/3 of a thickness
`TMLCC of the multi-layered ceramic capacitor.
`[0019] Herein, when the multi-layered ceramic capacitor is
`packaged with a packing unit such as a reel, a taping is
`performed to align the multi-layered ceramic capacitors with
`equal or similar width WMLCC and thickness TMLCC in one
`direction in such a way that the inner electrodes of the multi-
`layered ceramic capacitors may be mounted on the circuit
`board in the horizontal direction. Herein,
`the equality
`between the width and the thickness of the multi-layered
`ceramic capacitor does not means the physical equality but
`the social standards equality and the similarity between the
`width and the thickness of the multi-layered ceramic capaci-
`tor may be within a range of 0.75 ETMLCC/WMLCCE l .25.
`[0020] On the other hands, as the number of dielectric
`layers within the multi-layered ceramic capacitor is larger or
`the electric field per thickness of the dielectric layer of the
`multi-layered ceramic capacitor is higher, the stress and the
`mechanical deformation due to the piezoelectric phenom-
`enon of the multi-layered ceramic capacitor become large;
`and, particularly, the vibration noise is significantly generated
`when the number of dielectric layers is more than 200 layers
`internal electrodes in parallel are formed on both ends thereof
`or when the dielectric layer thickness is less than 3 pm.
`including: forming lands to mount the multi-layered ceramic
`[0021] Accordingly, the number of dielectric layers of the
`capacitor on a surface of the circuit board, wherein the lands
`multi-layered ceramic capacitor may be more than 200 layers
`ofthe circuit board are conductively connected to the external
`and the dielectric thickness of the dielectric layer may be less
`terminal electrodes in such a way that internal electrode lay-
`than 3 pm, wherein the dielectric thickness of the dielectric
`ers of the multi-layered ceramic capacitor and the circuit
`layer may be less than 3 pm simultaneously while the number
`board are arranged in a horizontal direction; and the lands are
`of dielectric layers of the multi-layered ceramic capacitor
`formed in a plural number on a surface of the circuit board by
`may be more than 200 layers.
`being separated so as to correspond to edge portions of the
`[0022]
`In accordance with another aspect of the present
`external terminal electrodes of the multi-layered ceramic
`invention to achieve the object, there is provided a method of
`capacitor to reduce an amount of soldering.
`mounting a circuit board having thereon a multi-layered
`[0027] Herein, if a width and a length of the multi-layered
`ceramic capacitor on which a plurality of dielectric sheet
`ceramic capacitor are defined as WMLCC and LMLCC, respec-
`having internal electrodes formed thereon are stacked and
`000012
`
`000012
`
`

`

`US 2012/0152604 A1
`
`Jun. 21,2012
`
`[0032] Meanwhile, in accordance with still another aspect
`of the present invention to achieve the object, there is pro-
`vided a packing unit for a multi-layered ceramic capacitor
`including: the multi-layered ceramic capacitor on which a
`plurality of dielectric sheet having internal electrodes formed
`thereon are stacked and external terminal electrodes con-
`
`nected to the internal electrodes in parallel are formed on both
`ends thereof; and a packing sheet including a storing space to
`contain the multi-layered ceramic capacitor, wherein internal
`electrodes ofthe multi-layered ceramic capacitors are aligned
`to be horizontally arranged with reference to a bottom surface
`of the storing space.
`[0033] Herein,
`the packing unit for the multi-layered
`ceramic capacitor further includes a packing layer which is
`coupled to the packing sheet and covers the multi-layered
`ceramic capacitor.
`the packing unit for the multi-layered
`[0034] Herein,
`ceramic capacitor is wound in a shape of reel.
`[0035] On the other hands, in accordance with still another
`aspect of the present invention to achieve the object, there is
`provided a method of aligning a multi-layered ceramic
`capacitor having a thickness TMLCC equal or similar to a width
`WMLCC in a horizontal direction including: mounting the
`multi-layered ceramic capacitor on a transferring unit to
`transfer continuously; and supplying magnetic field to align
`the multi-layered ceramic capacitor transferred in the trans-
`ferring unit.
`[0036] Herein, the inner electrode layer of the multi-lay-
`ered ceramic capacitor passed through supplying magnetic
`field is arranged horizontally with reference to a bottom plane
`of the transferring unit.
`[0037] Herein, the transferring unit further includes a pair
`of guide units to align the multi-layered ceramic capacitor.
`[0038] Herein, if a gap between the pair of guide units and
`a width, a thickness and a length ofthe multi-layered ceramic
`capacitor are defined as g, WMLCC, TMLCC and LMLCC,
`respectively, the following relationship is satisfied:
`
`‘/1W2MLCC+T2MLCC)<g<miH[\/(L2MLCC+T2MLCC)a
`
`[1
`
`(L2Ml.CC+ W2MLCC)]
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0039] These and/or other aspects and advantages of the
`present general inventive concept will become apparent and
`more readily appreciated from the following description of
`the embodiments, taken in conjunction with the accompany-
`ing drawings of which:
`[0040]
`FIG. 1 is a cross-sectional view showing a structure
`to mount a multi-layered ceramic capacitor horizontally on a
`circuit board in accordance with an embodiment of the
`
`tively, and a WLAND(b) and a LLANab) are defined as a width
`and a length occupied at the circuit board from an outside
`edge of any one land among separated lands to an outside
`edge of another land, a relationship among the WMLCC, the
`LMLCC, the WLAND(b) andthe LLAND(b) is as follows: 0<LL/[ND
`(1))/LMLCC, §1.2, 0<WLAND(b)/WMLCC§1.2.
`[0028]
`In the method of mounting the circuit board having
`thereon the multi-layered ceramic capacitor in accordance
`with the present
`invention which defines the lands as
`described above, a height T5 of conductive material to con-
`ductively connect the external terminal electrodes to the lands
`is less than 1/3 of a thickness TMLCC of the multi-layered
`ceramic capacitor.
`[0029] And also, in the method of mounting the circuit
`board having thereon the multi-layered ceramic capacitor in
`accordance with the present invention which defines the lands
`as described above, when the multi-layered ceramic capacitor
`is packaged with a packing unit such as a reel, a taping is
`performed to align the multi-layered ceramic capacitors with
`equal or similar width WMLCC and thickness TMLCC in one
`direction in such a way that the inner electrode of the multi-
`layered ceramic capacitor may be mounted on the circuit
`board in the horizontal direction. Herein, the equality and the
`similarity between the width and the thickness of the multi-
`layered ceramic capacitor may be within a range of 0.75
`TMLCC/WMLCC§1‘25‘
`[0030] Meanwhile, in accordance with still another aspect
`of the present invention to achieve the object, there is pro-
`vided a land pattern on a circuit board having thereon a
`multi-layered ceramic capacitor on which a plurality of
`dielectric sheet having internal electrodes formed thereon are
`stacked and external terminal electrodes connected to the
`
`internal electrodes in parallel are formed on both ends
`thereof, wherein the land pattern is formed in a plural number
`on a surface of the circuit board by being separated so as to
`correspond to portions of the external terminal electrodes of
`the multi-layered ceramic capacitor, wherein if a width and a
`length of the multi-layered ceramic capacitor are defined as
`WMLCC and LMLCC, respectively, and a WLAND@ and a LLAND
`(a) are defined as a width and a length occupied at the circuit
`board from an outside edge of any one land among separated
`lands to an outside edge of another land, a relationship among
`the WMLCC, the LMLCC, the WLAND(a) and the LLAND(a) is as
`follows: 0<LLAND(a)/LMLCO §1-2: 0<WLAND(a)/WMLCC§1-
`
`2 [
`
`0031] And also, in accordance with still another aspect of
`the present invention to achieve the object, there is provided a
`land pattern on a circuit board having thereon a multi-layered
`ceramic capacitor on which a plurality of dielectric sheet
`having internal electrodes formed thereon are stacked and
`external terminal electrodes connected to the internal elec-
`
`trodes in parallel are formed on both ends thereof, wherein the
`land pattern is formed in a plural number on a surface of the
`circuit board by being separated so as to correspond to edge
`portions of the external terminal electrodes of the multi-
`layered ceramic capacitor to reduce an amount of soldering,
`wherein if a width and a length of the multi-layered ceramic
`capacitor are defined as WMLCC and LMLCC, respectively, and
`a WLAND(b) and a LLANab) are defined as a width and a length
`occupied at the circuit board from an outside edge of any one
`land among separated lands to an outside edge of another
`land, it is preferable that a relationship among the WMLCC, the
`LMLCC, the WLAND(b) andthe LLAND(b) is as follows: 0<LL/[ND
`(1))/LMLCC, §1.2, 0<WLAND(b)/WMLCC§1.2.
`
`present invention;
`[0041]
`FIG. 2 is a diagram showing a multi-layered ceramic
`capacitor a having a thickness equal or similar to a width
`thereof and a multi-layered ceramic capacitor b having a
`width greater than a thickness thereof;
`[0042]
`FIG. 3 is a plan view showing a circuit board having
`a land pattern in accordance with another embodiment of the
`present invention;
`[0043]
`FIG. 4 is a simulation diagram for showing a rela-
`tionship between a land and a width and a length of the
`multi-layered ceramic capacitor in accordance with still
`another embodiment of the present invention;
`000013
`
`000013
`
`

`

`US 2012/0152604 A1
`
`Jun. 21,2012
`
`FIG. 5 is a plan View showing a circuit board in
`[0044]
`accordance with still another embodiment of the present
`invention;
`[0045]
`FIG. 6 is a simulation diagram for showing a rela-
`tionship between a land and a width and a length of the
`multi-layered ceramic capacitor in accordance with still
`another embodiment of the present invention;
`[0046]
`FIG. 7 is a diagram showing a packing unit for a
`multi-layered ceramic capacitor arranged in parallel in accor-
`dance with still another embodiment ofthe present invention;
`[0047]
`FIG. 8 is a diagram showing a packing unit for a
`multi-layered ceramic capacitor wound in a shape of reel in
`accordance with still another embodiment of the present
`invention;
`[0048]
`FIG. 9 is a simulation diagram showing a status that
`a multi-layered ceramic capacitor is aligned by a magnetic
`field;
`FIG. 10 and FIG. 11 are simulation diagrams show-
`[0049]
`ing views aligned by a magnetic field while a multi-layered
`ceramic capacitor is transferred by a transferring unit;
`[0050]
`FIG. 12 is a simulation diagram showing a horizon-
`tal direction alignment method of a multi-layered ceramic
`capacitor in accordance with still another embodiment of the
`present invention;
`[0051]
`FIG. 13 is a simulation diagram showing a case (a)
`when a multi-layered ceramic capacitor is horizontally
`mounted on a circuit board and a case (b) when a multi-
`layered ceramic capacitor is vertically mounted on a circuit
`board as test examples of the present invention;
`[0052]
`FIG. 14 is a graph showing an effect that a height of
`a conductive material (solder) has on a vibration noise when
`a multi-layered ceramic capacitor is horizontally or vertically
`mounted on a circuit board as test examples of the present
`invention; and
`[0053]
`FIG. 15 is a graph showing an effect that a size of a
`land has on a vibration noise when a multi-layered ceramic
`capacitor is horizontally or vertically mounted on a circuit
`board as test examples of the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERABLE EMBODIMENTS
`
`[0057] At first, the present invention will be explained in
`detail with reference to the accompanying drawings as fol-
`lows.
`
`A Mounting Structure of a Circuit Board Having Thereon a
`Multi-Layered Ceramic Capacitor and a Mounting Method
`Thereof
`
`FIG. 1 is a cross-sectional view showing a structure
`[0058]
`to mount a multi-layered ceramic capacitor 10 horizontally
`on a circuit board in accordance with an embodiment of the
`
`present invention.
`[0059] A structure and a method of mounting a circuit
`board 20 having thereon a multi-layered ceramic capacitor 10
`includes stacking a dielectric sheet 11 having internal elec-
`trodes 12 formed thereon, forming external terminal elec-
`trodes 14a and 14b to connect the internal electrode 12 in
`
`parallel on both ends of the multi-layered ceramic capacitor
`10, forming lands (not shown in FIG. 1) on a surface of the
`circuit board 20 to mount the multi-layered ceramic capacitor
`10, and conductively connecting the lands to the external
`terminal electrodes 14a and 14b by arranging the inner elec-
`trode layer 12 of the multi-layered ceramic capacitor 10 in a
`horizontal direction with reference to the surface ofthe circuit
`
`board 20, wherein a height TS of a conductive material 15 to
`conductively connect the external terminal electrodes 14a
`and 14b to the lands is less than 1/3 ofa thickness TMLCC ofthe
`multi-layered ceramic capacitor.
`the multi-layered ceramic
`[0060] As shown in FIG. 1,
`capacitor 10 includes a body 13 formed by alternately stack-
`ing the dielectric layer 11 and the internal electrode 12, and
`the pair of external electrodes 14a and 14b to alternately
`connect the internal electrode 12 in parallel at both ends ofthe
`body 13.
`[0061] The dielectric layer 11 is made of a ferroelectric
`material mainly composed of barium titanate or the like and
`can be made of the other ferroelectric materials.
`
`[0062] The internal electrode 12 is made of a thin metal
`formed by sintering a metal paste and the metal paste can be
`composed of metal materials such as Ni, Pd, Ag—Pd, Cu or
`the like as main components.
`[0063] The pair of external electrodes 14a and 14b are
`made of a metal material such as Cu and Ni or the like and a
`
`plating is performed on the surfaces ofthe external electrodes
`14a and 14b in order to improve the wetting property of
`solder.
`
`[0054] Hereinafter, specific embodiments of the present
`invention will be described with reference to the accompany-
`ing drawings. However, the following embodiments are pro-
`vided as examples but are not intended to limit the present
`invention thereto.
`
`[0055] Descriptions of well-known components and pro-
`cessing techniques are omitted so as not to urmecessarily
`obscure the embodiments of the present invention. The fol-
`lowing terms are defined in consideration of functions of the
`present invention and may be changed according to users or
`operator’s intentions or customs. Thus, the terms shall be
`defined based on the contents described throughout the speci-
`fication.
`
`[0056] The technical spirit of the present invention should
`be defined by the appended claims, and the following
`embodiments are merely examples for efiiciently describing
`the technical spirit of the present invention to those skilled in
`the art.
`
`[0064] Lands are formed on a surface of circuit board 20 to
`mount the multi-layered ceramic capacitor 10, wherein the
`lands mean the exposed portions of metal pad without being
`covered with the solder resist. Herein, the circuit board 20 can
`be a multi-layered circuit board and the like and there is no
`limitation in a type thereof.
`[0065] As shown in FIG. 2, a width W of the multi-layered
`ceramic capacitor 10 may be equal or similar to a thickness T
`thereof (see FIG. 2a) and a width ofthe multi-layered ceramic
`capacitor 10 is greater than a thickness thereof (see FIG. 2b).
`For the latter case, it always becomes the horizontal mounting
`due to its slim thickness, but, for the former case, the hori-
`zontal mounting and the vertical mounting are randomly per-
`formed. Herein, the equality and the similarity between the
`width WMLCC and the thickness TML CC of the multi-layered
`ceramic capacitor 10 may be within a range of 0.75 §TMLCC/
`WMLCCE l .25.
`[0066] As the conductive material 15 such as solder plays a
`role of a vibration medium between the multi-layered
`000014
`
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`

`

`US 2012/0152604 A1
`
`Jun. 21,2012
`
`ceramic capacitor 10 and the circuit board 20, the vibration
`transfer from the multi-layered ceramic capacitor to the cir-
`cuit board deteriorates as lowering the height of the conduc-
`tive material 15. In the case of the horizontal mounting of the
`multi-layered ceramic capacitor on the circuit board, the main
`vibration surface of the multi-layered ceramic capacitor is
`estimated to be parallel to the surface ofthe circuit board. The
`vibration of the top surface of the multi-layered ceramic
`capacitor in the horizontal mounting is difficult to transfer to
`the circuit board in the case of low height of conductive
`material because there is no vibration medium around its top
`surface due to low height of conductive material. Therefore,
`as the height of conductive material becomes low, the vibra-
`tion noise greatly decreases in the case of the horizontal
`mounting of the multi-layered ceramic capacitor on the cir-
`cuit board.
`
`[0067] On the other hands, in the case ofthe vertical mount-
`ing of the multi-layered ceramic capacitor on the circuit
`board,
`the main vibration surface of the multi-layered
`ceramic capacitor is estimated to be perpendicular to the
`surface of the circuit board. The vibration of the side surface
`
`of the multi-layered ceramic capacitor in the vertical mount-
`ing can be transferred to the circuit board even in the case of
`low height of conductive material because there is a vibration
`medium around the bottom portion of its side surface in spite
`of low height of conductive material. Therefore, as the height
`of conductive material becomes low,
`the vibration noise
`decreases slowly in the case of the vertical mounting of the
`multi-layered ceramic capacitor on the circuit board but the
`decrease of vibration noise in the vertical mounting is much
`less than that in the horizontal mounting.
`[0068] Accordingly, in order to reduce the vibration noise
`due to the multi-layered ceramic capacitor 10, it is preferable
`that the multi-layered ceramic capacitor 10 is mounted in the
`horizontal direction that means the internal electrode 12
`
`capacitor 10 of FIG. 1 are formed. Herein, the lands 21 and 22
`me