(12) Ulllted States Patent
`Lee et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 9,326,381 B2
`Apr. 26, 2016
`
`US009326381B2
`
`(72)
`
`(54) MULTILAYER CERAMIC CAPACITOR AND
`BOARD HAVING THE SAME MOUNTED
`THEREON
`.
`(71) Applicant: SAMSUNG ELECTRO-MECHANICS
`CO., LTD., Suwon-Si, Gyeonggi-Do
`(KR)
`
`,
`Inventors: Byoung Hwa Lee, Suwon-Si (KR);
`Heung Kil Park, Suwon-Si (KR); Kyo
`Kwang Lee, Suwon-Si (KR); Young
`Ghyu Ahn, Suwon-Si (KR); Sang S00
`Park, Suwon-Si (KR); Soon Ju Lee,
`<KR>
`(73) Assignee: SAMSUNG ELECTRO-MECHANICS
`CO., LTD., Suwon-Si, Gyeonggi-Do
`(KR)
`
`USPC .............. .. 361/301.4, 303-305, 306.1, 306.3,
`351/321-1, 3212
`See application file for complete search history.
`R f
`C't d
`° "'“"“°°5
`‘ °
`Us. PATENT DOCUMENTS
`
`56
`
`(
`
`)
`
`5,134,540 A 1‘
`5,952,040 A T
`
`7/1992 R tt
`9/1999 YEW
`.
`(commued)
`FOREIGN PATENT DOCUMENTS
`
`KR
`
`1023321125235:
`1/232:
`10-2008-0110180 A
`12/2008
`OTHER PUBLICATIONS
`
`<*>
`
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 197 days.
`(21) Appl.No.: 14/259,011
`
`240, 1995 IEEET
`
`(Continued)
`
`(22) Filed.
`
`Apt 22, 2014
`
`(65)
`
`Prior Publication Data
`
`.
`Primary Examiner — Nguyen T Ha
`(74) Attorney, Agent, or Firm — McDermott Will & Emery
`LLP
`
`US 2014/0367152 A1
`
`Dec. 18, 2014
`
`(57)
`
`ABSTRACT
`
`Foreign Application Priority Data
`(30)
`Jun. 14, 2013
`(KR) ...................... .. 10-2013-0068498
`(51)
`Int CL
`H01G 4/30
`H05K 1/11
`
`(2005-01)
`(2006.01)
`(Continued)
`
`(52) U-S- CL
`CPC ........... .. H05K1/111 (2013.01); H01 G 4/1209
`(2013.01); H01G 4/232 (2013.01); H01G 4/30
`(2013.01);
`
`(Continued)
`
`(58) Field Of Classificatiml Search
`CPC ........... .. H01G 4/30; H01G 4/06; H01G 4/12;
`H01G 4/005; H01G 4/008
`
`A Iiluétilaygr lceramif Capacitfirlrflay ingudet 6:1ceramig body
`inc u ing ie ectric ayers an
`aving rst an secon main
`surfaqes oppglslnlzlg eachdogher, fiést anddsecznd lffide surfaces
`opposing eac ot er, an
`rst an secon en su aces oppos-
`ing each other; an active layer configured to form capacitance
`by including first and second internal electrodes facing each
`other with one dielectric layer therebetween and alternately
`exposed to the first or second side surface; upper and lower
`cover layers disposed on and below the active layer; and a first
`external electrode disposed on the first side surface and a
`second external electrode disposed on the second side sur-
`face. Thickness T and width W of the ceramic body satisfy
`0.75WsTs1.25W, gap G between the first and second exter-
`nal electrodes satisfies 30 p.msGs0.9W, and an average num-
`ber of dielectric grains in a single dielectric layer in a thick-
`ness direction thereof is 2 or greater.
`
`19 Claims, 5 Drawing Sheets
`
`Exhibit 1001
`
`000001
`
`PGR2017-00010
`
`AVX CORPORATION
`
`000001
`
`Exhibit 1001
`PGR2017-00010
`AVX CORPORATION
`
`

`

`US 9,326,381 B2
`Page 2
`
`(51)
`
`Int. Cl.
`H01G 4/232
`H05K 3/34
`HOIG 4/12
`
`(2006.01)
`(2006.01)
`(2006.01)
`
`(52) U.S. Cl.
`CPC .......... ..
`
`HOIG 4/12 (2013.01); H05K 3/3442
`(2013.01); H05K 220]/0979 (2013.01); H05K
`220]/09709 (2013.01); H05K 2201/10015
`(2013.01); H05K 220]/2045 (2013.01); YOZP
`70/611 (2015.11)
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`6,377,439 B1*
`
`7,414,857 B2T
`8,238,116 B2T
`8,263,515 B2*
`
`4/2002 Sekidou ............... .. H01G4/005
`361/303
`
`8/2008 Ritter
`8/2012 Eggerding
`9/2012 Dogan ................. .. B82Y30/00
`501/127
`
`8,383,535 B2 *
`
`8,437,115 B2*
`
`8,737,037 B2 *
`
`9,009,240 B2 *
`
`9,129,750 B2*
`2008/0310074 A1
`2008/0310078 A1
`
`2/2013 Yamaguchi
`
`........... .. C04B 35/46
`361/321.4
`5/2013 Kim ....................... .. H01G 4/30
`361/305
`5/2014 Kim ................... .. H01G 4/0085
`361/305
`4/2015 Milic-Frayling .... .. G06Q 10/10
`370/432
`9/2015 Kim ................... .. H01G 4/1209
`12/2008 Togashi et al.
`12/2008 Lee et al.
`
`OTHER PUBLICATIONS
`
`Joseph M. Hock et a1.; TecF0rum TF-MP2, Inductance of Bypass
`Capacitors How to Define, How to Measure, How to Simulate,
`DesignC0n East 2005.T
`
`* cited by examiner
`T cited by third party
`
`000002
`
`000002
`
`

`

`U.S. Patent
`
`Apr. 26,2016
`
`Sheet 1 of5
`
`US 9,326,381 B2
`
`1 0
`
`132
`
`110
`
`131
`
`FIG.
`
`1
`
`000003
`
`000003
`
`

`

`U.S. Patent
`
`Apr. 26,2016
`
`Sheet 2 of5
`
`US 9,326,381 B2
`
`111
`
`FIG. 3
`
`000004
`
`000004
`
`

`

`U.S. Patent
`
`Apr. 26,2016
`
`Sheet 3 of5
`
`US 9,326,381 B2
`
`132
`
`Z
`
`131
`
`112
`122 f“IIATII"'“"" _
`yJJJJJJA 5.
`V
`
`IVHIIZZZJVZJZZZ ‘
`
`121
`
`111
`
`
`
`
`
`? __
`
`113
`
`
`
`1%
`W
`A - A'
`
`L
`
`T
`L»w
`
`FIG. 4
`
`
`
`‘
`
`X
`
`111a
`
`2 F
`
`IG. 5
`
`000005
`
`000005
`
`

`

`U.S. Patent
`
`Apr. 26,2016
`
`Sheet 4 of5
`
`US 9,326,381 B2
`
`200
`
`FIG. 6
`
`100
`
`230
`
`222
`
`132
`
`110
`
`131
`
`LL 210
`
`230
`
`221 K200
`
`FIG. 7
`
`000006
`
`000006
`
`

`

`U.S. Patent
`
`Apr. 26,2016
`
`Sheet 5 of5
`
`US 9,326,381 B2
`
`100
`
`230
`
`223'
`
`230
`
`224'
`
`132
`
`110
`
`I
`W
`LL 210
`
`230
`
`221'
`
`230
`
`222' K
`
`200
`
`FIG. 8
`
`100
`
`230
`
`222”
`
`132
`
`110
`
`131
`
`W
`
`
`
`LL 210
`
`230
`
`221"
`
`R200
`
`FIG. 9
`
`000007
`
`000007
`
`

`

`US 9,326,381 B2
`
`1
`MULTILAYER CERAMIC CAPACITOR AND
`BOARD HAVING THE SAME MOUNTED
`THEREON
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This application claims the benefit of Korean Patent Appli-
`cation No. l0-2013-0068498 filed on Jun. 14, 2013, with the
`Korean Intellectual Property Office, the disclosure ofwhich is
`incorporated herein by reference.
`
`BACKGROUND
`
`The present disclosure relates to a multilayer ceramic
`capacitor and a board having the same mounted thereon.
`In accordance with the recent trend toward miniaturization
`
`and high capacitance of electronic products, electronic com-
`ponents used in the electronic products are required to have a
`small size and high capacitance. Therefore, a demand for a
`multilayer ceramic electronic component has been increased.
`In the case of a multilayer ceramic capacitor, as equivalent
`series
`inductance
`(hereinafter,
`referred to as “ESL”)
`increases, performance of an electronic product may deterio-
`rate. In addition, in a case in which an electronic component
`is miniaturized and capacitance thereofis increased, the influ-
`ence of an increase in ESL on deterioration in performance of
`the electronic product has relatively increased.
`A so-called “low inductance chip capacitor (LICC)” is to
`decrease inductance by decreasing a distance between exter-
`nal terminals to shorten a current flow path.
`Meanwhile, the multilayer ceramic capacitor may have a
`structure in which a plurality of dielectric layers and internal
`electrodes having opposite polarities and having at least one
`of the dielectric layers interposed therebetween are alter-
`nately stacked.
`Since the dielectric layers have piezoelectric and electros-
`trictive properties, when direct current (DC) or alternating
`current (AC) voltage is applied to the multilayer ceramic
`capacitor, a piezoelectric phenomenon may occur between
`the internal electrodes, causing vibrations.
`Such vibrations may be transferred to a printed circuit
`board on which the multilayer ceramic capacitor is mounted
`through a solder, such that the entire printed circuit board may
`become an acoustic reflection surface to transmit the sound of
`vibrations as noise.
`
`Vibration noise may have a frequency corresponding to an
`audio frequency within a range of 20 to 20000 Hz, potentially
`causing listener discomfort. The vibration noise causing lis-
`tener discomfort, as described above, is known as acoustic
`noise.
`
`Research into a technology of reducing the acoustic noise
`in a multilayer ceramic capacitor is still demanded.
`
`SUMMARY
`
`An aspect of the present disclosure may provide a multi-
`layer ceramic capacitor and a board having the same mounted
`thereon.
`
`According to an aspect of the present disclosure, a multi-
`layer ceramic capacitor may include: a ceramic body includ-
`ing dielectric layers and having first and second main surfaces
`opposing each other, first and second side surfaces opposing
`each other, and first and second end surfaces opposing each
`other; an active layer configured to form capacitance by
`including a plurality of first and second internal electrodes
`disposed to face each other with at least one of the dielectric
`
`2
`
`layers interposed therebetween and alternately exposed to the
`first or second side surface; upper and lower cover layers
`disposed on and below the active layer, respectively; and a
`first external electrode disposed on the first side surface ofthe
`ceramic body and electrically connected to the first internal
`electrodes and a second external electrode disposed on the
`second side surface and electrically connected to the second
`internal electrodes, wherein when a thickness of the ceramic
`body is defined as T and a width thereof is defined as W,
`0.75WsTsl.25W may be satisfied, when a gap between the
`first and second external electrodes is defined as G, 30
`p.msGs0.9W may be satisfied, and an average number of
`dielectric grains in a single dielectric layer in a thickness
`direction thereof may be 2 or greater.
`The lower cover layer may have a thickness of l 0 um to 100
`pm.
`When the thickness of the ceramic body is a distance
`between the first and second main surfaces, the width of the
`ceramic body is a distance between the first side surface on
`which the first external electrode is formed and the second
`side surface on which the second external electrode is formed,
`and a length ofthe ceramic body is a distance between the first
`and second end surfaces, the distance between the first and
`second side surfaces may be shorter than or equal to the
`distance between the first and second end surfaces.
`
`When the length and the width of the ceramic body are
`defined as L and W, respectively, 0.5LsWsL may be satisfied.
`An average grain size ofthe dielectric grains may be 50 nm
`to 500 nm.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`The first and second internal electrodes may be spaced
`apart from the first and second end surfaces of the ceramic
`body by a predetermined distance.
`The first and second external electrodes may be extended to
`portions of the first and second main surfaces of the ceramic
`body.
`According to another aspect of the present disclosure, a
`board having a multilayer ceramic capacitor mounted thereon
`may include: a printed circuit board having two or more
`electrode pads formed thereon;
`the multilayer ceramic
`capacitor mounted on the printed circuit board; and a solder
`connecting the electrode pads and the multilayer ceramic
`capacitor, wherein the multilayer ceramic capacitor may
`include: a ceramic body including dielectric layers and hav-
`ing first and second main surfaces opposing each other, first
`and second side surfaces opposing each other, and first and
`second end surfaces opposing each other; an active layer
`configured to form capacitance by including a plurality of
`first and second internal electrodes disposed to face each
`other with at least one of the dielectric layers interposed
`therebetween and alternately exposed to the first or second
`side surface; upper and lower cover layers disposed on and
`below the active layer, respectively; and a first external elec-
`trode disposed on the first side surface of the ceramic body
`and electrically connected to the first internal electrodes and
`a second external electrode disposed on the second side sur-
`face and electrically connected to the second internal elec-
`trodes, wherein when a thickness of the ceramic body is
`defined as T and a width thereof is defined as W,
`0.75WsTsl.25W may be satisfied, when a gap between the
`first and second external electrodes is defined as G, 30
`p.msGs0.9W may be satisfied, and an average number of
`dielectric grains in a single dielectric layer in a thickness
`direction thereof may be 2 or greater.
`The lower cover layer may have a thickness of l 0 um to 100
`pm.
`When the thickness of the ceramic body is a distance
`between the first and second main surfaces, the width of the
`000008
`
`000008
`
`

`

`US 9,326,381 B2
`
`3
`ceramic body is a distance between the first side surface on
`which the first external electrode is formed and the second
`
`side surface on which the second external electrode is formed,
`and a length ofthe ceramic body is a distance between the first
`and second end surfaces, the distance between the first and
`second side surfaces may be shorter than or equal to the
`distance between the first and second end surfaces.
`
`When the length and the width of the ceramic body are
`defined as L and W, respectively, 0.5LsWsL may be satisfied.
`An average grain size ofthe dielectric grains may be 50 nm
`to 500 nm.
`
`The first and second internal electrodes may be spaced
`apart from the first and second end surfaces of the ceramic
`body by a predetermined distance.
`The first and second external electrodes may be extended to
`portions of the first and second main surfaces of the ceramic
`body.
`The solder may be disposed around portions ofthe first and
`second external electrodes of the multilayer ceramic capaci-
`tor.
`
`The solder may be disposed around central portions of the
`first and second external electrodes of the multilayer ceramic
`capacitor.
`The electrode pads may include first and second electrode
`pads connected to the first and second external electrodes of
`the multilayer ceramic capacitor, respectively.
`The first and second electrode pads may be offset to each
`other in a width direction of the multilayer ceramic capacitor.
`The electrode pads may include first and second electrode
`pads connected to the first external electrode ofthe multilayer
`ceramic capacitor and third and fourth electrode pads con-
`nected to the second external electrode of the multilayer
`ceramic capacitor.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`The above and other aspects, features and other advantages
`of the present disclosure will be more clearly understood
`from the following detailed description taken in conjunction
`with the accompanying drawings, in which:
`FIG. 1 is a perspective view showing a multilayer ceramic
`capacitor according to an exemplary embodiment of the
`present disclosure;
`FIG. 2 is a view showing a ceramic body according to an
`exemplary embodiment of the present disclosure;
`FIG. 3 is an exploded perspective view of FIG. 2;
`FIG. 4 is a cross-sectional view taken along line A-A‘ of
`FIG. 1;
`FIG. 5 is an enlarged view of part Z of FIG. 4;
`FIG. 6 is a perspective view showing a structure in which
`the multilayer ceramic capacitor of FIG. 1 is mounted on a
`printed circuit board;
`FIG. 7 is a plan view of FIG. 6;
`FIG. 8 is a plan view of FIG. 6 according to another exem-
`plary embodiment of the present disclosure; and
`FIG. 9 is a plan view of FIG. 6 according to another exem-
`plary embodiment of the present disclosure.
`
`DETAILED DESCRIPTION
`
`Exemplary embodiments of the present disclosure will
`now be described in detail with reference to the accompany-
`ing drawings.
`The disclosure may, however, be embodied in many differ-
`ent forms and should not be construed as being limited to the
`embodiments set forth herein. Rather, these embodiments are
`
`4
`
`provided so that this disclosure will be thorough and com-
`plete, and will fully convey the scope of the disclosure to
`those skilled in the art.
`
`In the drawings, the shapes and dimensions of elements
`may be exaggerated for clarity, and the same reference
`numerals will be used throughout to designate the same or
`like elements.
`
`Multilayer Ceramic Capacitor
`FIG. 1 is a perspective view showing a multilayer ceramic
`capacitor according to an exemplary embodiment of the
`present disclosure.
`FIG. 2 is a view showing a ceramic body according to an
`exemplary embodiment of the present disclosure.
`FIG. 3 is an exploded perspective view of FIG. 2.
`FIG. 4 is a cross-sectional view taken along line A-A‘ of
`FIG. 1.
`
`Referring to FIGS. 1 through 4, a multilayer ceramic
`capacitor 100 according to an exemplary embodiment of the
`present disclosure may include a ceramic body 110 including
`dielectric layers 111 and having first and second main sur-
`faces S1 and S2 opposing each other, first and second side
`surfaces S5 and S6 opposing each other, and first and second
`end surfaces S3 and S4 opposing each other; an active layerA
`configured to form capacitance by including a plurality of
`first and second internal electrodes 121 and 122 disposed to
`face each other, having at least one ofthe dielectric layers 111
`interposed therebetween, and alternately exposed to the first
`or second side surface S5 or S6; upper and lower cover layers
`112 and 113 formed on and below the active layer A; and a
`first external electrode 131 formed on the first side surface S5
`
`ofthe ceramic body 110 and electrically connected to the first
`internal electrode 121 and a second external electrode 132
`
`formed on the second side surface S6 and electrically con-
`nected to the second internal electrode 122, wherein when a
`thickness of the ceramic body 110 is defined as T and a width
`thereof is defined as W, T and W satisfy 0.75WsTsl.25W,
`when a gap between the first and second external electrodes
`131 and 132 is defined as G,
`the gap G satisfies 30
`p.msGs0.9W, and the average number of dielectric grains
`111a present in a single dielectric layer in a thickness direc-
`tion thereof is 2 or greater.
`Hereinafter, a multilayer ceramic electronic component
`according to an exemplary embodiment of the present disclo-
`sure will be described. Particularly, a multilayer ceramic
`capacitor will be described, but the present disclosure is not
`limited thereto.
`
`Referring to FIG. 1, in the multilayer ceramic capacitor
`according to an exemplary embodiment of the present disclo-
`sure, a ‘length direction’ refers to an ‘L’ direction, a ‘width
`direction’ refers to a ‘W’ direction, and a ‘thickness direction’
`refers to a ‘T’ direction. Here, the ‘thickness direction’ may be
`the same as a stacking direction in which dielectric layers are
`stacked.
`
`Referring to FIG. 2, in the exemplary embodiment of the
`present disclosure, the ceramic body 110 may have the first
`and second main surfaces S1 and S2 opposing each other, and
`the first and second side surfaces S5 and S6 and the first and
`second end surfaces S3 and S4 that connect the first and
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`second main surfaces S1 and S2 to each other. A shape of the
`ceramic body 110 is not particularly limited, but may be a
`hexahedral shape as shown.
`Referring to FIG. 3, a raw material forming the dielectric
`layers 111 is not particularly limited as long as sufficient
`capacitance may be obtained, but may be, for example,
`barium titanate (BaTiO3) powder.
`The material forming the dielectric layer 111 may further
`contain various ceramic additives, organic solvents, plasticiz-
`000009
`
`000009
`
`

`

`US 9,326,381 B2
`
`5
`ers, binders, dispersing agents, or the like, according to
`intended use of the capacitor, in addition to ceramic powder
`such as barium titanate (BaTiO3) powder, or the like.
`An average particle size of the ceramic powder used to
`form the dielectric layers 111 is not particularly limited and
`may be controlled, for example, to be 400 nm or less.
`A material for the first and second internal electrodes 121
`
`and 122 is not particularly limited. For example, the first and
`second internal electrodes 121 and 122 may be formed of a
`conductive paste including at least one of a noble metal mate-
`rial such as palladium (Pd), a palladium-silver (Pd—Ag)
`alloy, or the like, nickel (Ni), and copper (Cu).
`The first and second internal electrodes 121 and 122 may
`be disposed to face each other, having at least one of the
`dielectric layers 111 interposed therebetween, and may be
`alternately exposed to the first or second side surface S5 or S6.
`The first and second internal electrodes 121 and 122 are
`
`alternately exposed to the first or second side surface S5 or S6,
`such that a reverse geometry capacitor (RGC) or low induc-
`tance chip capacitor (LICC) may be obtained as described
`below.
`
`In a general multilayer ceramic electronic component,
`external electrodes may be disposed on opposing end surfaces
`of the ceramic body in a length direction thereof.
`In this case, when an alternative current (AC) voltage is
`applied to the external electrodes, a current path is relatively
`long, whereby an intensity of an induced magnetic field may
`be increased, resulting in an increase in inductance.
`In order to solve this problem, the first and second external
`electrodes 131 and 132 in the exemplary embodiment of the
`present disclosure may be disposed on the first and second
`side surfaces S5 and S6 of the ceramic body 110 opposing
`each other in the width direction so as to reduce the current
`
`path.
`In this case, since a distance between the first and second
`external electrodes 131 and 132 is relatively short, the current
`path may be reduced, the current path may be reduced, result-
`ing in a reduction in inductance.
`As described above, the first and second external elec-
`trodes 131 and 132 may be formed on the first and second side
`surfaces S5 and S6 of the ceramic body 110 opposing each
`other in the width direction and may be electrically connected
`to the first and second internal electrodes 121 and 122 in order
`
`to form capacitance.
`The first and second external electrodes 131 and 132 may
`be formed of the same conductive material as that of the first
`and second internal electrodes 121 and 122 but are not limited
`
`thereto. For example, the first and second external electrodes
`131 and 132 may be formed of a metal powder including
`copper (Cu), silver (Ag), nickel (Ni), or the like.
`The first and second external electrodes 131 and 132 may
`be formed by applying a conductive paste prepared by adding
`glass frits to the metal powder and then sintering the applied
`conductive paste.
`A width W of the ceramic body 110 may be a distance
`between the first side surface S5 on which the first external
`electrode 131 is formed and the second side surface S6 on
`which the second external electrode 132 is formed, and a
`length L of the ceramic body 110 may be a distance between
`the first and second end surfaces S3 and S4.
`
`According to the exemplary embodiment of the present
`disclosure, the distance between the first and second side
`surfaces 5 and 6 on which the first and second external elec-
`
`trodes 131 and 132 are formed, respectively, may be less than
`or equal to the distance between the first and second end
`surfaces 3 and 4.
`
`6
`Since the distance between the first and second external
`
`electrodes 131 and 132 is shortened, the current path may be
`shortened, resulting in a reduction in inductance.
`As described above, the multilayer ceramic capacitor, in
`which the first and second external electrodes 131 and 132 are
`formed on the first and second side surfaces 5 and 6 of the
`
`ceramic body 110, may be a reverse geometry capacitor
`(RGC) or low inductance chip capacitor (LICC).
`Referring to FIG. 4, the ceramic body 110 may include the
`active layer A contributing to forming capacitance of the
`capacitor and the upper and lower cover layers 112 and 113
`formed on and below the active layerA, respectively, as upper
`and lower margin parts.
`The active layer A may be formed by repeatedly stacking
`the plurality of first and second internal electrodes 121 and
`122, having at least one ofthe dielectric layers 111 interposed
`therebetween.
`
`Meanwhile, in the multilayer ceramic capacitor according
`to the exemplary embodiment ofthe present disclosure, when
`the thickness and the width of the ceramic body 110 are
`defined as T and W, respectively, 0.75WsTs1.25W may be
`satisfied.
`
`10
`
`15
`
`20
`
`25
`
`Acoustic noise may be reduced by controlling the thick-
`ness T and the width W of the ceramic body 110 to satisfy
`0.75WsTs1.25W.
`
`30
`
`35
`
`40
`
`45
`
`50
`
`In the case in which the thickness T of the ceramic body is
`less than 0.75W, target capacitance may not be generated in
`the multilayer ceramic capacitor.
`In the case in which the thickness T of the ceramic body
`110 is greater than l.25W, the multilayer ceramic capacitor
`may be inclined when being mounted on a board, whereby a
`mounting defect may occur.
`Meanwhile, when the gap between the first and second
`external electrodes 131 and 132 is defined as G, 30
`p.msGs0.9W may be satisfied.
`Acoustic noise may be reduced by controlling the gap G
`between the first and second external electrodes 131 and 132
`
`to satisfy 30 p.msGs0.9W.
`In the case in which the gap G between the first and second
`external electrodes 131 and 132 is less than 30 pm, the G
`between the first and second external electrodes 131 and 132
`
`is excessively narrow, such that a short circuit may occur.
`In the case in which the gap G between the first and 20
`second external electrodes 131 and 132 is greater than 0.9W,
`a width ofthe first and second external electrodes 131 and 132
`
`may be reduced to thereby reduce a mounting area when
`being mounted on the board, causing a defect resulting from
`poor adhesive strength.
`Further, when the length and width ofthe ceramic body 1 10
`are defined as L and W, respectively, 0.5LsWsL may be
`satisfied. However,
`the present disclosure is not
`limited
`thereto.
`
`55
`
`60
`
`65
`
`Inductance of the multilayer ceramic capacitor may be
`reduced by controlling the length and the width ofthe ceramic
`body to satisfy 0.5LsWsL.
`Therefore,
`low inductance may be implemented in the
`multilayer ceramic electronic component according to the
`exemplary embodiment of the present disclosure, whereby
`electric performance may be improved.
`Meanwhile, according to the exemplary embodiment ofthe
`present disclosure, the thickness of the lower cover layer 113
`may be 10 pm to 100 pm.
`When the thickness of the lower cover layer 113 is con-
`trolled to be 10 pm to 100 um, acoustic noise may be reduced
`and excellent reliability may be implemented in the multi-
`layer ceramic capacitor.
`000010
`
`000010
`
`

`

`US 9,326,381 B2
`
`7
`In the case in which the thickness of the lower cover layer
`113 is less than 10 um, such an excessively thin cover layer
`may result in the occurrence of a moisture resistance defect.
`In the case in which the thickness of the lower cover layer
`113 is greater than 100 um, acoustic noise may be rapidly
`increased due to displacement of the lower cover layer.
`A thickness of the upper cover layer 112 is not particularly
`limited, and may be equal to or similar to that of the lower
`cover layer 113. The thickness of the upper cover layer 112
`may be within a range preventing the occurrence of the mois-
`ture resistance defect.
`
`FIG. 5 is an enlarged View of part Z of FIG. 4.
`Referring to FIG. 5, the average number of dielectric grains
`111a present in a single dielectric layer 111 in a thickness
`direction thereof may be 2 or greater.
`Acoustic noise may be reduced by controlling the average
`number of dielectric grains 111a present in the single dielec-
`tric layer in the thickness direction thereof to be 2 or greater.
`In the case in which the average number ofdielectric grains
`111a in the single dielectric layer 111 in the thickness direc-
`tion thereof is less than 2, the number of grain boundaries is
`reduced, and when voltage is applied to the internal elec-
`trodes, a displacement of the dielectric layer may be
`increased, resulting in an increase in a displacement of the
`multilayer ceramic capacitor, whereby acoustic noise may be
`increased.
`
`Meanwhile, an average grain size of the dielectric grains
`111a may be 50 nm to 500 nm.
`Acoustic noise may be reduced by controlling the average
`grain size ofthe dielectric grains 111a to be 50 nm to 500 nm.
`In the case in which the average grain size of the dielectric
`grains 111a is less than 50 nm, such an excessively small
`grain size may cause a reduction in permittivity, whereby
`target capacitance of the multilayer ceramic capacitor
`required by a power terminal may not be generated.
`In the case in which the average grain size of the dielectric
`grains 111a is greater than 500 nm, such an excessively large
`grain size may increase a region in which a single dielectric
`grain occupies in a single dielectric layer, whereby acoustic
`noise may be increased.
`A method of measuring the average number of the dielec-
`tric grains 111a in the single dielectric layer in the thickness
`direction thereof and the average grain size of the dielectric
`grains 111a is not particularly limited, but the average num-
`ber and the average grain size of the dielectric grains 111a
`may be measured from an image obtained by scanning a
`cross-section of the ceramic body 110 in the width direction
`thereof using a scanning electron microscope (SEM) as
`shown in FIG. 4.
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`8
`Meanwhile, the first and second external electrodes 131
`and 132 may be extended to portions of the first and second
`main surfaces S1 and S2 of the ceramic body, but are not
`limited thereto.
`
`Hereinafter, a method of manufacturing a multilayer
`ceramic capacitor according to an exemplary embodiment of
`the present disclosure will be described, but is not limited
`thereto.
`
`In the method of manufacturing the multilayer ceramic
`capacitor according to the exemplary embodiment of the
`present disclosure, first, slurry containing powder such as
`barium titanate (BaTiO3) powder, or the like, may be applied
`to carrier films and dried to prepare a plurality of ceramic
`green sheets, thereby forming dielectric layers.
`The ceramic green sheet may be manufactured by mixing
`the ceramic powder, a binder, and a solvent to prepare the
`slurry and forming the prepared slurry as sheets having a
`thickness of several pm by a doctor blade method.
`Next, a conductive paste for internal electrodes may be
`prepared to contain 40 to 50 parts by weight ofnickel powder,
`in which an average particle size ofnickel powder is 0.1 pm to
`0.2 pm.
`After the conductive paste for internal electrodes is applied
`to the green sheets through a screen printing method to form
`internal electrodes, 400 to 500 green sheets on which the
`internal electrodes have been formed may be stacked to form
`an active layer, and then the ceramic green sheets may be
`stacked on and below the active layer to form cover layers,
`thereby forming a ceramic body having first and second main
`surfaces opposing each other, first and second side surfaces
`opposing each other, and first and second end surfaces oppos-
`ing each other.
`Then, first and second extemal electrodes may be formed
`on the first and second side surfaces of the ceramic body.
`Hereafter,
`although the present disclosure will be
`described in detail with reference to Inventive Examples, the
`present inventive concept is not limited thereto.
`
`EXPERIMENTAL EXAMPLE
`
`Multilayer ceramic capacitors according to Inventive
`Examples and Comparative Examples were manufactured as
`follows.
`
`Slurry containing powder such as barium titanate (Ba-
`TiO3), or the like, was applied to carrier films and dried to
`prepare a plurality of ceramic green sheets having a thickness
`of 1.8 um.
`Next, a nickel conductive paste for internal electrodes was
`applied to the ceramic green sheets using a screen to form
`internal electrodes.
`
`For example, as shown in FIG. 4, with respect to any
`dielectric layer randomly selected from an image obtained by
`scanning a cross-section of the ceramic body 10 in width-
`thickness (W-T) directions thereof after being cut in a central
`portion of the ceramic body 10 in the length (L) direction
`thereof, using a scanning electron microscope (SEM), the
`average number of the dielectric grains 111a in the single
`dielectric layer and the average grain size of the dielectric
`grains 1111 may be measured at thirty equidistant points
`thereof.
`
`The thirty equidistant points may be disposed in the active
`layer A, in which the internal electrodes 121 and 122 are
`overlapped with each other.
`The first and second internal electrodes 121 and 122 may
`be spaced part from the first and second end surfaces S3 and
`S4 of the ceramic body 110 by a predetermined distance, but
`are not limited thereto.
`
`About 200 ceramic green sheets were stacked to form a
`multilayer body. Here, the number of ceramic green sheets
`having no internal electrode disposed at a lower portion ofthe
`multilayer body below the stacked ceramic green sheets hav-
`ing the internal electrodes formed thereon was greater than
`the number of ceramic green sheets having no internal elec-
`trode disposed at an upper portion of the multilayer body
`above the stacked ceramic green sheets having the internal
`electrodes formed thereon. Isostatic pressing was performed
`on the multilayer body at 85° C. and 1000 kgf/cm2.
`The pressed ceramic multilayer body was cut into indi-
`vidual chips, and each chip was subjected to a de-binding
`process by being maintained at 230° C. for 60 hours under air
`atmosphere.
`Then, the chip was sintered at l200° C. under reduction
`atmosphere having oxygen partial pressure of l0‘“ atm to
`1040 atm lower than Ni—NiO equilibrium oxygen partial
`000011
`
`55
`
`60
`
`65
`
`000011
`
`

`

`US 9,326,381 B2
`
`9
`pressure so that the internal electrodes were not oxidized.
`After sintering, a size of the multilayer chip capacitor was
`about 1.0 mm><0.5 mm (Length><Width (L><W), 1005 size).
`Here, a manufacturing tolerance was within a range of 10.1
`mm (Length><Width