`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`AVX CORPORATION
`Petitioner
`v.
`
`SAMSUNG ELECTRO-MECHANICS CO., LTD.
`Patent Owner
`_____________________________
`
`Case No. PGR2017-00010
`Patent No. 9,326,381
`_____________________________
`
`
`DECLARATION OF MICHAEL RANDALL
`IN SUPPORT OF PATENT OWNER’S RESPONSE TO PETITION
`
`_____________________________
`
`
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`
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`TABLE OF CONTENTS
`
`Section
`INTRODUCTION
`I.
`II. QUALIFICATIONS AND PRIOR TESTIMONY
`III. MATERIALS CONSIDERED
`IV. BACKGROUND OF THE TECHNOLOGY
`A. Overview
`B. U.S. Patent 9,326,381 (‘381)
`C. U.S. Patent 7,808,770 (Itamura)
`D. U.S. Patent 5,134,540 (Rutt)
`E. U.S. Published Application 2012/0152604 (Ahn)
`V. PATENTABILITY OF THE CHALLENGED CLAIMS OF
`THE ‘381 PATENT
`A. Applicable Legal Principles
`B. Claim Construction
`C. Claim 1: Itamura and Rutt
`D. Claims 3, 4, 6 and 7: Itamura and Rutt
`E. Claim 2: Itamura, Rutt and Jeong
`F. Claims 8, 10, 11, 13-15 and 17-19: Itamura, Rutt and Ahn
`G. Claim 9: Itamura, Rutt, Ahn and Jeong
`H. Claim 16: Itamura, Jeong, Rutt, Ahn and EIA Standard
`VI. CONCLUSION
`
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`Page
`1
`1
`4
`5
`5
`53
`57
`57
`71
`73
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`73
`76
`91
`97
`97
`97
`101
`101
`102
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`I.
`
`INTRODUCTION
`I am a consultant in electronic materials and processing, ceramic
`1.
`
`dielectric materials and processes, passive electronic components, and surface
`
`mount technology, including with respect to ceramic capacitors.
`
`2.
`
`I have been retained in this matter by Samsung Electro-Mechanics Co.,
`
`Ltd. (“SEM”) to provide opinions regarding the instituted grounds of review of the
`
`Petition for Post-Grant Review (the “Petition”) of U.S. Pat. No. 9,326,381 (Ex. 1001,
`
`the “’381 patent”) filed by AVX Corporation (“AVX”).
`
`3.
`
`I am being compensated for my work in this matter. My compensation
`
`in no way depends upon the outcome of this proceeding. I have no financial interest
`
`in SEM or the ’381 patent.
`
`4.
`
`I am not a patent attorney. My understanding of legal principles
`
`regarding patent validity and claim construction is based on information provided to
`
`me by SEM’s counsel, which I have relied on in forming my opinions set forth in
`
`this declaration.
`
`5.
`
`It is my opinion that challenged claims 1–4, 6–11, and 13–19 of the
`
`’381 patent are not rendered obvious based on the instituted grounds.
`
`
`
`II. QUALIFICATIONS AND PRIOR TESTIMONY
`A copy of my curriculum vitae is attached as Exhibit A, and it details
`6.
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`my qualifications and experience, as well as listing my publications and prior
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`testimony. I have been involved in the field of Electronic Materials and Processing,
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`Ceramic Dielectric Materials and Processes, Passive Electronic Components, and
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`Surface Mount Technology, for more than 25 years and have experience in the
`
`design and manufacture of ceramic capacitors, as detailed in my curriculum vitae
`
`(Ex. A). I am an inventor on several patents in these areas.
`
`7.
`
`I earned a Bachelor of Science degree in ceramic engineering from the
`
`NYSCC at Alfred University, Alfred NY in 1985. I earned a Master of Science
`
`degree in Materials Science and Engineering from the University of Florida,
`
`Gainesville, FL in 1987. I earned a Ph.D. in Materials Science and Engineering
`
`from the University of Florida in 1993 as well. I earned a Master of Business
`
`Administration from Webster University in 1995.
`
`8.
`
`From 1992 to 1997, I was employed by AVX Corporation. My
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`positions at AVX Corporation included Manager of Ceramic Capacitor Research
`
`and Development, during which I was responsible for planning and oversight of
`
`multi-layered ceramic capacitor and materials development.
`
`9.
`
`From 1997 to 1999, I was employed by Ferro Corporation. My
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`positions at Ferro Corporation included Director of Research and Development,
`
`during which I was responsible for planning, direction, and oversight of division
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`level research and development, and new product development, including Low
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`Temperature Cofired Ceramic Systems and Multilayer Materials Systems.
`
`10. From 1999 to 2008, I was employed by KEMET Electronics. My
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`positions at KEMET Electronics included Director of Ceramic Technology, during
`
`which I was responsible for the direction of teams providing technology solutions
`
`for multilayer ceramic capacitor development needs. My positions at KEMET also
`
`included Director of Ceramic Technical Marketing and New Business
`
`Development, during which I was responsible for identification and management
`
`of ceramic capacitor technical marketing, including multilayer ceramic capacitors,
`
`and associated product lines. My positions at KEMET also included Director of
`
`Advanced Ceramic Technology, during which I was responsible for new product
`
`development for advanced ceramic products, including various capacitor types, and
`
`resulting in several inventions.
`
`11. Since 2003, I have been an independent consultant with Almegacy
`
`LLC in a variety of electronic device and material projects, including electronic
`
`component selection and sourcing for capacitors. I have served as an expert
`
`witness in the subject area of capacitors, including matters before the United States
`
`District Court, including the Central District of California, the Southern District of
`
`California, the Eastern District of Texas, and the Eastern District of NY. I have
`
`also served as an expert witness in the subject area of capacitors and electronic
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`components before the International Trade Commission. And I have served as an
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`expert witness in the subject area of capacitors for matters considered by the
`
`United States Patent and Trademark Office regarding nine different patents.
`
`12. This report and my opinions are based upon my own qualifications
`
`and experience and my personal knowledge.
`
`
`
`III. MATERIALS CONSIDERED
`13. In forming my opinions, I considered the Petition and its associated
`
`exhibits (including the ’381 patent (Ex. 1001), its file history (Ex. 1002), the cited
`
`prior art, and its attached declarations (see the List of Documents Reviewed, the List
`
`of Exhibits, as well as this Report)), as well as SEM’s preliminary response and its
`
`exhibits (see the List of Documents Reviewed, the List of Exhibits, as well as this
`
`Report)), as well as the Patent Trial and Appeals Board (“Board”)’s institution
`
`decision and any other exhibits or literature cited in this declaration or cited in the
`
`associated List of Exhibits or List of Documents Reviewed. My opinions are based
`
`upon my education, my related research and experience, as well as my investigation
`
`and the study of relevant materials. I may rely upon these materials and/or additional
`
`materials to counter arguments raised by the Petitioner. I may also consider
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`additional information and documents, including information and documents that
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`may not yet have been provided to me, in forming any necessary opinions.
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`14. My analysis of relevant materials produced is ongoing and I will
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`continue to review any new material as it is provided. This declaration represents
`
`only those opinions I have formed to date. I reserve the right to revise, supplement,
`
`and/or amend my opinions stated herein based on new information and on my
`
`continuing analysis of the materials already provided or on new materials provided.
`
`
`
`IV. BACKGROUND OF THE TECHNOLOGY
`A. Overview
`
`15.
`
`I have been informed by counsel that during a post-grant review, the
`
`Board construes claim terms according to their broadest reasonable construction in
`
`light of the specification of the patent in which they appear. (37 C.F.R. § 42.200(b)).
`
`Taking this into consideration, it is my opinion that the scope of background
`
`technology of the ‘381 patent includes certain types of multilayer ceramic capacitors.
`
`16. The ‘381 patent relates to a multilayer ceramic capacitor and a board
`
`having the same mounted thereon. (‘381 at 1:15-16). The ‘381 patent does not
`
`mention varistors, or thermistors, such as PTCR (positive temperature coefficient of
`
`resistance) thermistors, and those are outside the scope of the ‘381 patent.
`
`Additionally, one skilled in the art would have understood that the scope of the
`
`technology related to the ‘381 patent does not include all capacitors.
`
`17. To explain, there are numerous types of capacitors. The primary major
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`discriminator between capacitors is whether they are electrostatic or electrolytic.
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`Electrolytic capacitors utilize an electrolyte to facilitate charge transfer and are not
`
`within the scope of the ‘381 patent. A person of skill in the art (POSITA) would
`
`have understood that the ‘381 patent does not pertain to electrolytic capacitors. A
`
`POSITA also would have understood that the ‘381 pertains only to a specific type
`
`of electrostatic capacitors.
`
`18. To explain, electrostatic capacitors utilize solid state conductors (e.g.,
`
`metal electrodes) as a means to facilitate charge (e.g., electron) transfer. A POSITA
`
`further would have understood that a subset of electrostatic capacitors is multilayer
`
`capacitors, and that traditional single layer capacitors are also excluded from the
`
`scope of the subject matter of the ‘381 patent as they have a different electrode
`
`configuration than multilayer ceramic capacitors.
`
`19. Additionally a POSITA would have understood that the ‘381 patent
`
`does not pertain to all multilayer capacitors. For example, a POSITA would have
`
`understood that multilayer capacitors that are made from non-ceramic dielectric
`
`materials, such as organic film capacitors, and the like, are outside the scope of the
`
`‘381 patent.
`
`20. A POSITA further would have understood that the scope of the art of
`
`the ‘381 patent includes only certain ceramic dielectric materials, but not all ceramic
`
`dielectric materials, as an objective of the ‘381 patent is to reduce or minimize
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`acoustic noise (‘381 at 9:9-13:23). Since acoustic noise is insignificant for many
`
`types of dielectric ceramics (e.g., non-ferroelectric dielectrics, such as linear
`
`dielectrics or Class 1 dielectrics, as well as intergranular barrier layer capacitors
`
`(IBLC) materials, which utilize a ceramic material that is comprised of
`
`semiconducting grains between insulating barriers at each grain boundary), a
`
`POSITA would have understood that the scope of the subject matter of the ‘381
`
`patent is limited to multilayer ceramic capacitors that are made with ceramic
`
`dielectric materials that are ferroelectric or that otherwise exhibit electrostrictive or
`
`piezoelectric characteristics or characteristics that cause displacement of the
`
`dimensions of the dielectric material when said material is placed under an electric
`
`field as discussed below. Thus, a POSITA would have understood that the ‘381
`
`patent pertains not to multilayer ceramic capacitors comprised of linear ceramic
`
`dielectric materials, and not to multilayer ceramic capacitors comprised of
`
`intergranular barrier layer materials (IBLC). A POSITA would also have understood
`
`that the ‘381 patent pertains only to multilayer ceramic capacitors comprised of
`
`ferroelectric ceramic dielectrics, or other ceramic dielectric materials that exhibit
`
`significant mechanical displacement when said material is placed under an electric
`
`field as discussed below.
`
`21. A POSITA also would have understood that the ‘381 patent pertains to
`
`“reverse geometry” multilayer ceramic capacitors (MLCC). The term “reverse
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`geometry” refers to a reversal in the length (L) and width (W) dimensions of the
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`MLCC (e.g., reversal of length and width dimensions from 1206 (0.126”L x
`
`0.63”W) to 0612 (0.063”L x 0.126”W)) as illustrated below. The reverse geometry
`
`of the MLCC device results in internal electrodes that are wider and shorter than the
`
`internal electrodes of a traditional MLCC since conductors that have increased cross
`
`sectional area, combined with shorter current path length exhibit reduced inductance
`
`or ESL. Thus, the reverse geometry configuration exhibits reduced inductance or
`
`reduced equivalent series inductance (ESL) compared to a standard MLCC of the
`
`same peripheral size. For example, the inductance of a standard MLCC has been
`
`measured to be approximately double (1250 pH) that of a reverse geometry MLCC
`
`(610 pH) when comparing traditional 1206 MLCCs to reverse geometry 0612
`
`MLCCs.1
`
`Standard MLCC vs. Reverse Geometry MLCC2
`
`
`
`1 Ex. B: J. Cain, “Parasitic Inductance of Multilayer Ceramic Capacitors,” AVX Technical Information, p. 4/4, June
`1997. https://www.avx.com/docs/techinfo/CeramicCapacitors/parasitc.pdf
`2 Source: Vishay, Capacitors-Ceramic-Surface Mount: https://www.vishay.com/capacitors/ceramic/surface-mount/,
`Source: Digi-Key Electronics, Product Index-Capacitors-Ceramic Capacitors- AVX Corporation
`06125C104MAT2A: https://www.digikey.com/product-detail/en/avx-corporation/06125C104MAT2A/478-2901-1-
`ND/776677
`
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`22. Reduced inductance in an MLCC is generally preferable for increased
`
`frequency applications (e.g., ca. 100 KHz and above) as relatively low inductance
`
`reduces device impedance as described below. Simply put, impedance in alternating
`
`current (AC) circuits is analogous to resistance for direct current (DC) circuits.
`
`Reduced impedance in AC circuits results in less power loss in transmission
`
`(generally preferable), which aids in the performance of myriad applications such as
`
`high speed decoupling and the like. Realizing this, the inventors on the ‘381 patent
`
`embraced the objective of creating a low inductance MLCC device, having high
`
`capacitance density and low acoustic noise emission as explained herein. They also
`
`embraced the objective of designing the accompanying circuit board, to which said
`
`devices would be mounted, such that the benefits of low inductance and low acoustic
`
`noise emission exhibited by the MLCC device(s) are not sacrificed, but remain
`
`improved or are further improved.
`
`23. The ‘381 patent mentions inductance or equivalent series inductance
`
`(ESL) at least 10 separate times:
`
`1. “In the case of a multilayer ceramic capacitor, as equivalent
`series inductance (hereinafter referred to as “ESL”) increases,
`performance of an electronic product may deteriorate.” (Id. at
`1:22-25).
`2. “In addition, in a case in which an electronic component is
`miniaturized and capacitance thereof is increased, the influence
`of an increase in ESL on deterioration in performance of the
`electronic product has relatively increased.” (Id. at 1:25-28).
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`3. “A so-called "low inductance chip capacitor (LICC)" is to
`decrease inductance by decreasing a distance between external
`terminals to shorten a current flow path.” (Id. at 1:29-31).
`4. “Since the distance between the first and second external
`electrodes 131 and 132 is shortened, the current path may be
`shortened, resulting in a reduction in inductance.” (Id. at 6:1-3).
`5. “The first and second internal electrodes 121 and 122 are
`alternately exposed to the first or second side surface S5 or S6,
`such that a reverse geometry capacitor (RGC) or low inductance
`chip capacitor (LICC) may be obtained as described below.” (Id.
`at 5:17-21).
`6. “In this case, when an alternative current (AC) voltage is applied
`to the external electrodes, a current path is relatively long,
`whereby an intensity of an induced magnetic field may be
`increased, resulting in an increase in inductance.” (Id. at 5:25-
`30).
`7. “In this case, since a distance between the first and second
`external electrodes 131 and 132 is relatively short, the current
`path may be reduced, resulting in a reduction in inductance.” (Id.
`at 5:35-40).
`8. “As described above, the multilayer ceramic capacitor, in which
`the first and second external electrodes 132 are formed on the
`first and second side surfaces 5 and 6 of the ceramic body 110,
`may be a reverse geometry capacitor (RGC), or low inductance
`chip capacitor (LICC).” (Id. at 6:4-9).
`9. “Inductance of the multilayer ceramic capacitor may be reduced
`by controlling the length and the width of the ceramic body to
`satisfy 0.5L≤W≤L.” (Id. at 6:54-56).
`10. “Therefore, low inductance may be implemented in the
`multilayer ceramic electronic component according to the
`exemplary embodiment of the present disclosure, whereby
`electric performance may be improved.” (Id. at 6:54-56).
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`24. Thus, a POSITA would have understood that low inductance or ESL is
`
`a key objective of the ‘381 patent. Inductance (L or ESL) of a capacitor device
`
`contributes to the impedance (Z) of said device through the relation:
`
`
`
`where:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Z is impedance in Ohms (Ω)
`ESR is equivalent series resistance in Ohms (Ω)
`XL is inductive reactance = 2πfL in Ohms (Ω)
`XC is capacitive reactance = (1/(2πfC)) in ohms (Ω)
`f is frequency in Hertz (H)
`L is inductance in Henries (H)
`C is capacitance in Farad (F)
`
`
`25. Additionally, the self-resonance frequency of a capacitor occurs
`
`where the capacitive and inductive reactances are equal, and is determined through
`
`the relation:
`
`
`
`Fr is self-resonance frequency (SRF) in Hertz (Hz)
`L is equivalent series inductance (ESL) in Henry (H)
`C is capacitance in Farads (F)
`
`where:
`
`
`
`
`
`
`
`
`26. Above the self-resonance frequency (Fr), the inductive reactance of
`
`the capacitor device (2πfL) dominates the capacitive reactance, and the inductance
`
`Z
`
`
`
`ESR
`
`2
`
`
`
`(
`
`X
`
`L X
`
`
`C
`
`2
`
`)
`
`Fr
`
`
`
`1
`LC
`
`2
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`or ESL (equivalent series inductance) of the device, becomes the dominant factor
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`in determining impedance (Z).
`
`27. Low ESL (inductance) is important in applications that require low
`
`impedance (Z), such as decoupling, and the like, as discussed herein. In these
`
`applications low inductance results in low impedance, thus reducing “voltage
`
`droop” thereby improving signal integrity, etc., such that signals sent to each
`
`switching element in, for example, an integrated circuit (IC), are proper and are not
`
`significantly compromised by said “voltage droop,” or the like. Thus switching
`
`errors are avoided as illustrated below.
`
`
`Switching with Low and High Inductance MLCC for Decoupling
`
`Switching Signals
`•
`Ideal
`•
`Relatively Low Inductance
`•
`Relatively High Inductance
`
`Required
`Switching
`Duration
`Minimum
`Switching
`Voltage
`(Threshold)
`
`Voltage +
`
`Signal
`
`Time +
`
`•
`
`The Signal Voltage must Exceed The Switching Threshold for The
`Required Duration in Order for the Switching Element to Properly to
`Switch
`•
`An Ideal Signal Voltage is Shown, Resulting in No Switching Errors
`• Using Low Inductance MLCC, a Good (Usable) Voltage Signal is
`Achieved and No Switching Errors Occur
`• Using MLCC With Too High of an Inductance Results in Switching
`Errors as Switching Threshold and/or Duration are insufficient
`
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`28. An impedance (Z) versus frequency (f) curve of a low inductance
`
`MLCC versus a standard MLCC is shown below in order to illustrate this effect.
`
`Therefore, achieving a low inductance MLCC device is an important objective of
`
`the ‘381 patent.
`
`
`Impedance versus Frequency for Standard MLCC Compared to Low Inductance
`MLCC (LICC)
`
`
`
`
`
`
`
`Low Inductance Enables Reduced Impedance at
`Frequencies Above Resonance
`
`Standard MLCC:
`L=1250 pH
`C=1μF
`ESR=2mΩ
`
`Low Inductance
`LICC (RGC):
`L=610 pH
`C=1μF
`ESR=2mΩ
`
`Z (Ω) vs. Frequency (Hz)
`
`1.E+01
`
`1.E+00
`
`1.E-01
`
`1.E-02
`
`Impedance (Ω)
`
`1.E+08
`
`1.E+07
`
`1.E+06
`
`Frequency (Hz)
`
`Cap (µF) 1.0
`
`Cap (µF) 1
`
`1.E+05
`
`1.E-03
`
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`29. Further, the inventors of the ‘381 patent realized that it is necessary but
`
`insufficient, when pursuing low inductance circuits, that the MLCC device of
`
`interest have low inductance. Since the low ESL device is connected to the circuit
`
`in a series configuration (i.e., a first connection to a first polarity and a second
`
`connection to a second polarity, which results in at least 3 parasitic inductances as
`
`illustrated below), it is important that the connections of the MLCC device to the
`
`circuit board or printed circuit board (PCB) also have low inductance, so that the
`
`entire configuration has relatively low inductance or ESL.
`
`Inductance of a Mounted MLCC (adapted from Ahn)
`
`
`
`Mount Inductance
`
`Mount Inductance
`
`Device Inductance
`
`Current is Injected/Ejected
`
`Inductances add together when device is connected in series (always for capacitor as it only
`works when polarity at each terminal is relatively opposite to the other terminal), in this case:
`ESLMounted = ESLMLCC + 2ESLMOUNT
`
`Inductance of each of the solder connections (2 or more) depends upon the relative cross-
`sectional area of the connection in combination with the length of the connection
`• Short, wide, high (large cross sectional area) exhibit lower inductance
`•
`Long, narrow, short (small cross-sectional area) exhibit higher inductance
`
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`30. Additionally inductance or ESL has two components:
`
`1. Self-inductance: the inductance of a conductor that is due to the
`magnetic field that is generated due to current flowing through
`the conductor itself.
`2. Mutual inductance: the inductance imposed on a conductor that
`is due to the magnetic field that is generated by current flowing
`through a neighboring conductor.
`
`
`These two inductance components combine to provide an overall inductance that a
`
`conductor or component exhibits. Self-inductance is explained above, and is due to
`
`the magnetic field that develops clockwise with respect to the direction of current
`
`flow (i.e., the “Right Hand Rule”). Mutual inductance is the inductance that is
`
`impressed upon a given conductor by the magnetic field(s) of neighboring
`
`conductors. When the current in neighboring conductor(s) flows in the same
`
`direction as the current in the subject conductor, the magnetic fields are also in the
`
`same direction and combine to increase inductance as described and illustrated
`
`herein. When the current in the neighboring conductor(s) flows in the opposite
`
`direction of the conductor of interest, the magnetic fields run in counter directions
`
`and the net magnetic field is reduced, thereby reducing the overall inductance of the
`
`subject conductor.
`
`31. Subsequently, when the current flow in a conductor of interest ceases
`
`or reverses direction, the energy stored in said magnetic field (that is due either to
`
`self-inductance or to the net combination of self and mutual inductances), resists said
`
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`change in current flow, which effectively slows down these current changes and
`
`results in “voltage droop” in the associated circuit. Thus, in inductive circuits, the
`
`current change lags the voltage change. This lag can result in highly undesirable
`
`events, such as erroneous switching events in active circuits, such as for example if
`
`a switching element in an integrated circuit (IC) does not switch when it is supposed
`
`to due to this “voltage droop” (i.e., due to insufficient switching voltage in the signal
`
`to the IC, as described above, or the like). These undesirable events occur, for
`
`example, when the associated capacitor has unacceptably high inductance (ESL) for
`
`the switching speed requirements of the circuit associated with said decoupling
`
`application. Thus, in these types of applications, lower inductance (ESL) is required
`
`and high inductance (ESL) is not acceptable. Realizing this, the inventors on the
`
`‘381 patent embraced the objective of creating a low inductance MLCC device,
`
`having high capacitance density and low acoustic noise emission as explained
`
`herein. They also embraced the objective of designing the accompanying circuit
`
`board, to which said devices would be mounted, such that the benefits of low
`
`inductance and low acoustic noise emission exhibited by the MLCC device(s) are
`
`not sacrificed, but are further improved.
`
`32.
`
`In a “nutshell,” wide, thick, short conductors exhibit relatively low self-
`
`inductance, while narrow, thin, long conductors exhibit relatively high self-
`
`inductance. As discussed above, when two closely placed conductors conduct
`
`Exhibit 2008
`PRG2017-00010
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`
`
`
`electrical current in the same direction, the effect of mutual inductance of one
`
`conductor upon the other conductor is to increase the inductance of the other
`
`conductor. And when two closely placed conductors conduct electrical current in
`
`the opposite direction, the effect of mutual inductance of one conductor upon the
`
`other conductor is to decrease the inductance of the other conductor; the latter is used
`
`by designers and engineers, etc., to reduce inductance of ceramic capacitors by using
`
`interdigitated electrode design MLCCs, for example, as illustrated below.
`
`Mutual Inductance: Effect on Overall Inductance
`
`
`
`
`Exhibit 2008
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`
`
`33.
`
` These same phenomena work with electrode pads or mounting pads
`
`and associated circuitry on circuit boards (PCBs) as well. Thus, placing mounting
`
`pads of the same polarity, that conduct current in the same direction into or out of a
`
`mounted component such as an MLCC, will increase the mutual component of
`
`inductance and thus the overall inductance of the mounted MLCC. A POSITA
`
`would have understood that use of this configuration works against the objective of
`
`achieving low overall inductance. Further, a POSITA would have understood that
`
`use of a plurality of spaced mounting pads and associated solder attach on a circuit
`
`board where said pads are much narrower, and/or said solder is thinner in height than
`
`a single, full width mounting pad for a terminal of the component will increase the
`
`self-inductance of each of the solder mounts between the PCB and the component
`
`(MLCC in this case). If this increase in inductance, as well as the increase in mutual
`
`inductance as described above, is not overcome by the parallel nature of the mounts,
`
`the overall inductance of the mounted component configuration will increase. Again
`
`this works against the objective of the ’381 patent of achieving low overall
`
`inductance of the mounted component.
`
`34. Thus, a POSITA would have understood that prior art that discloses
`
`narrower, thinner, multiple electrode pads or circuit traces per terminal mount,
`
`and/or that discloses thinner associated solder mount material height, and/or that are
`
`closely spaced and flow current in the same direction all work against the objectives
`
`Exhibit 2008
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`Page 20 of 298
`
`
`
`of the ‘381 patent (i.e., a low inductance MLCC device, having high capacitance
`
`density and low acoustic noise emission, and an accompanying circuit board, to
`
`which said devices mount, that minimizes any additional inductance or noise
`
`emission of the overall mounted configuration). Thus, a POSITA would have been
`
`dissuaded from using multiple, narrow mounting pads for one MLCC external
`
`electrode, as taught by United States Published Patent Application US2012/0152604
`
`(Ahn) for example, as discussed in further detail below. And thus, a POSITA would
`
`have also been dissuaded from using relatively thin solder mount material between
`
`the mounted MLCC and the electrode mounting pad as is also taught in (Ahn) for
`
`example.
`
`35. The inventors of the ‘381 patent also had the objective of reducing or
`
`minimizing acoustic noise emission of the subject MLCCs. To explain, certain
`
`dielectric materials physically distort when they are placed within an electric field.
`
`This phenomenon is due to the crystal chemistry of the dielectric comprising the
`
`MLCC as explained below, and is significant in ferroelectric type or similar type
`
`ceramic dielectrics that are used as the dielectric material in high capacitance density
`
`MLCCs, such as the subject MLCC devices of the ‘381 patent.
`
`36. To explain, a major driving factor for the design of certain MLCCs
`
`(those that pertain to the ‘381 patent) is the amount of capacitance provided by the
`
`device, as well as the amount of capacitance exhibited by a given volume (unit
`
`Exhibit 2008
`PRG2017-00010
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`Page 21 of 298
`
`
`
`volume), called “C/V” and also known as the capacitance density of said capacitor
`
`device. A POSITA would have understood that, for these applications, it is
`
`important to maximize C/V in the subject MLCCs of the ‘381 patent. In an MLCC,
`
`the capacitance is determined by the relation:
`
`
`
`
`
`
`
`
`
`
`where:
`C is capacitance in Farads (F)
`
`n is the number of actives within the MLCC device
`
`
`ε0 is the dielectric permittivity of free space (8.854 x 10-12 F/m)
`ε’ is the dielectric constant of the material comprising the actives
`
`t is the thickness of each dielectric layer comprising the actives (m)
`
`
`37.
`
`In order to simplify the math, the device construction of the MLCC
`
`device of interest is often simplified such the MLCC is defined to be marginless, and
`
`to have no cover layer volume, and to have no internal or external electrode volume.
`
`With these simplifications in place, the volume of the MLCC (i.e., the length x the
`
`width x the thickness) may be defined as:
`
`
`
`where:
`V is the volume of the MLCC (m3)
`L is the length of the MLCC (m)
`W is the width of the MLCC (m)
`T is the thickness of the MLCC (T = n x t)
`A is the area of each of the marginless active(s) (A = L x W), (m2)
`n is the number of actives within the MLCC device
`t is the thickness of each dielectric layer comprising the actives (m)
`
`
`
`
`
`A
`
`nC
`'
`0
`t
`
`
`
`V
`
`
`
`LWT
`
`
`
`nAt
`
`Exhibit 2008
`PRG2017-00010
`SEM
`Page 22 of 298
`
`
`
`
`
`38. Using the above simplification, volumetric efficiency or capacitance
`
`density is equal to the capacitance divided by the volume (C/V). And using the above
`
`simplification leads to the relation:
`
`
`
`39. Thus, a POSITA would have understood that, in order to maximize
`
`capacitance density, it is important to maximize ε’ (the dielectric constant) as well
`
`as to minimize t (dielectric thickness), which not only increases C, but allows for
`
`higher n, thus leading to the effect that C/V increases proportionally to the inverse
`
`of the square of the dielectric thickness (t). For example, a POSITA would have
`
`understood that if dielectric thickness can be reduced by a factor of 10, capacitance
`
`density may be increased by as much as a factor of 100. A POSITA would have
`
`understood these factors and would understand that a major driving force in the
`
`MLCC industry is (and has been) to maximize C/V by increasing ε’ and by
`
`decreasing t, thereby enabling increased n as well.
`
`40. Subsequently, considerable effort has been devoted to developing
`
`dielectric ceramic materials that exhibit increased dielectric constant (ε’) and that
`
`are capable of enabling very thin dielectric layers in MLCCs. Ferroelectric
`
`materials, typically comprised of formulations that include barium titanate (BaTiO3
`
`or BT) are, by far, the material of choice for these applications since the crystal
`
`nVC
`A
`'
`
`/
`0
`2
`nAt
`
`
`
`
`
`'
`
`0
`2
`t
`
`
`
`1
`2
`t
`
`Exhibit 2008
`PRG2017-00010
`SEM
`Page 23 of 298
`
`
`
`structure of BT enables very high values of ε’. Said formulations are optimized to
`
`provide acceptably and stable ε’ over a broad range of temperature. For example,
`
`an X5R dielectric is designated as a Class 2 dielectric (ferroelectric or similar) that
`
`exhibits a relatively high ε’ over the temperature range from -55C to +85C. In this
`
`example ε’ cannot deviate more than +/-15% from the room temperature (RT) value
`
`of ε’ over the temperature range from -55oC to +85oC and still achieve the X5R
`
`classification. Using BT, X5Rs exhibiting ε’ values exceeding 3,000-5,000 may be
`
`achieved. This enables an in
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