Third Party Submission for Application USSN 14/259,011
`
`Patent No.:
`
`Inventor:
`
`Application No.:
`
`Filed:
`
`Document1
`
`US Patent 8,238,116
`
`Eggerding etal.
`
`12/061 ,150
`
`April 2, 2008
`
`Application Publication Date:
`Issue Date:
`
`October 16, 2008
`August 7, 2012
`
`Concise Description:
`Document 1 was published as an application and as a patentpriorto the earliest
`
`possible priority date of June 14, 2013 for the subject Application USSN 14/259,011.
`The subject Application USSN 14/259,011 is entitled "Multilayer Ceramic
`
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`
`a particular capacitor arrangementwhichresults in a reverse geometry capacitor having
`
`relatively low inductance.
`
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`132
`
`\
`
`121
`|22-—~>
`
`131
`
`(
`
`Z
`
`\
`LA,
`
`
`
`112
`
`
`
`
`111
`
`LIAF LLLLeshel
`
`FIG. 4
`hore
`°
`
`Exhibit 2001
`PGR2017-00010
`SEM
`Page 1 of 48
`
`Page 1 of 48
`
`
`
`Patent No.:
`
`Inventor:
`
`Application No.:
`
`Filed:
`
`Document1
`
`US Patent 8,238,116
`
`Eggerding etal.
`
`12/061 ,150
`
`April 2, 2008
`
`Application Publication Date:
`Issue Date:
`
`October 16, 2008
`August 7, 2012
`
`Concise Description:
`Document 1 was published as an application and as a patentpriorto the earliest
`
`possible priority date of June 14, 2013 for the subject Application USSN 14/259,011.
`The subject Application USSN 14/259,011 is entitled "Multilayer Ceramic
`
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`
`a particular capacitor arrangementwhichresults in a reverse geometry capacitor having
`
`relatively low inductance.
`
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`132
`
`\
`
`121
`|22-—~>
`
`131
`
`(
`
`Z
`
`\
`LA,
`
`
`
`112
`
`
`
`
`111
`
`LIAF LLLLeshel
`
`FIG. 4
`hore
`°
`
`Exhibit 2001
`PGR2017-00010
`SEM
`Page 1 of 48
`
`Page 1 of 48
`
`
`
`Examples from the specification of the subject Application USSN 14/259,011
`regarding such reverse geometry feature arrangement and resulting relatively low
`inductance are recited below re application Paragraphs [0050], and [0056] through
`
`[0061] (emphasis added):
`
`[0050] Referring to FIG. 1, in the multilayer ceramic capacitor according to
`an exemplary embodimentof the present disclosure,a ‘length direction’
`refers to an 'L' direction, a ‘width direction’ refers to a 'W' direction, and a
`‘thickness direction’ refers to a 'T' direction. Here, the ‘thickness direction’
`may be the sameasa stacking direction in which dielectric layers are
`stacked.
`
`[0056] Thefirst and secondinternal electrodes 121 and 122 may be
`disposed to face each other, having at least one of the dielectric layers
`111 interposed therebetween, and maybealternately exposedto thefirst
`or second side surface S5 or S6.
`
`[0057] Thefirst and secondinternal electrodes 121 and 122 are
`alternately exposed tothefirst or second side surface S5 or S6, such that
`a reverse geometry capacitor (RGC) or low inductance chip capacitor
`(LICC) may be obtained as described below.
`
`[0058] In a general multilayer ceramic electronic component, external
`electrodes may be disposed on opposing end surfaces of the ceramic
`bodyin a length direction thereof.
`
`[0059] In this case, when analternative current (AC) voltage is applied to
`the external electrodes, a current path is relatively long, whereby an
`intensity of an induced magnetic field may be increased, resulting in an
`increasein inductance.
`
`[0060] In order to solve this problem, the first and second external
`electrodes 131 and 132 in the exemplary embodimentof the present
`disclosure may be disposedon thefirst and second side surfaces S5 and
`S6 of the ceramic body 110 opposing each other in the width direction so
`as to reduce the current path.
`
`20f6
`
`Page 2 of 48
`
`Page 2 of 48
`
`
`
`[0061] In this case, since a distance betweenthefirst and second
`external electrodes 131 and 132 is relatively short, the current path
`may be reduced, ... resulting ina reduction in inductance.
`
`Further exemplary information from the specification of the subject Application
`
`USSN 14/259,011 relates to dielectric grain subject matter, as recited below re
`
`application Paragraphs [0087] and [0088] (emphasis added):
`
`[0087] FIG. 5 is an enlarged view of part Z of FIG. 4.
`
`[0088] Referring to FIG. 5, the average numberofdielectric grains 111a
`presentin a single dielectric layer 111 in a thickness direction thereof may
`be 2 or greater.
`
`Such Fig.5 of the USSN 14/259,011 is reproduced below:
`
`
`
`Claim 1 of the subject Application USSN 14/259,011 relates to multilayered
`
`ceramic capacitor subject matter, and recites in pertinent part (bracketed comments
`
`added):
`
`1. A multilayer ceramic capacitor, comprising:
`a ceramic body [110] including dielectric layers [111] and havingfirst
`and second main surfaces [$1, S2] opposing each other,first and second
`
`3 of 6
`
`Page 3 of 48
`
`Page 3 of 48
`
`
`
`side surfaces [S5, S6] opposing each other, andfirst and second end
`surfaces [S3, S4] opposing each other;
`an active layer including a plurality of first and secondinternal
`electrodes [121, 122] disposed to face each otherwith at least one of the
`dielectric layers interposed therebetween andalternately exposed to the
`first or second side surface;
`upper and lowercoverlayers [112, 113] disposed on and below the
`active layer, respectively; and
`a first external electrode [131] disposed on thefirst side surface [S3] of
`the ceramic body and electrically connectedto the first internal electrodes
`[121] and a second external electrode [132] disposed on the secondside
`surface [S4] and electrically connected to the secondinternal electrodes
`[122],
`wherein whena thickness of the ceramic bodyis defined as T anda
`width thereof is defined as W, 0.75W.lItoreq.T.Itoreq.1.25W is satisfied,
`when a gap between thefirst and second external electrodesis
`defined as G, 30 .mu.m.ltoreq.G.ltoreq.0.9W is satisfied {Fig. 4], and
`an average numberofdielectric grains in a single dielectric layer in a
`thickness direction thereof is 2 or greater[Fig. 5].
`
`Independentclaim 8 relates to a printed circuit board having at least two
`electrode pads, and such a multilayer ceramic capacitor mounted and soldered thereon.
`Document 1 (D1) is entitled "Land Grid Feedthrough Low ESL Technology,” and
`discloses subject matter pertinent to the subject Application USSN 14/259,011. See, for
`example, D1, Fig. 4a reproduced below and showing a reverse geometry multi-layer
`capacitor 400 mounted via traces 442 and 444 onprinted circuit board 420:
`
`
`
`4o0f6
`
`Page 4 of 48
`
`Page 4 of 48
`
`
`
`Further, the D1 specification refers to reducing inductance in the context of both
`reverse geometry capacitors and low aspectratio (length to width ratio). Both such
`features are pertinent to the subject Application USSN 14/259,011. See, for example,
`
`D1, specification Col. 1, lines 33-67 (emphasis added):
`
`There may be several strategies for reducing equivalent series
`inductance, or ESL, of chip capacitors compared to standard multilayer
`chip capacitors. ... A first exemplary strategy for reducing ESL
`involves reverse geometry termination, such as employedin low
`inductance chip capacitor (LICC) designs. In such LICCs, electrodes
`are terminated on the long side of a chip instead of the short side.
`Since the total inductance of a chip capacitor is determinedin part
`by its length to width ratio, LICC reverse geometry termination
`results ina reduction in inductance by as muchasa factorof six from
`conventional MLC chips.
`
`Interdigitated capacitors (IDCs) incorporate anotherstrategy for reducing
`capacitor inductance [by] having a main portion and multiple tab portions
`that connect to respective terminations formed on the capacitor periphery.
`
`A still further technology utilized for reduction in capacitor inductance
`involves [a] low inductance chip array (LICA) product, [which] achieves
`low inductance values by low aspectratio of the electrodes....
`
`Anotheraspect of D1 disclosesthe relationship between the gap betweena pair
`
`of external electrodes (which creates a current path or loop) and the resulting
`
`inductance of such arrangement. See, D1, Fig. 2, per below andits related description:
`
`"FIG. 2 provides a graphical comparison of general inductancetrends for low
`
`inductance MLCC components especially depicting lumped ESL values versus
`
`cancellation loop width for multiple exemplary LGA capacitor embodiments ofdiffering
`
`sizes;..."
`
`5of6
`
`Page 5 of 48
`
`Page 5 of 48
`
`
`
`Measured ESL for 1206 Extended Land MLCC and LGA
`Capacitors vs Terminal Gap
`
`Lumped
`
`1000 +
`
`ESL(pH)
`
`Terminal Gap (mm)
`ESL-LGA
`a
`
`+
`
`ESL-MLCx
`
`FIG. 2
`
`Thus, per the foregoing, at least the exemplary above-indicated disclosure of
`
`Document 1 subject matter as relates to lowering inductance for a multilayer ceramic
`
`capacitor is pertinent to the subject Application USSN 14/259,011.
`
`6 of 6
`
`Page 6 of 48
`
`Page 6 of 48
`
`
`
`Third Party Submission for Application USSN 14/259,011
`
`Patent No.:
`
`Inventor:
`
`Application No.:
`Filed:
`
`Document 2
`
`US Patent 7,414,857
`
`Ritter et al.
`
`11/588, 104
`October 26, 2006
`
`Application Publication Date:
`Issue Date:
`
`May 3, 2007
`August 19, 2008
`
`Concise Description:
`Document2 was published as a patentprior to the earliest possible priority date
`of June 14, 2013 for the subject Application USSN 14/259,011.
`The subject Application USSN 14/259,011 is entitled "Multilayer Ceramic
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`a particular capacitor arrangement which results in a reverse geometry capacitor having
`
`relatively low inductance.
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`
`
`rreee
`PLLLoghiaghaghahdZhLononlELaborrhorrmaeCorrbormbmbecodhy
`wtPF
`
`S
`
`:
`
`Page 7 of 48
`
`Page 7 of 48
`
`
`
`Examples from the specification of the subject Application USSN 14/259,011
`regarding such reverse geometry feature arrangement and resulting relatively low
`inductanceare recited below re application Paragraphs [0050], and [0056] through
`
`[0061] (emphasis added):
`
`[0050] Referring to FIG.1, in the multilayer ceramic capacitor according to
`an exemplary embodimentof the present disclosure, a ‘length direction’
`refers to an 'L' direction, a ‘width direction’ refers to a 'W' direction, and a
`‘thickness direction’ refers to a 'T' direction. Here, the ‘thickness direction’
`may be the sameas a stacking direction in which dielectric layers are
`stacked.
`
`[0056] Thefirst and secondinternal electrodes 121 and 122 may be
`disposed to face each other, having at least one of the dielectric layers
`111 interposed therebetween, and maybealternately exposedtothefirst
`or second side surface S5 or S6.
`
`[0057] Thefirst and secondinternal electrodes 121 and 122 are
`alternately exposedto thefirst or second side surface S5 or S6, suchthat
`a reverse geometry capacitor (RGC) or low inductance chip capacitor
`(LICC) may be obtained as described below.
`
`[0058] In a general multilayer ceramic electronic component, external
`electrodes may be disposed on opposing end surfaces of the ceramic
`body in a length direction thereof.
`
`[0059] In this case, when analternative current (AC) voltage is applied to
`the external electrodes, a current pathis relatively long, whereby an
`intensity of an induced magnetic field may be increased, resulting in an
`increasein inductance.
`
`[0060] In orderto solvethisproblem, thefirst and second external
`
`electrodes 131 and 132 in the exemplary embodimentof the present
`disclosure may be disposed onthefirst and second side surfaces S5 and
`S6 of the ceramic body 110 opposing each otherin the width direction so
`as to reduce the current path.
`
`2 of 6
`
`Page 8 of 48
`
`Page 8 of 48
`
`
`
`[0061] In this case, since a distance between the first and second
`
`external electrodes 131 and 132 is relatively short, the current path
`may be reduced, ... resulting in a reduction in inductance.
`
`Further exemplary information from the specification of the subject Application
`USSN 14/259,011 relates to dielectric grain subject matter, as recited below re
`
`application Paragraphs [0087] and [0088] (emphasis added):
`
`[0087] FIG. 5 is an enlarged view of part Z of FIG. 4.
`
`[0088] Referring to FIG. 5, the average numberofdielectric grains 111a
`presentin a single dielectric layer 111 in a thickness direction thereof may
`be 2 or greater.
`
`Such Fig.5 of the USSN 14/259,011 is reproduced below:
`
`
`
`Claim 1 of the subject Application USSN 14/259,011 relates to multilayered
`
`ceramic capacitor subject matter, and recites in pertinent part (bracketed comments
`
`added):
`
`1. A multilayer ceramic capacitor, comprising:
`a ceramic body [110] including dielectric layers [111] and havingfirst
`and second main surfaces [S1, S2] opposing eachother,first and second
`
`3 of 6
`
`Page 9 of 48
`
`Page 9 of 48
`
`
`
`side surfaces [S5, S6] opposing eachother, andfirst and second end
`surfaces [S3, S4] opposing each other;
`an active layer including a plurality of first and second internal
`electrodes [121, 122] disposed to face each other with at least one of the
`dielectric layers interposed therebetween andalternately exposed to the
`first or second side surface;
`upper and lower coverlayers [112, 113] disposed on and below the
`active layer, respectively; and
`a first external electrode [131] disposed on thefirst side surface [S3] of
`the ceramic body andelectrically connected tothefirst internal electrodes
`[121] and a second external electrode [132] disposed on the second side
`surface [S4] and electrically connected to the secondinternal electrodes
`[122],
`wherein when a thickness of the ceramic body is defined as T and a
`width thereof is defined as W, 0.75W.Itoreq.T.Itoreq.1.25W is satisfied,
`when a gap betweenthefirst and second external electrodesis
`defined as G, 30 .mu.m.ltoreq.G.Itoreq.0.9W is satisfied {Fig. 4], and
`an average numberofdielectric grains in a single dielectric layer in a
`thickness direction thereof is 2 or greater [Fig. 5].
`
`Independentclaim 8 relates to a printed circuit board having at least two
`electrode pads, and such a multilayer ceramic capacitor mounted and soldered thereon.
`Document 2 (D2) is entitled "Multilayer Ceramic Capacitor With Internal Current
`Cancellation and Bottom Terminals," and discloses subject matter pertinent to the
`
`subject Application USSN 14/259,011. See, for example, D2, Fig. 4 reproduced below
`and showing a ceramic multi-layer capacitor 42 mounted on printed circuit board 22 per
`
`vias and solder pads.
`
`Page 10 of 48
`
`
`Lae)
`j
`
`
`DARAAN
`Swe
`
`
`BOS
`
`Ree
`RADAPAD
`
`
`
`26
`
`iR
`
`De
`
`
`
`
`
`Page 10 of 48
`
`
`
`Further, the D2 specification refers to reducing inductancein the context of both
`reverse geometry capacitors and low aspectratio (length to width ratio). Both such
`features are pertinent to the subject Application USSN 14/259,011. See, for example,
`D2, specification Col. 1, lines 28-60 (emphasis added):
`
`The prior art includes several strategies for reducing equivalent series
`inductance, or ESL, of chip capacitors compared to standard multilayer
`chip capacitors. A first exemplary strategy involves reverse geometry
`termination, such as employed in low inductance chip capacitor
`(LICC) designs [which] are terminated _on the long side of a chip
`instead of the short side. Since the total inductance of a chip
`capacitor is determined in part by its length to width ratio, LICC
`reverse geometry termination results in a reduction in inductance by
`as muchasa factor of six from conventional MLC chips.
`
`Interdigitated capacitors (IDCs) incorporate a second knownstrategy for
`reducing capacitor inductance [by] having a main portion and multiple tab
`portions that connect to respective terminations formed on the capacitor
`periphery.
`
`A still further known technologyutilized for reduction in capacitor
`inductanceinvolves[a] low inductance chip array (LICA) product, [which]
`achieves low inductance values by low aspectratio of the
`electrodes....
`
`Another aspect of D2 discloses the relationship between the gap betweena pair
`
`of external electrodes (which creates a current path or loop) and the resulting
`
`inductance of such arrangement. See, D2, Fig. 3, per beiow andits reiated description:
`
`"FIG. 3 provides a graphicalillustration of a general inductance trend for low
`
`inductance chip capacitors, especially depicting lumped ESL values versus cancellation
`
`loop width for multiple exemplary capacitor embodimentsofdiffering sizes;"
`
`5 of 6
`
`Page 11 of 48
`
`Page 11 of 48
`
`
`
`
`
`180
`
`160
`
`140
`
`120
`
`100 -
`
`ESL(pH) 0
`Lumped
`
`80
`
`60
`
`40
`
`20 +
`
`0
`
`0.5
`
`1
`
`1.5
`
`2
`
`Cancellation Loop Width (mm)
`
`FIG. 3
`
`Thus, per the foregoing, at least the exemplary above-indicated disclosure of
`Document 2 subject matter as relates to lowering inductance for a multilayer ceramic
`
`capacitor is pertinent to the subject Application USSN 14/259,011.
`
`6 of 6
`
`Page 12 of 48
`
`Page 12 of 48
`
`
`
`Third Party Submission for Application USSN 14/259,011
`
`Patent No.:
`
`Inventor:
`
`Application No.:
`
`Filed:
`
`Issue Date:
`
`Document 3
`
`US Patent 5,134,540
`
`Rutt
`
`07/758 623
`
`September 12, 1991
`
`July 28, 1992
`
`Concise Description:
`
`Document3 was published as a patentprior to the earliest possible priority date
`
`of June 14, 2013 for the subject Application USSN 14/259,011.
`
`The subject Application USSN 14/259,011 is entitled "Multilayer Ceramic
`
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`
`a particular capacitor arrangement whichresults in a reverse geometry capacitor having
`
`relatively low inductance.
`
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`132
`
`z
`\
`
`131
`
`“12
`
`
`
`
`
`
`
`
`seecccoaae ZorrahormntonbrmnateSe
`
`1 of 6
`
`Page 13 of 48
`
`Page 13 of 48
`
`
`
`Examples from the specification of the subject Application USSN 14/259,011
`regarding such reverse geometry feature arrangement and resulting relatively low
`inductance are recited below re application Paragraphs [0050], and [0056] through
`
`[0061] (emphasis added):
`
`[0050] Referring to FIG. 1, in the multilayer ceramic capacitor according to
`an exemplary embodiment of the present disclosure, a ‘length direction’
`refers to an 'L' direction, a 'width direction’ refers to a 'W' direction, and a
`‘thickness direction’ refers to a 'T' direction. Here, the ‘thickness direction’
`may be the sameasa stacking direction in which dielectric layers are
`stacked.
`
`[0056] Thefirst and secondinternal electrodes 121 and 122 may be
`disposed to face each other, having at least one of the dielectric layers
`111 interposed therebetween, and maybealternately exposedto thefirst
`or secondside surface S5 or S6.
`
`[0057] Thefirst and secondinternal electrodes 121 and 122 are
`alternately exposedto thefirst or second side surface S5 or S6, such that
`a reverse geometry capacitor (RGC) or low inductance chip capacitor
`(LICC) may be obtained as described below.
`
`[0058] In a general multilayer ceramic electronic component, external
`electrodes may be disposed on opposing end surfacesof the ceramic
`body in a length direction thereof.
`
`[0059] In this case, when analternative current (AC) voltage is applied to
`the external electrodes, a current path is relatively long, whereby an
`intensity of an induced magnetic field may be increased, resulting in an
`increasein inductance.
`
`[0060] In order to solve this problem, the first and second external
`electrodes 131 and 132 in the exemplary embodimentof the present
`disclosure may be disposed on thefirst and second side surfaces S5 and
`S6 of the ceramic body 110 opposing each otherin the width direction so
`as to reduce the current path.
`
`2 of 6
`
`Page 14 of 48
`
`Page 14 of 48
`
`
`
`[0061] In this case, since a distance betweenthefirst and second
`external electrodes 131 and 132 is relatively short, the current path
`may be reduced, ... resulting in a reduction in inductance.
`
`Further exemplary information from the specification of the subject Application
`
`USSN 14/259,011 relates to dielectric grain subject matter, as recited below re
`
`application Paragraphs [0087] and [0088] (emphasis added):
`
`[0087] FIG. 5 is an enlarged view of part Z of FIG. 4.
`
`[0088] Referring to FIG. 5, the average numberof dielectric grains 111a
`presentin a single dielectric layer 111 in a thickness direction thereof may
`be 2 or greater.
`
`Such Fig.5 of the USSN 14/259,011 is reproduced below:
`
`
`
`Claim 1 of the subject Application USSN 14/259,011 relates to multilayered
`
`ceramic capacitor subject matter, and recites in pertinent part (bracketed comments
`
`added):
`
`1. A multilayer ceramic capacitor, comprising:
`a ceramic body [110] including dielectric layers [111] and havingfirst
`and second main surfaces [S1, $2] opposing eachother,first and second
`
`3 0f6
`
`Page 15 of 48
`
`Page 15 of 48
`
`
`
`side surfaces [S5, S6] opposing each other, and first and second end
`surfaces [S3, S4] opposing each other;
`an active layerincluding a plurality of first and second internal
`electrodes [121, 122] disposed to face each other with at least one of the
`dielectric layers interposed therebetween andalternately exposed to the
`first or second side surface;
`upper and lowercoverlayers [112, 113] disposed on and below the
`active layer, respectively; and
`a first external electrode [131] disposed onthefirst side surface [S3] of
`the ceramic body and electrically connectedto the first internal electrodes
`[121] and a second external electrode [132] disposed on the second side
`surface [S4] and electrically connected to the secondinternal electrodes
`[122],
`wherein whena thickness of the ceramic body is defined as T anda
`width thereof is defined as W,0.75W.ltoreq.T.ltoreq.1.25W is satisfied,
`when a gap betweenthefirst and second external electrodesis
`defined as G, 30 .mu.m.ltoreq.G.ltoreq.0.9W is satisfied {Fig. 4], and
`an average number ofdielectric grains in a single dielectric layer ina
`thickness direction thereof is 2 or greater [Fig. 5].
`
`Independentclaim 8 relates to a printed circuit board having at least two
`
`electrode pads, and such a multilayer ceramic capacitor mounted and soldered thereon.
`
`Document 3 (D3) is entitled "Varistor or Capacitor and Method of Making Same,”
`
`and discloses subject matter pertinent to the subject Application USSN 14/259,011.
`
`See, for example, D3, Figs. 1 and 1A reproduced below and described as "FIG. 1. isa
`
`schematic sectional view through a capacitor or varistor in accordance with the
`
`invention. FIG. 1A is a magnified section of the circled component portion of FIG. 1.":
`
`FIG. |
`
`18
`cae
`RaaRaatTIIKXeee
`
`
`4of6
`
`Page 16 of 48
`
`Page 16 of 48
`
`
`
`
`
`The D3 specification refers to features 13, 14, and 15 as dielectric layers, and
`
`enlarged Fig. 1A showsgrains 24 and 25 regarding oneillustrated exemplary grain
`
`boundary. See, for example, D3, specification Col. 3, lines 47-56 and Col. 4, lines 31-
`
`40.
`
`The D3 Abstract states in pertinent part:
`
`In accordance with the method the ceramic layers of the varistor are
`formedby providing at least two strata separated by a boundary layer
`which resists grain growth thereacross. ... By this method the ceramic
`layers have a predictable number of grain boundaries between adjacent
`electrodes.
`
`Since those of ordinary skill in the art understand that grain boundaries are
`
`aroundgrains, plural "boundaries" clearly implies plurality of grains.
`
`Another aspect of D3 discloses more explicitly that the more grains, the higher
`
`the break downvoltage, while a singular grain is not favorable. See, D3, Col. 1, lines
`
`57-69:
`
`It has been experimentally determined that the breakdown voltage of a
`varistor-ceramic formulation is a function of the numberof grain
`boundaries of the ceramic grains intervening between adjacentelectrode
`layers. The greater the number of boundaries between adjacentlayers,
`the higher the break down voltage necessary to provide a conductive path.
`
`5 of 6
`
`Page 17 of 48
`
`Page 17 of 48
`
`
`
`Conversely, in the event of a grain size such that grains of ceramic directly
`span the distance between adjacent electrodes, the device will exhibit
`break down orpasscurrent at extremely low voltages.
`
`Asstated further in D3, Col. 3, lines 15-17: "In this manner, there may be formed
`
`a ceramic layer wherein the numberof grains taken in a depth-wise direction may be
`
`accurately controlled."
`
`Also, D3, claim 3 states in pertinent part: "3. In a monolithic ceramic ... capacitor
`
`comprising at least one ceramic dielectric layer, ... said layer being comprised ofat
`
`least two discrete strata, each of said strata being comprised of grains of ceramic
`
`material, ...."
`
`Therefore, the average numberof dielectric grains is 2 or greater.
`
`Thus, per the foregoing, at least the exemplary above-indicated disclosure of
`
`Document 3 subject matter as relates to grain related features for a ceramic capacitoris
`
`pertinent to the subject Application USSN 14/259,011.
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`6 of 6
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`Page 18 of 48
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`Page 18 of 48
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`
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`Third Party Submission for Application USSN 14/259,011
`
`Patent No.:
`
`Inventor:
`
`Application No.:
`Filed:
`
`Issue Date:
`
`Document 4
`
`US Patent 5,952,040
`
`Yadavetal.
`
`08/730,661
`October 11, 1996
`
`September 14, 1999
`
`Concise Description:
`Document4 was published as a patentprior to the earliest possible priority date
`
`of June 14, 2013 for the subject Application USSN 14/259,011.
`The subject Application USSN 14/259,011 is entitled "Multilayer Ceramic
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`a particular capacitor arrangement which results in a reverse geometry capacitor having
`
`relatively low inductance.
`
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`1 of 5
`
`Page 19 of 48
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`Page 19 of 48
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`
`
`Examples from the specification of the subject Application USSN 14/259,011
`regarding such reverse geometry feature arrangement and resulting relatively low
`inductance are recited below re application Paragraphs [0050], and [0056] through
`
`[0061] (emphasis added):
`
`[0050] Referring to FIG. 1, in the multilayer ceramic capacitor according to
`an exemplary embodimentof the presentdisclosure, a ‘length direction’
`refers to an 'L' direction, a ‘width direction’ refers to a 'W' direction, and a
`‘thickness direction’ refers to a 'T' direction. Here, the ‘thickness direction’
`may be the sameasa stacking direction in which dielectric layers are
`stacked.
`
`[0056] Thefirst and secondinternal electrodes 121 and 122 may be
`disposed to face each other, having at least one of the dielectric layers
`111 interposed therebetween, and maybe alternately exposed tothefirst
`or secondside surface S5 or S6.
`
`[0057] The first and secondinternal electrodes 121 and 122 are
`alternately exposedto the first or second side surface S5 or S6, suchthat
`a reverse geometry capacitor (RGC) or low inductance chip capacitor
`(LICC) may be obtained as described below.
`
`[0058] In a general multilayer ceramic electronic component, external
`electrodes may be disposed on opposing end surfaces of the ceramic
`body in a length direction thereof.
`
`[0059]In this case, whenanalternative current (AC) voltage is applied to
`the external electrodes, a current path is relatively long, whereby an
`intensity of an induced magnetic field may be increased, resulting in an
`increase in inductance.
`
`[0060] In orderto solve this problem, the first and second external
`electrodes 131 and 132 in the exemplary embodimentof the present
`disclosure may be disposed on thefirst and second side surfaces S5 and
`S6 of the ceramic body 110 opposing each otherin the width direction so
`as to reduce the current path.
`
`20f5
`
`Page 20 of 48
`
`Page 20 of 48
`
`
`
`[0061] In this case, since a distance betweenthefirst and second
`
`external electrodes 131 and 132 is relatively short, the current path
`may be reduced, ... resulting ina reduction in inductance.
`
`Further exemplary information from the specification of the subject Application
`USSN 14/259,011 relates to dielectric grain subject matter, as recited below re
`application Paragraphs [0087] and [0088] (emphasis added):
`
`[0087] FIG. 5 is an enlarged viewofpart Z of FIG. 4.
`
`[0088] Referring to FIG. 5, the average numberofdielectric grains 111a
`present in a single dielectric layer 111 in a thickness direction thereof may
`be 2 or greater.
`
`Such Fig.5 of the USSN 14/259,011 is reproduced below:
`
`
`
`FIG. 5
`
`Claim 1 of the subject Application USSN 14/259,011 relates to multilayered
`ceramic capacitor subject matter, and recites in pertinent part (bracketed comments
`
`added):
`
`1. A multilayer ceramic capacitor, comprising:
`a ceramic body [110] including dielectric layers [111] and havingfirst
`and second main surfaces [S1, S2] opposing eachother,first and second
`
`3 of 5
`
`Page 21 of 48
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`Page 21 of 48
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`
`
`side surfaces [S5, S6] opposing each other, andfirst and second end
`surfaces [S3, S4] opposing each other;
`an active layer including a plurality offirst and secondinternal
`electrodes [121, 122] disposed to face each otherwith at least one of the
`dielectric layers interposed therebetween and alternately exposed to the
`first or second side surface;
`upper and lower coverlayers [112, 113] disposed on and below the
`active layer, respectively; and
`a first external electrode [131] disposed onthefirst side surface [S3] of
`the ceramic body andelectrically connected to thefirst internal electrodes
`[121] and a second external electrode [132] disposed on the secondside
`surface [S4] and electrically connected to the second internal electrodes
`[122],
`wherein whena thickness of the ceramic body is defined as T and a
`width thereof is defined as W, 0.75W.Itoreq.T.Itoreq.1.25W is satisfied,
`when a gap betweenthefirst and second external electrodesis
`defined as G, 30 .mu.m.ltoreq.G.Itoreq.0.9W is satisfied {Fig. 4], and
`an average numberofdielectric grains in a single dielectric layer in a
`thickness direction thereof is 2 or greater [Fig. 5].
`
`Independentclaim 8 relates to a printed circuit board having at least two
`electrode pads, and such a multilayer ceramic capacitor mounted and soldered thereon.
`Document 4 (D4)is entitled "Passive Electronic Components From Nano-
`
`Precision Engineered Materials," and discloses subject matter pertinent to the subject
`
`Application USSN 14/259,011.
`
`In particular, D4 relates in part to ceramic layers coated
`
`with electrodes as part of passive electronic components.
`
`See, for example, D4, specification Col. 6, lines 44-48 (emphasis added):
`
`Therefore, according to the foregoing objectives, one aspect of this
`invention involves the use of nanostructured precursors (narrowly
`distributed nanosize powders with mean grain size preferably less than
`100 nm and standard deviation preferably less than 25 nm) to form the
`ceramic layers, electrode layers, or both, in passive electronic
`components.
`
`4o0f5
`
`Page 22 of 48
`
`Page 22 of 48
`
`
`
`Another aspect of D4 discloses the benefit of using multiple grains, indicating that
`the strength is better, and that the resulting electrical parameters are improved.
`See, D4, Col. 8 lines 52 through Col. 9,line 10 (emphasis added):
`
`A primary aspectof this invention lies in the recognition that a standing
`barrier to markedly improved technology in the manufacture of passive
`electronic components exists in the limitations inherent with the grain size
`of the ceramic and electrode material used. ... Since precursor powders
`are not ductile, the films of ceramic material have to be packed several
`grains thick and sintered to ensure that there are no pin-holes in the
`resulting ceramic and electrode layers. Thus, even though the
`theoretical limit with existing materials and manufacturing technology on
`the thickness of the ceramic layer is in the 2 to 5 .mu.m range, current
`passive electronic components are routinely made with 5 to 20
`.mu.m thick ceramic layers. Attempts to reduce this thickness to the
`theoretical limit have resulted in problemsof electrical, thermal,
`mechanical, or chemical breakdown with consequentreliability
`issues. Thus, it is clear that the minimum thickness of ceramic and
`electrode layers attainable with conventional processesis limited by
`the grain size of the precursor ceramic and electrode material.
`
`In "Example 1 — Capacitor", the subject layer was about 8 to 9 grains thick. See,
`
`D4, Col. 15, lines 62-65.
`
`Thus, per the foregoing, at least the exemplary above-indicated disclosure of
`
`Document 4 subject matter as relates to grain thicknessfor dielectric layers of a ceramic
`
`capacitor is pertinent to the subject Application USSN 14/259,011.
`
`5 of 5
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`Page 23 of 48
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`Page 23 of 48
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`
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`Third Party Submission for Application USSN 14/259, 014
`
`Mocument 5
`
`DesignCon East 2005
`
`Title:
`
`Subject:
`
`TecForum TF-MP2Z
`
`inductance of Bypass Capacitors; How to Define, How
`io Measure, Howfo Simulate
`
`Presenters:
`
`Joseph M. Hock et al.
`
`Paper Publication Year.
`
`2005
`
`Cancise Description:
`
`Document § was published as a paper in 2005 prior to the earliest possible
`
`priority date of June 14, 20193 for the subject Application USSN 14/259,011,
`
`The subject Application USSN 14/259 071 is entitled "Multilayer Ceramic
`
`Capacitor and Board Having the Same Mounted Thereon.” it relates in pertinent
`
`part fo a particular capacitor arrangement which results in a reverse geometry
`
`capacitor having relatively low inductance.
`
`Fig. 4 af subject application USGN 14/259,017 is exemplary (reproduced
`
`below}
`
`Page Tot?
`
`Page 24 of 48
`
`Page 24 of 48
`
`
`
`Examples from the specification of the subject Application USSN
`14/259,011 regarding such reverse geometry feature arrangement and resulting
`
`relatively low inductance are recited below re application Paragraphs [O050], and
`
`fOO56T through [0067] (emphasis added):
`
`fOO50] Referring to FIG. 1, in the multilayer ceramic capacitor
`according to an exemplary embodiment of the present disclosure, a
`Tength direction’ refers to an ‘L’ direction, a ‘width direction’
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