Jan. 22, 1963
`
`Filed Aug. 31, 1961
`
`D. V. JONES
`VARIABLE PULSE WIDTH PARALLEL INVERTERS
`2 Sheets-Sheet 1
`
`3,075,136
`
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`LIBERTY EXHIBIT 1028, Page 1
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`LIBERTY EXHIBIT 1028, Page 1
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`

`

`Jan. 22, 1963
`
`Filed Aug. 31, 1961
`
`2 Sheets-Shset 2
`
`D. V. JONES
`VARIABLE PULSE WIDTH PARALLEL INVERTERS
`
`3,075,136
`
`INVENTOR.
`LWMBfeb ViTornes,
`"Pangronnie
`
`ACCOrney.
`
`_ LIBERTY EXHIBIT 1028, Page 2
`
`LIBERTY EXHIBIT 1028, Page 2
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`

`

`United States Patent Office
`
`3,075,136
`Fatented Jan. 22, 1963
`
`1
`3,975,136
`VARIABLE PULSE WIDTH PARALLEL INVERTERS
`Dwight V. Jones, Baldwinsville, N.Y., assignor to Gen-
`eral Electric Company, a corporation of New York
`Filed Aug. 31, 1961, Ser. No. 135,334
`11 Claims.
`(Cl. 321—45)
`
`This invention relates to parallel invérters and more
`particularly to an improved arrangement of a parallel in-
`verter wherein the pulse width of the inverter output
`can be readily controlled.
`Parallel inverters employing such switching devises as
`thyratrons,
`ignitrons and silicon controlled:
`rectifiers,
`have been generally used for higher power applications
`‘a8 compared with the series type of inverters, At low
`operating frequencies, the parallel inverter can be used
`to provide a substantially square-wave alternating out-
`put from a direct current source. By rectifying the out-
`put voltage of the parallel inverter, the inverter can be
`used as a D.C. to D.C. converter or by employing a rec-
`tified alternating voltage input, the inverter can be read-
`ily adapted for use as a frequency changer.
`in many applications of the parallel inverter, it is de-
`sirable that the power output of the inverter be effec-
`tively regulated. For example, in a lamp dimming sys-
`tem, a wide range of regulation is required to effectively
`operate the lamps at various levels of luminous intensity,
`Similarly, in a power supply system for the operation of
`motors at various speeds,it is desirable, if not necessary,
`to regulate the power supplied to the motors. Hereto-
`fore, the arrangements used to achieve power regulation
`in a parallel inverter have not been entirely satisfactory.
`In prior art parallel inverter circuits employing thyra-
`trons, regulation was achieved at the expense of increased
`commutating capacity, and the circuits were inefficient.
`There is a need, therefore, for a parallel circuit inverter
`wherein a high degree of regulation can be achieved
`readily andefficiently.
`Accordingly; an object of this invention is to provide
`an improved variable pulse width parallel inverter.
`Another object of the present invention is to provide
`an improved paraliel inverter wherein regulation of the
`power supplied by the inverteris efficiently achieved.
`Itis still another object of the invention to provide an
`improved parallel circuit inverter wherein the pulse width
`of the inverter output can be readily varied to achieve
`regulation by feedback control arrangements.
`The foregoing and other obiects and advantages of the
`invention are realized by a parallel inverter circuit hay-
`ing a pair of parallel connected controlled rectifiers which
`are alternately triggered at a predetermined frequency to
`cause a reversal of current flow through a first and a sec-
`ond primary winding portion of an output transformer.
`The conduction time of the pair of controlled rectifiers
`is controlled by firing a cut-off controlled rectifier ata
`predetermined point at each half cycle to connect a
`charged capacitor in parallel with an inductor in the cir-
`cuit and thus provide a pulse that turns off the conduct-
`ing one of the pair of controlled rectifiers.
`In this man-
`ner the pulse width of the inverter output is regulated.
`The firing of the cut-off controlled rectifier is synchro-
`nized with the start of the conduction of the controlled
`rectifiers so that the controlled rectifier is fired after a
`predetermined interval in each half cycle after one of the
`pair of controlled rectifiers is fired.
`The subject matter which I regard as my invention is
`set forth in the appended claims. The invention itself,
`however,
`together with further objects and advantages
`thereof may be understood by referring to the following
`description taken in connection with the accompanying
`drawings in which:
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`1 is a schematic circuit diagram of a parallel in-
`FIG.
`verter circuit illustrating one embodiment of the inven-
`tion.
`FIG. 2 is a schematic circuit diagram of the firing cir-
`cuit for triggering controlled rectifier SCR; of the par-
`allel inverter illustrated in FIG. 1; and
`FIG, 3 is a schematic circuit diagram of thefiring cir-
`cuit used to alternately trigger controlled rectifiers SCR,
`and SCR, of the parallel inverter illustrated in FIG. 1.
`Having more specific reference now to the parallel in-
`verter identified generally by reference numeral 11 and
`shown in FIG.1, it will be seen that the parailel inverter
`‘Li includes a pair of controlled rectifiers SCR, and SCR,
`connected in circuit with a first winding portion P, and a
`second winding portion P, of output transformer Ty. As
`the controlled rectifiers SCR; and SCR, are alternately
`triggered by firing circuit 12, a voltage of one polarity
`is induced across secondary windings S, during one half
`of each cycle of the inverter output and a voltage of op-
`posite polarity is induced across the secondary winding
`S; in the other half of each cycle.
`It will be noted that controlled rectifier SCR, and pri-
`mary winding portion P, are connected in a parallel cir-
`cuit with controlled rectifier SCR, and primary winding
`portion Py across a direct current supply means which
`includes a lead. 13 connected to a center-tap 14 on pri-
`mary winding Pj, lead 15 connected to a ground 16, and
`input terminal lead 17 provided for connection to the
`positive side of a direct current source,
`The output transformer T, has a magnetic core 18 and
`a secondary winding S; inductively coupled with the pri-
`mary winding P which is divided by tap 14 into primary
`winding portions P; and P,. As shown in FIG. 1, the
`secondary winding S, is connected in circuit by output
`leads 19, 29 with aload 21. Since transformer Ty is sub-
`jected to rapidly changing currents during the commuta-
`tion interval of the parallel inverter 11, the leakage re-
`actance of the transformer T, was preferably kept down
`toa minimum. Thus, the transformer T, was designed
`so that it operates below saturation. The leakage induc-
`tance between the primary winding portions P, and Po,
`and the source impedance is preferably kept relatively
`‘small so that it will have nosignificant effect on the com-
`mutation of the controlled rectifiers SCR, and SCR.
`It will be seen that in the illustrative embodiment of
`the invention shown in FIG. 1, the input terminal lead
`17 is connected in circuit with a pair of feedback diodes
`D,, Dz and with controlled rectifiers SCR,, SCR, through
`an inductor L;.
`Input terminal lead 17 is provided for
`connection to a suitable direct current voltage source,
`which should be capable of accepting power as well as
`supplying power.
`Inductor L,
`is connected in series
`circuit with a cut-off controlled rectifier SCR;. A com-
`mutating capacitor C,
`is connected in parallel circuit
`across inductor L, and controlled rectifier SCR;. so that
`when the controlled rectifier SCR, is triggered into a con-
`ducting state, inductor L, is connected in electrical cir-
`cuit and in parallel with the commutating capacitor C,.
`Thus, when connected in parallel,
`inductor L, and the
`commutating capacitor C, comprise an oscillatory circuit,
`Feedback diode D, is connectedin circuit with one end
`of primary winding portion P, and in inversé relation
`with controlled rectifier SCR. Similarly, feedback diode
`Dy, is connected in circuit with primary winding portion
`P; of the primary winding P and in inverse relation with
`controlled rectifier SCR».
`Connected in such an arrangement, the feedback diodes
`D,, Dy serve to limit the voltage across primary winding
`portions P;, P. of transformer T,
`to the magnitude of
`the D.C. voltage supply and make it possible to use
`silicon controlled rectifiers having a lower breakover
`voltage. Also, as will be hereinafter more full explained
`
`LIBERTY EXHIBIT 1028, Page 3
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`LIBERTY EXHIBIT 1028, Page 3
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`3,075,136
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`3
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`in connection with the description of the operation of
`the parallel
`inverter 11,
`the diodes D,, Dy feed back
`reactive power into the supply and thereby reduce volt-
`age variations across the secondary winding S,.
`Continuing with the description of the circuit shown
`schematically in FIG. 1,
`it will be seen that one end
`of the inductor L, is connected in circuit with commu-
`tating capacitor C, and controlled rectifier SCR3. The
`other end of the inductor L, is connected in circuit with
`the anodes of diodes D3, Ds. They are so poled that
`when either controlled rectifier SCR, or SCR,
`is in a
`conducting state,
`the lower plate of capacitor C;, as
`seen in the view of FIG. 1, will be negatively charged to
`a voltage considerably greater than the source of voltage.
`This increased voltage is due to the transformer action in
`charging the commutating capacitor C, through the diodes
`D; and D, and also the circuit time constants. Prefer-
`ably,
`the inductor L, provides an inductance sufficient
`to keep the current flow through it to a low value un-
`til the controlled rectifier SCR; is turned off by the re-
`versal of the current in the oscillatory circuit comprised
`of the capacitor C;-and the inductor L,.
`The controlled rectifiers SCR; SCR, and SCR; used
`in the illustrative embodiment of the invention were
`PNPN semiconductors each having three terminals, an
`anode represented by the arrow symbol, a cathode rep-
`resented by a line drawn through the apex of the arrow
`symbol and a gate represented by a diagonal line ex-
`tending from the cathode.
`Silicon controlled rectifiers
`are desirable power switching devices since relatively
`large amounts of power can be switched into a load using
`an insignificant amount of power to trigger the switching
`device. The operating characteristics of a silicon con-
`trolled rectifier are such that it conducts in a forward
`direction with a forward characteristic very similar to
`that of an ordinary rectifier when a gate signal is applied.
`Thus, when a positive voltage is applied to the outside
`P layer and a negative voltage is applied to the outside
`N layer, the two outside junctions are biased in a for-
`ward direction while the inner junction is reversely biased.
`Current does not flow through the controlled rectifier
`under these conditions, except for a small leakage cur-
`rent. When the voltage. is increased to a breakover volt-
`age, the current gain of the device increases to unity at
`which time the current. through the controlled rectifier
`will increase suddenly and become a function of the ap-
`plied voltage and the load impedance. The controlled
`rectifier will remain in a conductive state provided the
`current through the device exceeds a minimum holding
`value.
`A small amount of current supplied to the gate lead
`can be used for controlling the firing of the controlled
`rectifier since the current supplied to the gate lowers the
`breakover voltage. The controlled rectifier is normally
`operated well below the forward breakover voltage and
`is triggered by supplying current to the gate lead.
`A capacitor C, is connected in circuit with the cathode
`of controlled rectifier SCR, and across the primary wind-
`ing portion P;, so that the cathode is clamped.to ground
`when a negative turn-off pulse is applied to the anode of
`controlled rectifiers SCR,.
`It. also serves to minimize
`switching transients from the load. Similarly, capacitor
`C; is connected in circuit with controlled rectifier SCR,
`and across primary winding portion P, of the output trans-
`former T, so that
`the cathode of controlled rectifier
`SCR,
`is clamped to ground when a negative turn-off
`pulse is applied to its anode. Capacitors Cz and C, en-
`hance the performance of the circuit, but they are not
`absolutely necessary since the circuit will operate without
`them.
`In order to provide a unidirectional supply voltage for
`firing circuit 22, diodes Ds; and Dg are connected across
`the primary winding P. A lead 23 is connected in cir-
`cuit with cathodes. of the diodes Ds, Dg,
`the anodes
`being connected in circuit with.
`the cathodes of con-
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`trolled rectifiers SCR, SCR,. Thus, firing circuit 22
`is energized when either controlled rectifier SCR, or SCRe
`is conducting.
`It will be seen that the diode D;is poled
`so that when controlled rectifier SCR, starts conducting,
`a current is supplied to firing circuit 22. Also, diode Dg
`is poled so that current will be supplied to firing circuit
`22 the instant controlled rectifier SCR. is triggered.
`In
`this mannerthe firing circuit 22 is synchronized with the
`start of each half cycle of the inverter. output which be-
`gins with the triggering of oné of the controlled recti-
`fiers SCRy, SCRg.
`In FIGS. 2 and 3, I have illustrated the schematic
`circuit diagrams which are represented in the schematic
`diagram of FIG.
`1 in block form. Firing circuit 12 is
`connected in circuit with the gates and cathodes of con-
`trolled rectifiers SCR, SCR» by electrical leads 25, 26
`and 27, 28, respectively. The gate and cathode of cut-
`off controlled rectifiers SCRare connected in circuit with
`firing circuit 22 by means of electrical leads 29, 36. The
`type of firing circuits 12 and 22 which were employed
`in the exemplification of the invention shown in FIG, 1
`are well known in the art and are described in the Gen-
`eral Electric Controlled Rectifier Manual, first edition,
`1960, at pages 50-58.
`In accordance. with the invention, the firing circuit 22
`provides a current pulse to fire controlled rectifier SCR
`which turns off the conducting controlled rectifier SCR,
`or SCR, at a predetermined point in each half cycle.
`It
`will be seen that input lead 23 connectsfiring circuit 22
`in circuit with the controlled rectifiers so that a current
`is supplied only when one of the controlled rectifiers is
`conducting. A resistor Rp and the zener diode Z, limit
`the maximum interbase voltage of unijunction transistor
`UIT, The zener diode Z,
`is a semiconductor diode,
`preferably a silicon diode, having a predetermined re-
`verse breakdown voltage. For voltages below the break-
`down value, the zener diode Z, acts as a rectifier and only
`a negligibly small current can flow in the reverse direction.
`When the reverse voltage exceeds the breakdown value,
`the zener diode Z, presents a very low resistance and
`permits current to flow freely in the reverse direction
`with no substantial increase in voltage.
`A resistor Rg is connected in circuit with the base-two
`electrode 31 in order to compensate for temperature
`variations of the interbase resistance of the unijunction
`transistor UJT;. Capacitor C3 is charged through re-
`sistor Ry and the variable resistor Rs.
`‘The rate at which
`the capacitor C; is charged to the peak emitter voltage
`of unijunction transistor UST, determines the point in
`each half cycle at which unijunction transistor UJTis
`fired. When unijunction transistor UJT, is fired, a pulse
`of current flows through primary winding P3 of the pulse
`transformer T; and a current pulse is induced in the sec-
`ondary winding S;, electrical leads 29, 39 applying this
`pulse across the gate and cathode of cut-off controlled rec-
`tifier SCR;.
`It will be seen that the primary winding P;
`is connected at one end with base-one electrode 32 and
`at the other end with a ground 33.
`Transistor Q; acts as a shunt to divert charging current
`flowing through the resistor Ry and R;.. The amount of
`charging current diverted is proportional to the amount
`of current supplied to the base electrode of the transistor
`through lead 35. Thus, as base current is increased,
`additional current is diverted and the firing angle of the
`unijunction transistors UIT,
`is retarded. Accordingly,
`the firing of controlled rectifier SCR; is also retarded and
`the cut-off of the conducting controlled rectifier SCR, or
`SCRgis delayed.
`In FIG.3, I have illustrated a transistor multi-vibrator
`firig circuit 12 that was used in the illustrative embodi-
`ment of the invention toalternately apply firing pulses to
`controlled rectifiers SCR, and SCRy. Two pairs of out-
`put leads 25, 26 and 27, 28 which are connectedin circuit
`with the secondary windings S,, S; of pulse transformers
`Ty. are provided for connection across the gate and
`
`LIBERTY EXHIBIT 1028, Page 4
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`LIBERTY EXHIBIT 1028, Page 4
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`5
`cathode of controlled rectifiers SCR,, SCRg,respectively,
`as shown in FIG. 1. The primary winding portions P,,
`Ps are connected in circuit with the collector of transistors
`Qs, Qs.
`Input terminal lead 36 is provided for connec-
`tion to the positive side of the direct current source used
`to energize the parallel inverter in FIG.1,
`Although in the exemplification of the invention a
`multi-vibrator circuit configuration was used to provide
`alternating trigger pulses with good symmetry tothe con-
`trolled rectifiers SCR, SCRo, it will be appreciated that
`other firing circuits can be used to generate and provide
`alternate triggering pulses at a predetermined frequency
`to a pair of controlled rectifiers, As an example, a pair
`of unijunction transistor relaxation osciliators coupled
`together by means of a capacitor connected between the
`emitters may be employed to provide the alternating
`pulses. Aliso, firing circuits utilizing saturating reactors
`may be used as a pulse source.
`The unijunction relaxation oscillator portion of the
`multi-vibrator circuit provides good symmetry and fre-
`quency control to the multi-vibrator. Although in ex-
`emplification of
`the invention the inverter circuit 11
`shown in FIG,
`1 was supplied with short duration trigger
`pulses to fire controlled rectifiers SCR, and SCRo, for
`highly reactive loads the trigger pulse width must be ex-
`tended in time for the duration of reactive current flow.
`The maximum pulse width at the gate connot exceed the
`inverter pulse width,
`therefore for large reactive loads
`the trigger pulse width must follow the changing inverter
`pulse width. This varying trigger pulse width can be
`obtained by varying the symmetry of a multivibrator as
`a function of the inverter pulse width,
`Continuing now with the description of the firing circuit
`12 shown schematically in FIG.3, it will be seen that the
`firing circuit 12 employs two PNP transistors Qs, Q3 ina
`saturating flip-flop arrangement. A unijunction transistor
`UIT, serves to trigger the flip-flop from one state to the
`other by providing a negative ttigger pulse. This nega-
`tive pulse is developed across resistor Ris and is coupled
`to the resistor Rg by means
`for
`the capacitor Co.
`Capacitor Cg serves as a timing capacitor. Cross coupling
`capacitors C; and C, are relatively small in size and are
`connceted in parallel with the cross-coupling resistors Ry,
`Rg and in circuit with the base electrodes of transistors
`Qs, Qs. Diodes Dy and Dg clamp the base electrode of
`transistors Qs, Qs to the emitter electrode,
`Resistor Ry and the variable resistor or potentiometer
`Rig control the charging rate of the timing capacitor Cg
`and thereby serve as the frequency control forthe inverter
`circuit. Resistor Ri, is connected to the base-two elec-
`trode 37 of the unijunction éransistor UIT. Base-one
`electrode 38 is connected in circuit with a ground 39 by
`means of leads 40, 41,
`esistors Rg, Riz, Ryg serve as
`temperature stabilizing resistors. Resistor Rio provides
`the frequency control for the output of the inverter since
`it controls the rate at which the flip-flop is triggered.
`Capacitors Cy and Cyy in conjunction with the gate to
`cathode impedance of the controlled rectifier differentiate
`the square wave ‘across secondary windings S, and S; to
`provide a pulse output. Pulse triggering can be used
`unless the load has a low and lagging power factor.
`Throughthe action of the zener diode Zy andresistor Rig
`a regulated D.C. voltageis applied tothe unijunction tran-
`sistor UIT.
`Having reference now to the circuit shown in FIGS, 1,
`2 amd 3, the operation of the parallel inverter circuit 41
`will now be more fully described. When the positive
`terminal of a direct current source is connected in circuit
`with input terminal lead 17 and the inverter circuit 11 is
`effectively grounded as shown in FIG. 1, invertercircuit
`11 is energized. Let us assume arbitrarily that a firing
`pulse is supplied initially to the gate of the controlled
`rectifier SCR; When controlled rectifier SCR,
`is trig-
`gered, the commutating capacitor C, is charged toa volt-
`age that is greater in magnitude than the impressed volt-
`
`6
`age due to the transformed action that charges the capac-
`itor C,
`through the diode Dy. Also, when controlled
`rectifier SCR,
`is triggered, current flows through diode
`Dsto firing circuit 22 and capacitor C, begins its charging
`period.
`Depending upon the setting of the variable resistor or
`potentiometer Rs and the feed-back current being sup-
`plied to the transistor Q,, the unijunction transistor UJT,
`will trigger the control rectifier SCR, at a predetermined
`point in the half cycle of the alternating inverter output.
`When controlled rectifier SCR, is triggered, it will be seen
`that the lower plate of the commutating capacitor C, is
`negatively charged. Also, when controlled rectifier SCR3
`is triggered, commutating capacitor C,
`is connected in
`parallel circuit relation with the inductor Ly. An oscil-
`latory pulse is developed across the inductor Ly which
`reverse biases controlled rectifier SCR, and thereby turns
`it off,
`The commutating capacitor C, will maintain a reverse
`bias across controlled rectifier SCR, long enough for the
`controlled rectifier SCR, to return to a blocking state.
`Capacitor Cy clamps the cathode of controlled rectifier
`SCR, to ground 16 while the negative turn-off pulse is
`applied to the ancde.
`It will be seen that controlled
`rectifier SCR; conducts for a very short interval since
`it is reverse biased when the current reverses in the oscil-
`latory circuit comprised of capacitor C, and the induc-
`tor Ly.
`During the commutating interval an inductive load
`connected at the output of the inverter circuit 11 would
`prevent
`the main load current from reversing instantane-
`ously. Diodes Dj, Dg are therefore provided to feed-
`back this current to the direct current supply until the
`load current reverses.
`In the first half of each cycle it
`will be appreciated that during the interval that current
`flows through diode Ds, controlled rectifier SCR, will be
`back-biased, and if conducting, would be turned off. For
`highly reactive loads, the triggering pulse width provided
`by firing circuit was extended in time for the duration of
`the reactive current flow but did not exceed the inverter
`pulse width.
`Continuing with the description of the operation of
`the inverter circuit, the second half of the cycle com-
`mences when a pulse is supplied to the gate of controlled
`rectifier SCR. With controlled rectifier SCR, conduct-
`ing,
`the commutating capacitor C,
`is charged through
`diode Ds, the lower plate of capacitor C, as seen in FIG,
`1, again being negatively charged. The turn-off of con-
`trolled rectifier SCR, is accomplished in the same manner
`as the turn-off of controlled rectifier SCR. Firing cir-
`cuit 22 triggers controlled rectifier SCR; which connects
`the negatively charged plate of the commutating capaci-
`-tor C,
`in circuit with the anode of controlled rectifier
`SCR and also connects the capacitor C; in parallel cir-
`cuit with inductor Ly. Thus, a negative pulse is devel-
`oped across the inductor L, which results in a reverse
`bias being applied across controlled rectifier SCR, and
`it is turned off. Similarly, diode D, feeds back to the
`direct current source reactive power during the commu-
`tating interval, the amount of the feed-back being pro-
`portional to the inductive components of the load.
`Ti will be seen that as the firing circuit 12 applies posi-
`tive trigger pulses alternately to the gates of the con-
`trolled rectifiers SCR;, SCR., the current from the direct
`current supply will flow alternately through the opposite
`ends of the primary winding P of the transformer Ty and
`generate an alternating current voltage across secondary
`winding S,. According to the invention, regulation of
`the output across the secondary winding S, is achieved by
`turning off the conducting controlled rectifier in each
`half cycle to vary the pulse width of the inverter output.
`From the foregoing description of the inverter circuit
`and its operation, it will be seen that the conduction time
`is regulated by firing controlled rectifier SCRs at a pre-
`determined point in each half cycle to connect the com-
`
`LIBERTY EXHIBIT 1028, Page 5
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`mutating capacitor C, in parallel with the inductor L; so
`that an oscillatory pulse is provided to turn off the con-
`ducting controlled rectifier. The pulse width of the out-
`put voltage can be readily varied in response to demands
`of the load thereto. The components used in the turn-off
`circuit arrangement in accordance with the invention have
`low power requirements since they handle only the turn-
`off energy for the controlled rectifier SCRy, SCRg. Fur-
`ther, the arrangement in accordance with the invention is
`readily adaptable to a feed-back type of control.
`It will be understood that the preferred embodimentof
`the invention described herein is intended as an illustra-
`tive example of the invention and that the invention is
`not necessarily limited to such an embodiment thereof.
`It will be apparent that many modifications of the inven-
`tion described herein may be made. As, for example, the
`inverter circuit may be modified so that the positive ter-
`minal and negative terminal connection of the power sup-
`ply are reversed. Further, the inverter circuit arrange-
`ment of the invention is adaptable to three phase appli-
`cations. Itis to be understood, therefore, that I intend by
`the appended claims to cover all such modifications that
`fall within the true spirit and scope of the invention.
`What I claim as new and desire to secure by Letters
`Patent of the United States is:
`1. In a parallel inverter having a first controlled rec-
`tifier and a first primary winding portion connected in
`parallel circuit relation with a second controlled rectifier
`and a second primary winding portion across a direct cur-
`rent supply means, an inductor connected in circuit with
`said first and second controlled rectifier, a commutating
`capacitor, a cut-off controlled rectifier, circuit means
`connecting said cut-off controlled rectifier in series cir-
`cuit relation with said inductor and in parallel circuit re-
`lationship with said commutating capacitor, a first firing
`circuit means to alternately fire said first and second con-
`trolled rectifier, a second firing circuit means connected
`in circuit with said cut-off controlled rectifier to fire said
`cut-off controlled rectifier at a predetermined point in
`seach half cycle after said first and second controlled rec-
`tifiers are fired, said cut-off controlled rectifier when
`triggered causing an oscillatory pulse to be induced across
`said first inductor thereby turning off the conducting one
`of said first and second controlled rectifiers.
`2. The inverter circuit as set forth in claim 1 wherein
`said second firing circuit means includes a first and a
`second diode, each of said diodes having an anode and a
`cathode, the anode ofsaid first diode being connected in
`circuit with the cathode of said first controlled rectifier
`and the anode of said second diode being connected in
`circuit with the cathode of said second controlled rectifier,
`the cathodes being connected in circuit with a unijunction
`transistor oscillator and causing said oscillator
`to be
`energized only when one of said first and second con-
`trolled rectifiers are in a conducting state thereby syn-
`chronizing said secondfiring circuit means with said first
`and second controlled rectifiers.
`3. The inverter circuit as set forth in claim 1 wherein
`a capacitor is connected across each of said first and
`second primary winding portions in order to clamp the
`cathodes of said first and second controlled rectifiers
`to ground when a negative oscillatory pulse is applied to
`the anodes thereof.
`4. In a parallel inverter having a pair of controlled
`rectifiers and a transformer with a secondary and a first
`and a second primary winding portion, one of said con-
`trolled rectifiers and said first winding portion being con-
`nected in parallel circuit relation with the other of said
`controlled rectifiers and said second winding portion and
`in circuit with a direct current supply means, a cut-off
`controlled rectifier having an anode, a cathode and a gate
`electrode, a first inductor connected in circuit with said
`pair of controlled rectifiers, a commutating capacitor
`connected in series circuit relation with the cathode of
`said. cut-off controlled rectifier and in circuit with said
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`10
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`15
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`20
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`first inductor so that when said cut-off controlled rectifier
`is triggered said commutating capacitor is connected in
`parallel circuit relation with said first inductor, said first
`inductor and said capacitor comprising an oscillatory cir-
`cuit, a second inductor comnected in circuit with said
`ccommutating capacitor, a pair of diodes, circuit means
`connecting said diodes in circuit with said pair of con-
`trolled rectifiers and said commutating capacitor so that
`said capacitor is charged during cach half cycle when
`one of said first and second controlled rectifiers is con-
`ducting, firing circuit means connected with the gate of
`said cut-off controlled rectifier, said firing circuit means
`- triggering said cut-off controlled rectifier at a predeter-
`mined point in each half cycle, circuit means alternately
`triggering one of said pair of controlled rectifiers into a
`«conducting state to provide an alternating output across
`the secondary of said transformer, said cut-off controlled
`‘rectifier when in a conducting state connecting said com-
`mutating capacitor in parallel circuit with said first in-
`ductor thereby producing an oscillatory pulse across said
`inductor to turn off the conducting one of said pair of
`controlled rectifiers.
`5. A parallel inverter comprising a transformer having
`a secondary winding and a primary winding split into a
`first primary winding portion and a second primary wind-
`ing portion, a first controlled rectifier connected in series
`circuit relation with said first winding portion, a second
`controlled rectifier connected in series circuit relation
`with said second winding portion, a direct current supply
`‘means, said serially connected first controlled rectifier
`and first winding portion being connected in parallel cir-
`cuit relation with said serially connected second con-
`trolled rectifier and second winding portion, firing circuit
`means connected in circuit with said first and second
`controlled rectifiers to cause a current to flow in one di-
`rection through said first winding portion in one half cycle
`and in an opposite direction through a second winding
`portion in the other half cycle, a turn-off controlled rec-
`tifier having an anode, a cathode and a gate, an inductive
`means connected in circuit with said first and second con-
`trolled rectifiers and in circuit with the anode of said
`cut-off controlled rectifier, a capacitor connected in cir-
`cuit with the cathode of said cut-off controlled rectifier,
`said capacitor and said inductive means comprising an
`oscillatory circuit, circuit means connecting said capaci-
`tor in circuit with said first and second controlled recti-
`fier so that said commutating capacitor is charged in each
`half cycle when one of said first and second controlled
`‘rectifiers is conducting,. firing circuit means connected
`to the gate of said cut-off controlled rectifier and firing
`said cut-off controlled rectifier at a predetermined point
`in each half cycle after one of said first and second con-
`trolled rectifiers is fired to control the pulse width of the
`output across the secondary winding of said transformer.
`6..In a parallel inverter circuit having a transformer
`with a first primary winding portion and a secondary
`primary winding portion inductively coupled with a sec-
`ondary winding, a pair of controlled rectifiers, each of
`said controlled rectifiers having an anode, a cathode and
`a gate, one of said controlled rectifiers and sai