(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2010/0312956A1
`(43) Pub. Date:
`Dec. 9, 2010
`Hiraishi et al.
`
`US 2010.0312956A1
`
`(54) LOAD REDUCED MEMORY MODULE
`(75) Inventors:
`Atsushi Hiraishi, Tokyo (JP);
`Toshio Sugano, Tokyo (JP);
`Fumiyuki Osanai, Tokyo (JP);
`Masayuki Nakamura, Tokyo (JP);
`Hiroki Fujisawa, Tokyo (JP);
`Shunichi Saito, Tokyo (JP)
`Correspondence Address:
`MCGINN INTELLECTUAL PROPERTY LAW
`GROUP, PLLC
`8321 OLD COURTHOUSE ROAD, SUITE 200
`VIENNA, VA 22182-3817 (US)
`(73) Assignee:
`Elpida Memory, Inc., Tokyo (JP)
`
`(21) Appl. No.:
`
`12/801,325
`
`(22) Filed:
`(30)
`
`Jun. 3, 2010
`Foreign Application Priority Data
`
`Jun. 5, 2009 (JP) ................................. 2009-136648
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F 12/00
`(2006.01)
`G06F 3/00
`(52) U.S. Cl. ... 711/105: 710/52; 711/154; 711/E12.001
`(57)
`ABSTRACT
`A memory module includes a plurality of memory chips and
`a plurality of data register buffers mounted on the module
`Substrate. At least two memory chips are allocated to each of
`the data register buffers. Each of the data register buffers
`includes M input/output terminals (M is a positive integer
`equal to or larger than 1) that are connected to the data
`connectors via a first data line and N input/output terminals
`(N is a positive integer equal to or larger than 2M) that are
`connected to corresponding memory chips via second and
`third data lines, so that the number of the second and third data
`lines is N/M times the number of the first data lines. Accord
`ing to the present invention, because the load capacities of the
`second and third data lines are reduced by a considerable
`amount, it is possible to realize a considerably high data
`transfer rate.
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`Micron Technology Inc. et al.
`Ex. 1005, p. 1
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`

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`Patent Application Publication
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`Dec. 9, 2010 Sheet 1 of 29
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`Micron Technology Inc. et al.
`Ex. 1005, p. 2
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`

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`Patent Application Publication
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`Dec. 9, 2010 Sheet 2 of 29
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`US 2010/0312956 A1
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`Micron Technology Inc. et al.
`Ex. 1005, p. 3
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 3 of 29
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`Micron Technology Inc. et al.
`Ex. 1005, p. 4
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 4 of 29
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`US 2010/0312956 A1
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 5 of 29
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`

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`Patent Application Publication
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`Dec. 9, 2010 Sheet 6 of 29
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`US 2010/0312956 A1
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`Micron Technology Inc. et al.
`Ex. 1005, p. 7
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`Patent Application Publication
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 8 of 29
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`Micron Technology Inc. et al.
`Ex. 1005, p. 9
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 9 of 29
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`Ex. 1005, p. 10
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 12 of 29
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 13 of 29
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`Micron Technology Inc. et al.
`Ex. 1005, p. 14
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`Dec. 9, 2010 Sheet 14 of 29
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`Micron Technology Inc. et al.
`Ex. 1005, p. 21
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`Dec. 9, 2010 Sheet 21 of 29
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 24 of 29
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`US 2010/0312956A1
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`Ex. 1005, p. 26
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 26 of 29
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`US 2010/0312956A1
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`Ex. 1005, p. 27
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`

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`Patent Application Publication
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`Dec. 9, 2010
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`Sheet 27 Of 29
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`Micron Technology Inc. et al.
`Ex. 1005, p. 28
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`Patent Application Publication
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`Dec. 9, 2010 Sheet 28 of 29
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`

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`Patent Application Publication
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`Dec. 9, 2010
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`Sheet 29 Of 29
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`

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`US 2010/0312956 A1
`
`Dec. 9, 2010
`
`LOAD REDUCED MEMORY MODULE
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`0001
`0002 The present invention relates to a memory module,
`and particularly relates to a Load Reduced memory module.
`0003 2. Description of Related Art
`0004. A memory module such as a DIMM (Dual Inline
`Memory Module) has a configuration in which a large num
`ber of memory chips such as DRAMs (Dynamic Random
`Access Memories) are mounted on a module Substrate. Such
`a memory module is inserted in a memory slot provided on a
`motherboard, thereby a data transfer is performed between a
`memory controller and the memory module. In recent years,
`because a system requires a considerable amount of memory
`capacity, it is hard to provide the required memory capacity
`with a single memory module. Therefore, in most cases, the
`motherboard includes a plurality of memory slots, so that a
`plurality of memory modules can be mounted on the moth
`erboard.
`0005. However, when a plurality of memory modules are
`mounted on a motherboard, a load capacity of a data line on
`the motherboard increases, resulting in a degradation of Sig
`nal quality. Although it does not cause a serious problem
`when a data transfer rate between the memory controller and
`the memory module is relatively low, it may cause a serious
`problem that the data transfer cannot be performed in a proper
`manner due to the degradation of the signal quality when the
`data transfer rate increases to a certain level. In recent years,
`a data transfer rate as high as about 1.6 Gbps to 3.2 Gbps is
`required, and in order to realize Such a high speed data trans
`fer, it is necessary to reduce the load capacity of the data line
`on the motherboard to a sufficiently low level.
`0006. A so-called Fully Buffered memory module is
`known as a memory module in which the load capacity of the
`data line can be reduced (Japanese Patent Application Laid
`open No. 2008-135597). In a write operation of the Fully
`Buffered memory module, a dedicated chip called an
`Advanced Memory Buffer (AMB) once receives all write
`data supplied from the memory controller, and then the AMB
`Supplies the write data to a predetermined memory chip. A
`read operation is opposite to the write operation, in which all
`read data output from a memory chip is once Supplied to the
`AMB, and then the read data is supplied from the AMB to the
`memory controller. As a result, because the memory control
`ler does not experience the load capacity of each memory
`chip, the load capacity of the data line is considerably
`reduced.
`0007. However, because the AMB employed in the Fully
`Buffered memory module is a sophisticated chip, which is
`relatively expensive, it causes a problem that the cost of the
`memory module considerably increases. Further, because an
`interface between the memory controller and the AMB is
`different from a typical interface between the memory con
`troller and the memory chip in the Fully Buffered memory
`module, it causes another problem that a conventional
`memory controller cannot be used as it is.
`0008 Because of such a background, a memory module
`called a Load Reduced memory module has been recently
`proposed. The Load Reduced memory module is a memory
`module in which a register buffer is used instead of the AMB.
`Because the register buffer is a chip that only buffers signals
`Such as data and command/address, it can be provided at low
`cost. In addition, because an interface between the memory
`
`controller and the register buffer has no difference from the
`typical interface between the memory controller and the
`memory chip in the Load Reduced memory module, the
`conventional memory controller can be used as it is.
`0009. However, from a result of extensive researches on
`the Load Reduced memory module by the present inventors,
`it has been found that, when the data transfer rate is consid
`erably high, simply using a single register buffer is not suffi
`cient to maintain the signal quality on the module Substrate.
`To deal with this problem, the present inventors performed
`further researches on a Load Reduced memory module in
`which a considerably high data transfer rate can be realized.
`The present invention has been achieved as a result of such
`researches.
`
`SUMMARY
`0010. In one embodiment, there is provided a memory
`module comprising: a module Substrate including a plurality
`of data connectors; a plurality of memory chips mounted on
`the module Substrate, each of the memory chips including at
`least one data terminal; and a plurality of data register buffers
`mounted on the module Substrate, each of the data register
`buffers being assigned to at least two memory chips, wherein
`each of the data register buffers includes M first input/output
`terminals each being connected to an associated one of the
`data connectors via a first data line formed on the module
`Substrate, where M is a positive integer equal to or larger than
`1, and N Second input/output terminals each being connected
`to the data terminal of corresponding memory chips via a
`second data line formed on the module substrate, where N is
`a positive integer equal to or larger than 2M, so that number of
`the second data lines is N/M times number of the first data
`lines.
`0011. According to the present invention, because a plu
`rality of data register buffers are mounted on a module sub
`strate and numbers of data lines on a controller side and a
`memory chip side viewed from the data register buffers are
`asymmetrically provided, the load capacity of the data line on
`the module substrate is considerably reduced. This makes it
`possible to enhance the signal quality on the module Sub
`strate. As a result, it is possible to realize a considerably high
`data transfer rate.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0012. The above features and advantages of the present
`invention will be more apparent from the following descrip
`tion of certain preferred embodiments taken in conjunction
`with the accompanying drawings, in which:
`0013 FIG. 1 is a schematic diagram of a configuration of
`a memory module 100 according to an embodiment of the
`present invention;
`0014 FIG. 2 is a block diagram of a configuration of an
`information processing system 10 including the memory
`module 100 according to the present embodiment;
`0015 FIG. 3 is a perspective view of a part of a configu
`ration of a motherboard 21 on which the memory system 20 is
`mounted;
`0016 FIG. 4 is a perspective view of a part of a configu
`ration of a motherboard 21 on which the memory system 20 is
`mounted;
`0017 FIG. 5 is a block diagram of the configuration of the
`data register buffer 300:
`
`Micron Technology Inc. et al.
`Ex. 1005, p. 31
`
`

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`US 2010/0312956 A1
`
`Dec. 9, 2010
`
`0018 FIG. 6 is a block diagram of the configuration of the
`command/address/control register buffer 400;
`0019 FIG. 7 is a connection diagram of the memory mod
`ule 100:
`0020 FIGS. 8A and 8B are schematic diagrams for
`explaining a data transfer path for transferring 1-bit data in the
`memory module 100 according to the present embodiment,
`where FIG. 8A is a layout diagram and FIG. 8B is a connec
`tion diagram
`0021 FIGS. 9A and 9B are schematic diagrams for
`explaining a data transfer pathfortransferring 1-bit data when
`the data lines L1 and L2 are put together in a single data line,
`where
`0022 FIG. 9A is a layout diagram and FIG.9B is a con
`nection diagram;
`0023 FIG. 10 is a timing chart for explaining an interleav
`ing operation using the two data lines L1 and L2.
`0024 FIG. 11 is a timing chart for explaining a read opera
`tion of the memory module 100 according to the present
`embodiment;
`0025 FIG. 12 is a timing chart for explaining the write
`operation of the memory module 100 according to the present
`embodiment;
`0026 FIG. 13 is a flowchart for explaining the initializing
`operation of the memory module 100 at the time of activation;
`0027 FIGS. 14A and 14B are timing charts for explaining
`the write leveling operation between the data register buffer
`300 and the memory chip 200, where FIG. 14A is a timing
`chart at the time of starting the leveling and FIG. 14B is a
`timing chart at the time of ending the leveling;
`0028 FIG. 15 is a timing chart for explaining the read
`leveling operation between the data register buffer 300 and
`the memory chip 200;
`0029 FIGS. 16A and 16B are timing charts for explaining
`the write leveling operation between the memory controller
`12 and the data register buffer 300, where FIG. 16A is a
`timing chart at the time of starting the leveling and FIG. 16B
`is a timing chart at the time of ending the leveling;
`0030 FIG. 17 is a timing chart for explaining the read
`leveling operation between the memory controller 12 and the
`data register buffer 300:
`0031
`FIG. 18 is a timing chart for explaining a problem
`that occurs when performing the ODT operation without
`using the DLL circuit;
`0032 FIG. 19 is a timing chart for explaining a read-to
`read operation when both the ODT function and the DLL
`circuit are in an ON state;
`0033 FIG. 20 is a timing chart for explaining the read-to
`read operation when both the ODT function and the DLL
`circuit are in an OFF state;
`0034 FIG. 21 is a timing chart for explaining a write-to
`write operation when both the ODT function and the DLL
`circuit are in an ON state;
`0035 FIG. 22 is a timing chart for explaining the write
`to-write operation when both the ODT function and the DLL
`circuit are in an OFF state;
`0036 FIGS. 23A and 23B are schematic diagrams for
`explaining a data transfer path for transferring 1-bit data in a
`memory module according to a modification of the present
`embodiment, where FIG. 23A is a layout diagram and FIG.
`23B is a connection diagram;
`0037 FIGS. 24A and 24B are schematic diagrams for
`explaining a data transfer path for transferring 1-bit data in a
`memory module according to another modification of the
`
`present embodiment, where FIG.24A is a layout diagram and
`FIG. 24B is a connection diagram;
`0038 FIG.25 is a schematic diagram of a configuration of
`a memory module according to still another modification of
`the present embodiment;
`0039 FIG. 26 is a plan view showing a configuration of the
`sub-module 500:
`0040 FIG. 27 is a cross section of the sub-module 500 cut
`along a line Y1-Y1' shown in FIG. 26:
`0041
`FIG. 28 is a plan view showing another configura
`tion of the sub-module 500; and
`0042 FIG. 29 is a cross section of the sub-module 500 cut
`along a line Y2-Y2" shown in FIG. 28.
`
`DETAILED DESCRIPTION OF THE
`EMBODIMENTS
`
`0043 Preferred embodiments of the present invention will
`be explained below in detail with reference to the accompa
`nying drawings.
`0044 FIG. 1 is a schematic diagram of a configuration of
`a memory module 100 according to an embodiment of the
`present invention.
`0045. As shown in FIG. 1, the memory module 100
`according to the present embodiment includes a module Sub
`strate 110, a plurality of memory chips 200 mounted on the
`module substrate 110, a plurality of data register buffers 300,
`and a command/address/control register buffer 400.
`0046. In the present embodiment, the memory module 100
`includes thirty-six memory chips 200. When it is necessary to
`specify each of the memory chips, the memory chips are
`respectively represented by memory chips 200-0 to 200-35.
`Furthermore, in the present embodiment, the memory module
`100 includes nine data register buffers 300. When it is neces
`sary to specify each of the data register buffers, the data
`register buffers are respectively represented by data register
`buffers 300-0 to 300-8. On the other hand, the command/
`address/control register buffer 400 is provided as a single
`unit. However, it is not essential to set the number of units of
`the command/address/control register buffer 400 to one, but
`two or more units of the command/address/control register
`buffer 400 can be mounted without any limitation.
`0047. The module substrate 110 is a printed circuit board
`that includes a multilayer wiring. The planar shape of the
`module substrate 110 is substantially rectangle, as shown in
`FIG. 1, with a long side in the X direction and a short side in
`the Y direction. On one side of the module substrate 110 along
`the X direction, which is the long side, a plurality of data
`connectors 120 and a plurality of command/address/control
`connectors 130 are provided. The data connectors 120 and the
`command/address/control connectors 130 are terminals for
`making an electrical connection with a memory controller via
`a memory slot, which will be described later.
`0048. The data connectors 120 are connectors for
`exchanging write data to be written in the memory chip 200
`and read data read from the memory chip 200 between the
`memory module 100 and the memory controller. Although it
`is not particularly limited, the number of pins of the data
`connectors 120 is seventy two in the present embodiment. As
`shown in FIG.1, among the seventy-two data connectors 120,
`data connectors corresponding to the memory chips 200-0 to
`200-19 are arranged in an area 110a that is located substan
`tially right below the memory chips 200-0 to 200-19, and data
`connectors corresponding to the memory chips 200-20 to
`
`Micron Technology Inc. et al.
`Ex. 1005, p. 32
`
`

`

`US 2010/0312956 A1
`
`Dec. 9, 2010
`
`200-35 are arranged in an area 110b that is located substan
`tially right below the memory chips 200-20 to 200-35.
`0049. The command/address/control connectors 130 are
`connectors for Supplying a command signal, an address sig
`nal, a control signal, and a clock signal to be supplied to the
`command/address/control register buffer 400. As shown in
`FIG. 1, the command/address/control connectors 130 are
`arranged in an area 110c that is located between the area 110a
`and the area 110b.
`0050. The memory chips 200 are, for example, DRAMs.
`The memory chips 200-0, 200-2, ... with even branch num
`bers are mounted on one surface of the module substrate 110
`(a first surface), and the memory chips 200-1, 200-3, ... with
`odd branch numbers are mounted on the other surface of the
`module substrate 110 (a second surface). Two corresponding
`memory chips, for example, the memory chips 200-0 and
`200-1 are mounted at positions facing each other across the
`module substrate 110, respectively.
`0051. The memory module 100 according to the present
`embodiment has a so-called 4-Rank configuration. The num
`ber of Ranks indicates the number of memory spaces that can
`be selected in an exclusive manner. Although the same
`address is assigned to each of the Ranks, one of the Ranks is
`selected by exclusively activating a chip select (CS) signal or
`a clock enable (CKE) signal.
`0052. In the present embodiment, four memory chips 200
`constitute a single group (a single set), and the four memory
`chips 200 constituting the single group belong to different
`Ranks from each other. For example, the memory chips 200-0
`to 200-3 constitute a single group, and the memory chips
`200-0 to 200-3 belong to different Ranks from each other.
`0053 As shown in FIG. 1, the four memory chips 200
`constituting a single group are connected to one of the data
`register buffers 300. For example, the group of the memory
`chips 200-0 to 200-3 is connected to the data register buffer
`300-0. Among the memory chips 200-0 to 200-3, the memory
`chips 200-0 and 200-1 that are mounted on the upper side of
`the module substrate 110 are connected to the data register
`buffer 300-0 via a data line L1, and the memory chips 200-2
`and 200-3 that are mounted on the lower side of the module
`substrate 110 are connected to the data register buffer 300-0
`via a data line L2. Anarrow of each of the data lines L1 and L2
`shown in FIG. 1 indicates a line of 1 byte (8bits). Both the
`data lines L1 and L2 are formed inside the module substrate
`110.
`0054 An operation of the memory chip 200 is controlled
`based on the command signal, the address signal, the control
`signal, and the clock signal Supplied from the command/
`address/control register buffer 400. Details on the memory
`chip 200 will be described later.
`0055. A single data register buffer 300 is allocated for
`every four memory chips 200, as described above, so that nine
`data register buffers 300 are arranged along the X direction,
`which is the long side. The data register buffer 300 is a chip
`for buffering write data that is transferred via a data line L0
`and outputting the write data to either one of the data lines L1
`and L2, and at the same time, buffering read data that is
`transferred via either one of the data lines L1 and L2 and
`outputting the read data to the data line L0. The data line L0
`is also formed inside the module substrate 110.
`0056. With the above configuration, the single data regis
`ter buffer 300, the data connectors 120 and the four memory
`chips 200 corresponding to the data register buffer 300 con
`stitute a group G. The memory chips 200, the data register
`
`buffer 300, and the data connectors 120 included in the same
`group are arranged along the Y direction, which is the short
`side, and a plurality of groups G formed in the above manner
`are arranged along the X direction, which is the long side.
`Therefore, a relative positional relationship between each of
`the data register buffers 300 and corresponding four memory
`chips 200 becomes constant in all the groups G.
`0057 With this arrangement, a line length of the data line
`L0 can be shortened, and at the same time, the line length of
`the data line L0 can be made Substantially equal among the
`groups. Similarly, line lengths of the data lines L1 and L2 can
`be shortened, and at the same time, the line lengths of the data
`lines L1 and L2 can be made Substantially equal among the
`groups.
`0.058 An operation of the data register buffer 300 is con
`trolled based on the control signal Supplied from the com
`mand/address/control register buffer 400. Details on the data
`register buffer 300 will be described later.
`0059 Only a single command/address/control register
`buffer 400 is mounted on the module substrate 110. As shown
`in FIG. 1, the command/address/control register buffer 400 is
`arranged at an approximate center portion of the module
`substrate 110 in the X direction, which is the long side.
`0060. The command/address/control register buffer 400
`receives the command signal, the address signal, the control
`signal, and the clock signal (in Some cases, collectively
`referred to as a command/address/control signal and the like)
`that are Supplied from the command/address/control connec
`tors 130 through an input terminal 401, buffers the signals,
`and Supplies the signals to the memory chips 200. At the same
`time, the command/address/control register buffer 400 gen
`erates a control signal. The command/address/control signal
`to be supplied to the memory chips 200 are output through an
`output terminal 402, and the control signal to be Supplied to
`the data register buffers 300 are output through an output
`terminal 403.
`0061 The output terminal 402 is provided at each of the
`left side and the right side of the command/address/control
`register buffer 400. For example, the output terminal 402 at
`the left side is commonly connected to the memory chips
`200-0 to 200-19 except for a control signal that is used to
`select the Rank. That is, the command signal, the address
`signal, and the clock signal are commonly Supplied to the
`memory chips 200-0 to 200-19. Similarly, the output terminal
`403 is provided at each of the left side and the right side of the
`command/address/control register buffer 400. For example,
`the output terminal 403 at the left side is commonly connected
`to the data register buffers 300-0 to 300-4, so that the gener
`ated control signal is commonly supplied to the data register
`buffers 300-0 to 300-4.
`0062. In addition, on the module substrate 110, a termi
`nating resistor R1 is provided at both edges in the X direction
`to prevent a reflection of the command/address signal and the
`control signal output from the command/address/control reg
`ister buffer 400. Furthermore, in order to prevent a reflection
`wave of the command/address/control signal that is input to
`the command/address/control register buffer 400, a stub
`resistor R2 is inserted on a command/address/control line L3
`that connects the command/address/control connectors 130
`and the command/address/control register buffer 400. Details
`on the command/address/control register buffer 400 will be
`described later.
`
`Micron Technology Inc. et al.
`Ex. 1005, p. 33
`
`

`

`US 2010/0312956 A1
`
`Dec. 9, 2010
`
`0063 FIG. 2 is a block diagram of a configuration of an
`information processing system 10 including the memory
`module 100 according to the present embodiment.
`0064. The information processing system 10 shown in
`FIG. 2 includes a CPU 11, a memory control hub (MCH)12,
`and various devices that are connected to the CPU 11 via an
`interface controller hub (ICH) 13.
`0065. The memory module 100 shown in FIG. 1 and a
`graphic controller 15 are connected to the MCH12. As shown
`in FIG. 2, the memory module 100 and the MCH12 constitute
`a memory system 20, where the MCH 12 has a controller
`function for the memory module 100. That is, the MCH 12
`functions as a memory controller for the memory module
`1OO.
`0066. A storage device 16, an I/O device 17, and a BIOS
`(Basic Input/Output System) 18 are connected to the ICH 13.
`The storage device 16 includes a magnetic drive such as a
`hard disk drive, an optical drive such as a CD-ROM drive, and
`the like. The I/O device 17 includes an input device such as a
`keyboard and amouse, an output device Such as a speaker, and
`a network device such as a modem and a LAN. The BIOS 18
`is a kind offirmware that stores therein various pieces of basic
`information about the information processing system 10,
`which is formed by a nonvolatile memory such as a flash
`memory.
`0067 FIG. 3 is a perspective view of a part of a configu
`ration of a motherboard 21 on which the memory system 20 is
`mounted.
`0068. As shown in FIG.3, a memory slot 22 is provided on
`the motherboard 21, so that the memory module 100 is
`inserted in the memory slot 22. On the other hand, a memory
`controller 12 is directly mounted on the motherboard 21. As
`described above, a plurality of memory chips 200 are
`mounted on the memory module 100.
`0069. On a signal path between the memory controller 12
`and the memory chips 200, there exist a line 23 formed on the
`motherboard 21 and the data line L0 and the command/ad
`dress/control line L3 formed on the module substrate 110.
`However, as described above referring to FIG. 1, in the
`memory module 100 according to the present embodiment,
`because the data register buffer 300 is connected to the data
`line L0, the memory controller 12 cannot experience the load
`capacity of the memory chips 200 that exist on the signal path
`beyond the data register buffer 300. Similarly, because the
`command/address/control register buffer 400 is connected to
`the command/address/control line L3, the memory controller
`12 cannot experience the load capacity of the memory chips
`200 that exist on the signal path beyond the command/ad
`dress/control register buffer 400. Therefore, the load capacity
`of the signal path that connects the memory controller 12 and
`the memory module 100 is reduced, making it possible to
`ensure an excellent signal quality even with a high data trans
`fer rate.
`0070 Although only a single memory slot 22 is provided
`on the motherboard 21 in the memory system 20 shown in
`FIG. 3, in actual cases, a plurality of memory slots (for
`example, four) are provided on the memory system, so that
`the memory module 100 is mounted on each of the memory
`slots. As the number of units of the memory module 10