`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`__________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`__________________________
`
`TCL INDUSTRIES HOLDINGS CO., LTD.,
`Petitioners
`v.
`ATI TECHNOLOGIES ULC,
`Patent Owner.
`
`__________________________
`
`PTAB Case No. IPR2024-00366
`
`Patent No. 8,760,454 B2
`__________________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,760,454
`__________________________
`
`

`

`TABLE OF CONTENTS
`
`
`Page
`I.
`INTRODUCTION ....................................................................................... 1
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(B) ......................... 1
`A.
`REAL PARTY IN INTEREST ......................................................... 1
`B.
`RELATED MATTERS ..................................................................... 2
`C.
`NOTICE OF COUNSEL AND SERVICE
`INFORMATION ............................................................................... 3
`PAYMENT OF FEES ................................................................................. 4
`III.
`IV. STANDING ................................................................................................. 4
`V.
`THE BOARD SHOULD NOT EXERCISE ITS DISCRETION
`TO DENY INSTITUTION .......................................................................... 4
`VI. REQUEST FOR INTER PARTES REVIEW OF CLAIMS 1-11
`OF THE ’454 PATENT ............................................................................... 6
`A.
`37 C.F.R. § 42.104(b)(1): Claims for Which IPR is
`Requested .......................................................................................... 6
`37 C.F.R. § 42.104(b)(2): Identification of Prior Art and
`Asserted Grounds for Which IPR is Requested ................................ 6
`Level of Ordinary Skill in the Art ..................................................... 8
`C.
`37 C.F.R. § 42.104(b)(5): Evidence Supporting Challenge .............. 8
`D.
`VII. THERE EXISTS A REASONABLE LIKELIHOOD THAT
`THE CHALLENGED CLAIMS ARE UNPATENTABLE ........................ 9
`A.
`Technology Background ................................................................... 9
`B.
`Description of the Alleged Invention of the ’454 Patent ................ 13
`C.
`Prosecution History of the ’454 Patent and Alleged
`Priority of Invention ........................................................................ 15
`D. Ground #1: Claims 1-11 based on the Lindholm Patents .............. 18
`1.
`The Lindholm ’685 Patent .................................................... 18
`2.
`The Lindholm ’913 Patent .................................................... 21
`3.
`Combining the Lindholm Patents ......................................... 23
`
`B.
`
`- i -
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`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`4.
`Independent Claim 2 ............................................................. 23
`Independent Claim 3 ............................................................. 32
`5.
`Independent Claim 4 ............................................................. 38
`6.
`Independent Claim 5 ............................................................. 39
`7.
`Dependent Claim 6 ................................................................ 40
`8.
`Dependent Claims 7 and 10 .................................................. 40
`9.
`10. Dependent Claim 8 ................................................................ 41
`11. Dependent Claim 9 ................................................................ 42
`12.
`Independent Claim 11 ........................................................... 42
`13.
`Independent Claim 1 ............................................................. 43
`Ground #2: Claims 1-11 based on the Combination of
`Amanatides and Kohn ..................................................................... 44
`1.
`Amanatides ............................................................................ 44
`2.
`Kohn ...................................................................................... 46
`3.
`Combining Amanatides and Kohn ........................................ 47
`4.
`Independent Claim 2 ............................................................. 49
`5.
`Independent Claim 3 ............................................................. 57
`6.
`Independent Claim 4 ............................................................. 61
`7.
`Independent Claim 5 ............................................................. 62
`8.
`Dependent Claim 6 ................................................................ 62
`9.
`Dependent Claims 7 and 10 .................................................. 63
`10. Dependent Claim 8 ................................................................ 64
`11. Dependent Claim 9 ................................................................ 65
`12.
`Independent Claim 11 ........................................................... 65
`13.
`Independent Claim 1 ............................................................. 65
`Ground #3: Claims 1-11 based on the Combination of
`Selzer and Fiske ............................................................................... 66
`
`- ii -
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`E.
`
`F.
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`1.
`Selzer ..................................................................................... 66
`Fiske ...................................................................................... 67
`2.
`Combining Selzer and Fiske .................................................. 68
`3.
`Independent Claim 2 ............................................................. 71
`4.
`Independent Claim 3 ............................................................. 78
`5.
`Independent Claim 4 ............................................................. 80
`6.
`Independent Claim 5 ............................................................. 80
`7.
`Dependent Claim 6 ................................................................ 81
`8.
`Dependent Claims 7 and 10 .................................................. 81
`9.
`10. Dependent Claim 8 ................................................................ 83
`11. Dependent Claim 9 ................................................................ 83
`12.
`Independent Claim 11 ........................................................... 83
`13.
`Independent Claim 1 ............................................................. 84
`VIII. CONCLUSION .......................................................................................... 85
`
`
`- iii -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`PETITIONER’S EXHIBIT LIST
`
`1008
`
`1009
`
`Exhibit # Reference Name
`1001
`U.S. Patent 8,760,454 to Morein et al.
`1002
`Prosecution History of U.S. Patent 8,760,454
`1003
`Declaration of Hanspeter Pfister, Ph.D.
`1004
`Curriculum Vitae of Hanspeter Pfister, Ph.D.
`1005
`U.S. Patent 7,038,685 to Lindholm et al. (“Lindholm ’685”)
`1006
`U.S. Patent No. 7,015,913 to Lindholm et al. (“Lindholm ’913”)
`1007
`John Amanatides and Edward Szurkowski, A Simple, Flexible,
`Parallel Graphics Architecture, In Proceedings of Graphics
`Interface at 155-160 (Canadian Information Processing Society
`1993) published in Proc. Graphics Interface ’93 in May 1993
`(“Amanatides”)
`Les Kohn and Neal Margulis, Introducing the Intel i860 64-bit
`Microprocessor, IEEE, Volume 9, Issue 4, pages 15-30, August
`1989 (“Kohn”)
`Harald Selzer, Dynamic Load Balancing within a High
`Performance Graphics System, In Proceedings of Rendering,
`Visualization and Rasterization Hardware (Eurographics' 91
`Workshop) at 37-53 (Springer-Verlag 1993) published in 1993
`(“Selzer”) [Library of Congress]
`Stuart Fiske and William J. Dally, Thread prioritization: A Thread
`Scheduling Mechanism for Multiple-Context Parallel Processors,
`In Proceedings of First Symposium on High-Performance
`Computer Architecture, 1995 at 210-221 (IEEE 1995) published in
`1995 (“Fiske”)
`IEEE Xplore bibliography page for Fiske, Thread prioritization: A
`Thread Scheduling Mechanism for Multiple-Context Parallel
`Processors, visited on May 11, 2023
`Declaration of Gordon MacPherson re Authentication of Fiske
`(May 11, 2023)
`
`1010
`
`1011
`
`1012
`
`- iv -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`IEEE Xplore bibliography page for Kohn, Introducing the Intel
`i860 64-bit Microprocessor visited on May 11, 2023
`Declaration of Gordon MacPherson re Authentication of Kohn
`(May 11, 2023)
`Initial Determination on Violation of Section 337, Certain
`Consumer Electronics and Display Devices With Graphics
`Processing and Graphics Processing Units Therein, 337-TA-932
`(October 9, 2015)
`Harald Selzer, Dynamic Load Balancing within a High
`Performance Graphics System, In Proceedings of Rendering,
`Visualization and Rasterization Hardware (Eurographics' 91
`Workshop) at 37-53 (Springer-Verlag 1993) published in 1993
`(“Selzer”) [University of California, Berkeley, Library]
`
`1013
`
`1014
`
`1015
`
`1016
`
`
`
`
`
`
`
`
`- v -
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`

`

`
`
`I.
`
`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`INTRODUCTION
`Pursuant to 35 U.S.C. §§ 311-319 and 37 C.F.R. §§ 42.1-.80 & 42.100-.123
`
`et seq., Petitioner respectfully requests inter partes review of claims 1-11 of U.S.
`
`Patent No. 8,760,454. The challenged claims are unpatentable under 35 U.S.C.
`
`
`
`§103 over the prior art publications identified and applied in this Petition.
`
`ATI Technologies ULC (“ATI”) did not invent the first “unified
`
`shader,” which the ’454 patent discloses as a graphics processor that uses a
`
`single processor unit to perform both vertex and pixel operations. Nor did
`
`ATI invent the first unified shader that could be flexibly allocated to pixels
`
`or vertices based on workload. All of this was accomplished years earlier by
`
`Lindholm, Amanatides, Intel, Selzer, and others.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(B)
`Pursuant to 37 C.F.R. § 42.8, Petitioner provides the following mandatory
`
`disclosures:
`
`A. REAL PARTY IN INTEREST
`Petitioner TCL Industries Holdings Co., Ltd. (“TCL”) and TCL Industries
`
`Holdings (H.K.) Limited; TCL Electronics Holdings Limited; TCL Technology
`
`Group Corporation; TTE Corporation; TCL Holdings (BVI) Limited; TCL King
`
`Electrical Appliances (Huizhou) Co., Ltd.; Shenzhen TCL New Technology Co.,
`
`Ltd.; TCL MOKA International Limited; TCL Smart Device (Vietnam) Co., Ltd.;
`
`– 1 –
`
`

`

`
`
`Manufacturas Avanzadas SA de CV; TCL Electronics Mexico, S de RL de CV;
`
`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`TCL Overseas Marketing Ltd., and TTE Technology, Inc. are the real parties-in-
`
`interest.
`
`B. RELATED MATTERS
`Pursuant to 37 C.F.R. § 42.8(b)(2), Petitioner identifies that the ’454 Patent is
`
`currently subject to inter partes review in Realtek Semiconductor Corp. v. ATI
`
`Technologies ULC, No. IPR2023-00922, which was instituted on December 1, 2023
`
`and remains pending. Petitioner files herewith a motion for joinder of the instant
`
`Petition with the petition in IPRR2023-00922.
`
`Petitioner identifies that the ’454 Patent is the subject of a patent
`
`infringement lawsuit brought by the Patent Owner, ATI Technologies ULC,
`
`against Petitioner in the following cases that may affect or be affected by a decision
`
`in this proceeding:
`
`• Advanced Micro Devices, Inc. et al. v. TCL Industries Holdings
`
`Co., LTD., et al., Case No. 2:22-cv-00134, now pending in the
`
`Eastern District of Texas. This action is stayed “until final
`
`resolution of Investigation No. 337-TA-1318.” (Dkt. 65)
`
`The ’454 Patent was previously asserted in Certain Graphics Systems,
`
`Components Thereof, and Digital Televisions Containing The Same, Inv. No. 337-
`
`TA-1318, pending in the U.S. International Trade Commission, but the asserted
`
`– 2 –
`
`

`

`
`
`patent claims were terminated by Order No. 10 on July 14, 2022, upon motion of
`
`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`ATI. The target date for completion of the investigation is January 23, 2024.
`
`The ’454 Patent was previously the subject of:
`
`• IPR2017-01225, which was terminated prior to an institution
`
`decision;
`
`• Certain Graphics Systems, Components Thereof, and Consumer
`
`Products Containing Same, Inv. No. 337-TA-1044, but the
`
`investigation as to the asserted claims was terminated prior to a
`
`determination on the merits; and
`
`• Case No. 1:17-cv-00065 in the District of Delaware, which was
`
`dismissed October 18, 2017.
`
`C. NOTICE OF COUNSEL AND SERVICE INFORMATION
`Lead counsel: John Schnurer, Reg. No. 52, 196.
`
`Back-up counsel: Yun (Louise) Lu, Reg. No. 72,766; Kevin J. Patariu, Reg.
`
`No. 63,210; Kyle R. Canavera, Reg. No. 72,167.
`
`These attorneys can be reached by mail at Perkins Coie LLP, 11452 El
`
`Camino Real, Suite 300, San Diego, CA 92130; by phone at (858) 720-5700; and
`
`by fax at (858) 720-5799.
`
`Petitioners consent to electronic service. All services and communications
`
`to the attorneys listed above may be sent to: PerkinsServiceTCL-
`
`– 3 –
`
`

`

`
`
`AMDIPRs@perkinscoie.com. A Power of Attorney is being filed concurrently.
`
`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`III. PAYMENT OF FEES
`The fees pursuant to 37 C.F.R. §42.103 are being paid, and the Patent Trial
`
`and Appeal Board (“the Board”) is hereby authorized to charge any further fees to
`
`Perkins Coie, LLP: Deposit Account 50-0665.
`
`IV. STANDING
`Pursuant to 37 C.F.R. §42.104(a), Petitioner certifies that (1) the ’454 Patent
`
`is available for inter partes review; and (2) Petitioner is not barred or estopped
`
`from requesting inter partes review of claims 1-11 of the ’454 Patent on the
`
`grounds identified in this Petition. T his Petition is timely filed under 35 U.S.C.
`
`§ 315(b), at least because of the concurrent request for joinder under § 315(c).
`
`V. THE BOARD SHOULD NOT EXERCISE ITS DISCRETION TO
`DENY INSTITUTION
`Although the ’454 Patent is asserted in a case in the Eastern District of
`
`Texas, there is no basis to deny institution under §314. This proceeding is still in
`
`its very early stages. Petitioner has not filed an answer. The action has been stayed
`
`at the request of the Patent Owner “until final resolution of Investigation No. 337-
`
`TA-1318.” Accordingly, there is no effective trial date and none will be set until
`
`sometime after January 23, 2024, the target date for completion of the
`
`Investigation, at the earliest. Petitioner filed this Petition and the concurrent
`
`– 4 –
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`

`

`
`
`
`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`motion for joinder within one month of institution of IPR2023-00922 as
`
`required by 37 CFR §42.122. Petitioner will join that ongoing proceeding
`
`and does not expect to seek any modification to the schedule already entered
`
`in that proceeding. Thus, the first, second, third, fifth and sixth Fintiv factors
`
`strongly favor institution.
`
`The Board also should exercise its discretion to institute under §325(d)
`
`because the Examiner neither cited nor discussed the references that form the second
`
`and third grounds for unpatentability. Moreover, Patent Owner did not address the
`
`Examiner’s rejection based on the ’685 patent on its merits and was not able to
`
`overcome the rejection on its merits. And as discussed below, ATI’s evidence of
`
`prior invention was found inadequate in the 337-TA-923 ITC Investigation.
`
`Finally, the Board should not exercise its discretion to deny institution under
`
`§314(a) based on IPR2017-01225. The prior petition was filed April 3, 2017, by a
`
`different petitioner (LG), about six years before Petitioner was accused of infringing
`
`the ’454 patent and is alleged to have notice of ATI’s claims of infringement. See
`
`Unified Patents Inc. v. Bradium Technologies LLC, IPR2018-00952, Institution
`
`Decision at 15-24 (December 20, 2018).
`
`– 5 –
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`
`
`VI. REQUEST FOR INTER PARTES REVIEW OF CLAIMS 1-11 OF
`THE ’454 PATENT
`37 C.F.R. § 42.104(b)(1): Claims for Which IPR is Requested
`A.
`Petitioner requests that the Board finds unpatentable Claims 1-11 of the ’454
`
`Patent (the “Challenged Claims”). Such relief is justified as the alleged invention
`
`of the ’454 Patent was described by others prior to the effective filing date of the
`
`’454 Patent.
`
`B.
`
`37 C.F.R. § 42.104(b)(2): Identification of Prior Art and Asserted
`Grounds for Which IPR is Requested
`The prior art relied upon in this Petition is:
`
`U.S. Patent No. 7,038,685 (“’685 patent”) was filed on June 30, 2003 and
`
`issued on May 2, 2006. EX1005. It is therefore prior art to the ’454 patent under at
`
`least 35 U.S.C. § 102(e).
`
`U.S. Patent No. 7,015,913 (“’913 patent”) was filed on June 27, 2003 and
`
`issued on March 21, 2006. EX1006. It is therefore prior art to the ’454 patent
`
`under at least 35 U.S.C. § 102(e).
`
`John Amanatides and Edward Szurkowski, A Simple, Flexible, Parallel
`
`Graphics Architecture, In Proceedings of Graphics Interface at 155-160 (Canadian
`
`Information Processing Society 1993) (“Amanatides”) was published in Proc.
`
`Graphics Interface ’93 in May 1993. EX1007. It is therefore prior art to the ’454
`
`Patent under at least 35 U.S.C. § 102(a) and (b).
`
`– 6 –
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`

`

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`
`
`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`Les Kohn and Neal Margulis, Introducing the Intel i860 64-bit
`
`Microprocessor, IEEE, Volume 9, Issue 4, pages 15-30, August 1989 (“Kohn”).
`
`EX1008, EX1013, EX1014. It is therefore prior art to the ’454 patent under at least
`
`35 U.S.C. § 102(a) and (b).
`
`Harald Selzer, Dynamic Load Balancing within a High Performance
`
`Graphics System, In Proceedings of Rendering, Visualization and Rasterization
`
`Hardware (Eurographics' 91 Workshop) at 37-53 (Springer-Verlag 1993)
`
`(“Selzer”) was published in 1993. EX1009, EX1016. It is therefore prior art to the
`
`’454 patent under at least 35 U.S.C. § 102(a) and (b).
`
`Stuart Fiske and William J. Dally, Thread Prioritization: A Thread
`
`Scheduling Mechanism for Multiple-Context Parallel Processors, In Proceedings
`
`of First Symposium on High-Performance Computer Architecture, 1995 at 210-
`
`221 (IEEE 1995) (“Fiske”) was published in 1995. EX1010, EX1011, EX1012. It
`
`is therefore prior art to the ’454 patent under at least 35 U.S.C. § 102(a) and (b).
`
`The one-year time bar under pre-AIA 35 U.S.C. §102(b) is measured
`
`from the effective U.S. filing date of the ’454 Patent, which is no earlier
`
`than November 20, 2003.
`
`Inter partes review is requested on the following grounds:
`
`Ground 1: The Challenged Claims are rendered obvious under 35
`
`U.S.C. § 103(a) by the ’685 patent in combination with the ’913 patent.
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`– 7 –
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`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
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`Ground 2: The Challenged Claims are rendered obvious under 35
`
`U.S.C. § 103(a) by Amanatides in combination with Kohn.
`
`Ground 3: The Challenged Claims are rendered obvious under 35
`
`U.S.C. § 103(a) by Selzer in combination with Fiske.
`
`C. Level of Ordinary Skill in the Art
`A person of ordinary skill in the field, at the time the ’454 patent
`
`was effectively filed, would have had at least a four-year degree in
`
`electrical engineering, computer engineering, computer science, or a
`
`related field and two years relevant experience in the graphics processing
`
`field including developing, designing, or programming hardware for
`
`graphics processing units.
`
`37 C.F.R. § 42.104(b)(5): Evidence Supporting Challenge
`D.
`The Declaration of Dr. Hanspeter Pfister, Ph.D. (EX1003) and other
`
`supporting evidence in the Exhibit List are filed herewith. Dr. Pfister’s
`
`background and qualifications, and the information provided to him, are
`
`discussed in EX1004.
`
`
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`– 8 –
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`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
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`
`
`VII. THERE EXISTS A REASONABLE LIKELIHOOD THAT THE
`CHALLENGED CLAIMS ARE UNPATENTABLE
`A. Technology Background
`The ’454 patent is directed to the typical functions of a graphics
`
`processor, which is used to generate complex shapes and structures to be
`
`displayed on a screen. EX1001 at 1:38-48; EX1003 ¶37. A graphics
`
`processor converts a 3D object or scene (comprised of points in 3D space
`
`called “vertices”) into a 2D image to be displayed on a computer screen
`
`(comprised of “pixels”). Id. Generally, 3D graphics processing starts with
`
`creating a mathematical model of each object. Id. The model is then
`
`processed through a series of steps, referred to as a “graphics processing
`
`pipeline,” that renders the scene as a 2D image on a display:
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`– 9 –
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`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
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`
`
`
`
`
`In most cases, 3D objects are conceptualized as a series of triangles
`
`(called “primitives”) that cover the surface of an object, such as a teapot:
`
`
`
`EX1003 ¶38.
`
`Each point of the primitive is called a “vertex,” and each vertex has
`
`– 10 –
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`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`certain properties, which are represented as data. Id. For example, a vertex
`
`includes not just its location, but may also include other information, such
`
`as the color of the object and its material properties (e.g., whether it is
`
`reflective). EX1003 ¶¶39-40. A vertex processor (the “front end” of the
`
`graphics pipeline) transforms these vertices from 3D space into 2D space
`
`and determines how lighting and other conditions in the 3D scene impact
`
`the color of the vertices. Id.
`
`After the vertex processing, a step called rasterization determines
`
`what pixels on the 2D screen are covered by each
`
`primitive (at right). Id. ¶¶41-45. At least one
`
`“fragment” is generated for each pixel on the screen
`
`(as a result, the terms “fragment” and “pixel” are
`
`sometimes used interchangeably). Id. The initial values of each pixel
`
`(such as its color) are calculated using the vertex data and interpolation. Id.
`
`A pixel processor (the “back end” of the graphics pipeline) then performs
`
`additional operations on the pixels, which includes determining the final
`
`color of each pixel. Id. All of this information is gathered together for the
`
`final image to be displayed on a screen. Id.
`
`– 11 –
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`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
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`
`
`Conventionally, separate dedicated vertex processors and pixel
`
`processors (sometimes referred to as “shaders”) were used to process
`
`vertex data and pixel data. EX1003 ¶46. Before the ’454 patent was filed,
`
`inventors such as Erik Lindholm, John Amanatides, and Harald Selzer
`
`recognized that the conventional approach of using separate and dedicated
`
`vertex and pixel processors created inefficiencies. Separate, fixed function
`
`vertex and pixel processors could not adapt to the varying needs of each
`
`image, some of which have a lot of vertex data to process while others
`
`have more pixel data. Id. at ¶¶47-48. This was inefficient, as either vertex
`
`processors or pixel processors were often idle while the other type of
`
`processor became backlogged. Id.
`
`What was needed was a way to process both vertex and pixel data
`
`through a single piece of hardware that could process either data type and
`
`then prioritize or balance a common set of resources between the two
`
`– 12 –
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`

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`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
`
`sample types. The inventor of the ’685 and ʼ913 Patents, Erik Lindholm,
`
`solved the problem. Mr. Lindholm invented a multithreaded processor
`
`unit that could process both vertex and pixel graphics data (sometimes
`
`called a “unified shader”) depending on available resources and priorities.
`
`Id. ¶48. The invention also allowed the multithreaded processor unit to
`
`dynamically balance or control the number of threads processing vertices
`
`or pixels during operation, depending on the available resources.
`
`Amanatides and Selzer similarly invented unified shaders that could
`
`process vertices and pixels in the same processing units based on
`
`workload, available resources, and processing priorities.
`
`B. Description of the Alleged Invention of the ’454 Patent
`Similar to the Lindholm patents, the ’454 patent notes that one
`
`drawback to separate vertex and pixel shader hardware was the increased
`
`footprint required on the processor. EX1003 ¶¶49-50. Thus, the ’454
`
`patent uses the same piece of hardware, which it also terms a “unified
`
`shader,” to run both vertex shader programs and pixel shader programs.
`
`EX1001 at 2:58-3:3. The patent defines “unified shader” as a shader that is
`
`“configured to perform both vertex and pixel operations.” Id. at 3:10-12.
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`Figure 4 of the ’454 patent is illustrative of the unified shader.
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`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
`PTAB Case No. IPR 2024-00366
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`Within the unified shader is a general-purpose register block for
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`storing vertex and pixel data to be processed. Id. at 4:29-39. The
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`specification discloses that there was nothing inventive about the hardware
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`comprising the “unified shader” itself, which is described as being “a
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`processor (e.g., CPU) 96.” Id. at 4:30-34. In one embodiment, the
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`processor 96 is “logically partitioned into two sections,” one of which is
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`Petition for Inter Partes Review of U.S. Pat. No. 8,760,454
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`configured to perform 32-bit floating point arithmetic operations and
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`another of which is configured to perform scalar operations (e.g., log,
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`exponent, reciprocal square root). Id. It was known to a POSITA that
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`vertex processing typically required floating point operations and pixel
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`processing required scalar operations. EX1003 ¶¶54-55. The processor
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`unit within the unified shader can process vertex data concurrently with
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`pixel data and alternate between the two types of operations. EX1001 at
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`5:32-36; 6:36-41. Within the unified shader, the unit that maintains
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`instructions for performing vertex and pixel operations is called the
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`sequencer. Id. at 4:52-5:5. An arbiter circuit is used to determine which of
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`a plurality of inputs, such as vertices or pixels, are selected for processing
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`by the unified shader. Id. at 4:13-28. This determination might be made
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`by giving priority to vertex processing based on whether the general-
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`purpose registers have enough available space to store incoming vertex
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`data, and if not, pixel operations are continued. Id. at 5:41-52.
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`C.
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`Prosecution History of the ’454 Patent and Alleged Priority of
`Invention
`The application that led to the ’454 patent was filed on May 17,
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`2011, and issued on June 14, 2014. The ’454 patent claims priority to an
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`application filed November 20, 2003. During prosecution, the Examiner
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`rejected the claims of the ’454 patent three times as anticipated by the
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`Lindholm ’685 patent. EX1002. ATI never addressed the Lindholm
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`rejection on its merits and was not able to overcome the rejection on its
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`merits. Id. Instead, ATI filed an inventor declaration under 37 CFR 1.131,
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`which the Examiner found sufficient in an Office Action dated August 8,
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`2013, without substantive analysis.
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`However, ATI’s evidence of prior invention was subsequently found
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`insufficient to antedate the ’685 patent after a full adjudication on the
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`merits. In Certain Consumer Electronics and Display Devices with
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`Graphics Processing and Graphics Processing Units Therein, Judge Pender
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`found that ATI was unable to prove conception prior to the effective filing
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`date of the ’685 patent, June 30, 2003, or actual reduction to practice. Inv.
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`No. 337-TA-932, Final Initial Determination (October 9, 2015) (EX1015).
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`For example, Judge Pender rejected ATI’s evidence of earlier conception of
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`claim limitations directed to the processing of graphics data by assigning a
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`priority to processing vertices or pixels, as well as the allocation of threads
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`to vertices and pixels based on such a priority. Id. at 140-145. Judge Pender
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`also found that ATI’s evidence could not support an earlier invention date
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`for load balancing, i.e., determining whether to process pixel data or vertex
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`data based on workload. Id. Judge Pender further found ATI’s documentary
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`evidence of prior conception of its “sequencer” to be non-enabling. Id. In
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`addition, Judge Pender found ATI’s evidence insufficient to show actual
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`reduction to practice, i.e., that the relevant features disclosed in the early
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`R400 development documents were actually implemented in the later Xenos
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`chip. Id. at 145-149.1
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`As Judge Pender already adjudicated, ATI cannot prove prior
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`invention as to the features claimed in the ’454 patent. Petitioner anticipates
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`the evidence will fail to antedate the ’685 patent or the ’913 patent because
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`ATI cannot show prior conception, actual reduction to practice, and
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`sufficient diligence in reduction to practice as to the claims of the ’454
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`patent.
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`1 In a later decision, the Federal Circuit held that ATI met its burden of
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`antedating the ’685 patent, but only as to claims of three other patents—not the
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`’454 patent. Those patents did not claim a priority for processing vertices or pixels,
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`load balancing between processing vertices and pixels, and other limitations of the
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`challenged claims of the ’454 patent. ATI Technologies ULC v. Iancu, 920 F.3d
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`1362, 1366-68 (Fed. Cir. 2019).
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`D. Ground #1: Claims 1-11 based on the Lindholm Patents
`The Lindholm ’685 Patent
`1.
`The ’685 patent describes the same unified shader architecture
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`claimed in the ’454 patent and discloses numerous ways to optimize the
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`allocation of resources when simultaneously performing vertex and pixel
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`operations. EX1003 ¶71.
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`Figure 1 of the ʼ685 patent depicts the basic components of a graphics
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`processor that includes a programmable graphics processing pipeline, which
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`can be programmed to operate on graphics data called “samples,” such as
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`vertices and primitives. Id. at 3:59-64. The programmable graphics
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`processing pipeline includes one or more execution pipelines as shown in
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`Figure 2:
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`EX1005 at Fig. 2 and 4:36-41.
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`Each execution pipeline contains one or more multithreaded
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`processing units. EX1005 at 4:27-29. Each multithreaded processing unit
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`accepts samples for processing when a thread is available, sending a signal
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`to the Vertex Input Buffer or to the Pixel Input Buffer when a vertex or a
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`pixel can be accepted for processing. Id. at 4:31-36, 5:23-25. Figure 4
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`shows certain details of the multithreaded processing unit:
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`Id. at Fig. 4.
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`Each thread can process any sample type, such as a vertex or a pixel
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`(fragment), which enables the multithreaded processing unit to
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`simultaneously process vertices and pixels. Id. at 6:52-59; 9:39-49; claims
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`1, 13, 23, 25, 36, 41, 43. The Thread Control Unit uses a thread allocation
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`priority to determine whether to assign a vertex or pixel to an available
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`thread, which priority may be fixed, programmable, or dynamic. EX1005 at
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`6:40-7:36. After samples are assigned to threads, the Thread Selection Unit
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`uses a “thread execution priority assigned to each thread type” (e.g., vertex
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`or pixel) to determine the order of processing. Id. at 7:56-8:32. The thread
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`execution priority may also be fixed, programmable, or dynamic. Id. at
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`7:60-61. See EX1003 ¶¶72-77.
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`The Lindholm ’913 Patent
`2.
`The Lindholm ’913 patent was filed just three days before the
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`Lindholm ’685 patent and is directed to the same unified shader architecture.
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`EX1003 ¶¶78-79. The ’913 patent describes how the unified shader can
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`quickly switch