http://www.wiley.com/college/sze
`
`on=|
`5. M. Sze is UMC Chair Professor of the National Chiao Tung University and President of the
`=
`National Nano Device Laboratories, Taiwan, 8.0.C. For many years he was a memberof the tech-
`wm
`nical staff at Bell Laboratories. Professor Sze is the co-inventor of the nonvolatile semiconductor
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`‘Se
`
`Physics
`
`Technology
`
`2nd Edition
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`TK 7871
`65
`. 89883
`
`2001
`
`COPY i
`
`LIBRARY OF CONGRESS
`
`ii
`PUAN
`
`
`
`
`
`
`
`; the
`This eagerly-anticipated revision offers more than 50% new
`0 008 885 083 A
`multitude of important recent discoveries and advances in device physics and integrated circuit
`
`The bookoffers a thorough introduction to physical principles of modern semiconductor devices
`and their fabrication technology. Readers are presented with theoretical and practical aspects of
`every step in device characterizations and fabrication, with an emphasis on integratedcircuits.
`
`The materialis divided into three parts:
`the basic properties of semiconductor materials, emphasizing silicon and gallium arsenide
`the physics and characteristics of semiconductor devices bipolar, unipolar special microwave
`and photonic devices
`the latest processing technologies, from crystal growth to lithographic pattern transfer
`
`Each chapter is presented in a logical manner enabling readers to learn all important devices
`from a single source. Plus, the book covers historical developments of devices and technologyin
`the last 100 years. Readers gain a sound perspective on the past and a foundation for projecting
`
`ABOUT THE AUTHOR
`
`memory. He has written numerous texts on devices physics, including PHYSICS OF SEMICONDUCTOR
`DEVICES, considered a reference classic. In 1991, he received the IEEE J. J. Ebers award for his “fun-
`
`damental and pioneering contributions...” He received his PhD in solid-state electronics from
`Stanford University in 1963.
`
`JOHN WILEY & SONS, INC.
`New York / Chichester
`
`Weinheim/Brisbane
`
`ISBN O-4?L-J34dd?e-?
`90000>
`
`|
`
`olPso47 1333722
`
`|
`
`ONSEMI EXHIBIT 1042, Page 1
`
`

`

` TT
`
`2 ND EDITION
`
`
`Semiconductor
`Devices
`
`Physics and Technology
`
`
`S. M. SZE
`UMCChair Professor
`National Chiao Tung University
`National Nano Device Laboratories
`Hsinchu, Taiwan
`
`
`
`
`
`JOHN WILEY & SONS,INC.
`
`ONSEMI EXHIBIT 1042, Page 2
`
`

`

`Marketing Manager Katherine Hepburn > :
`Production Services Manager
`Jeanine Furino ~~~
`Production Fditor Sandra Russell
`Designer Harald Nolan
`Production Management Services Argosy Publishing Services
`
`
`
`
`
`=!yy
`
`Cover Photography: A transmission-electron micrographofa floating-gate nonvolatile semicon-
`ductor memorywith a magnification of 100,000times. (Photography courtesy of George 'T. T.
`Sheng.) Fora discussion of the device, see Chapters 1, 6, and 14.
`
`This book was typeset in Nete Caledonia by Argosy Publishing and printed and bound by
`R. R. Donnelley and Sons, Inc. (Willard). The cover was printed by The Lehigh Press.
`
`The paperin this book was manufactured bya mill whose forest management programsinclnde
`sustained yield harvestingofits timberlands. Sustainedyield harvesting principles ensure that
`the numberoftrees cut each year does not exceed the amountof new growth.
`
`The bookis printed on acid-free paper.
`
` Acquisitions Editor William Zobrist.
`
`Copyright © 1985, 2002 byJohn Wiley & Sons, Inc. All rights rights reserved.
`Nopart of this publication may be reproduced, storedin a retrieval system or transmitted in any form ar by
`any meaus, electronic, mechanical, photocopying, recording, scamming, or otherwise, except as permitted
`underSections LO7 or 108 of the 1976 United States Copyright Act, without cither the prior written permis-
`sion of the Publisher or anthorization through payment ofthe appropriate per-copyfee to the Copyright
`Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (508) 730-8400, fax (508) 750-4470, Requests
`to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons,
`Inc. 605 Third Avenue, New York, NY 10158-0012, (212) 850-6008, E-mail: PERMREQ@WILEY.COM. To
`order books or for custome service call 1-800-CALL-WILEY(225-5943).
`
`Library of Congress Cataloging in Publication Data:
`Sze, S. M., 1936-
` Seir
`‘ondnetordevices, physics and technology/S.M. $ze.—2nd ed.
`p- cin.
`Includes bibliographical references andindex.
`ISBN 0-471-33372-7 (cloth: alk. paper)
`1, Semicouductors.1. Title.
`TK7871,85 $9883 2001
`621.3815'2—de21
`
`ISBN 0-471-33372-7
`Printed in the United States of America
`10987654321
`
`2001026003
`
`In Memory of My Mentors
`Academia Sinica
`
`Dr. L. J. Chu
`
`Dr. R. M. Ryder
`
`Bell Laboratories
`
`
`
`ONSEMI EXHIBIT 1042, Page 3
`
`

`

`
`
`!
`
`|
`
`488
`
`Chapter 13. Impurity Doping
`
`FOR SECTION 13.5
`
`IMPLANT DAMAGE AND ANNEALING
`
`16. 1fa50 keV boronionis implanted intothe silicon substrate, calculate the damage de:“iisity,
`Assumesilicon ator density is 5.02 x 10°? atoms/cin?, the silicon displacement enerev is
`15 eV. the range is 2.5 nn, and the spacing betweensiliconlattice plane is 0.25 nm,
`V7. Explain why high-temperature RTA is preferable to low-temperature RTA for defect-(ree
`shallow-junction formation,
`18. Estimate the implant dose required to reduce a p-chanmel thresholdveltage by 1 Vif the
`gate oxide is 4 nmthick, Assume that the implantvoltage is adjusted so that the peak of
`the distribution accurs at theoxicle-silicon interface Thus, half of the inyalant goesinto
`thesilicon, Further, assume that 90%ofthe implanted ionsin thesilicon arc clectrically
`activated by the annealing process. These assumptions allow45% ofthe implantedions to
`be usedfor threshold acljusting. Also assume that all of the charge in thesilicon is effoc-
`livelyat the silicon oxide interface.
`FOR SECTION 13.6
`IMPLANTATION-RELATED PROCESSES
`
`19, We wouldlike to form 0.1 jim deep, heavily doped junctions forthe source and drain
`regions of a submicron MOSFET. Comparethe options that are available to introduce
`andactivate dopant forthis application. Which option would you recommendand why?
`
`20. Whenan arsenic implant at 100 keVis used and the photoresist thickness is 400 nm, find
`ve effectiveness ofthe resist maskin preventing the transmission of ions (R, = 0.6 jum,
`~ 0.2 fim}. Tithe resist thickness is changed to 1 pm, calculate the maskingefficiency.
`21. a reference to Ex. 4, what thickness of SiO, is required to mask 99.999%ofthe
`:
`Lg
`implantedions
`
`|
`
`|
`
`|
`
`|
`
`CHAPTER
`
`
`
`1
`t d D
`t
`|
`eC V | C e S
`n C g r a eC
`
`
`14.1 PASSIVE COMPONENTS
`14.2 BIPOLAR TECHNOLOGY
`14.3 MOSFET TECHNOLOGY
`14.4 MESFET TECHNOLOGY
`14.5 CHALLENGES FOR MICROELECTRONICS
`SUMMARY
`
`
`:
`,
`an
`.
`;
`Microwave, photonic, and powerapplications generally employdiscrete devices. For exam-
`pics
`\)
`oe cae
`pres
`dlc, an IMPATTdiode is used as a microwave generator, an injection laser as an optical
`source, and a thyristoras a high-powerswitch. Towever, most electronicsystems are built
`?
`é
`?
`ontheintegrated circuit (IC), which is an ensemble ofboth active (c.g., tansistor) and
`passive devices (e.g., resistor, capacitor, and inductor) formed onandwithin a single-crys-
`tal semiconductorsubstrate and interconnected by a metallization pattern.! 1Cs have cnor-
`mous advantages overdiscrete devices connected by wire bondings. The advantages
`includes (a) reduction oftheinterconnection parasitics, because an IC with multilevel
`mnetallization can substantially reduce the overall wiring length, (b) full utilization of semi-
`conductor waler’s “real estate,” because devices can be closely packedwithin an IC chip,
`and (c) drastic reduction in processing cost, because wire bonding is a time-consuming
`anc error-prone operation.
`In this chapter we combine the basic processes described in previous chapters to
`fabricateactive andpassive components in an IG. Because the key clement ofan ICis
`the transistor, specific processing sequences are developedto optimize its performance.
`We considerthree major ICtechnologies associated with the three transistor families:
`the bipolar transistor, the MOSFET, and the MESI'FT.
`Specifically, we coverthe following topics:
`*
`‘The design and fabrication of IC resistor, capacitor, and inductor.
`* Theprocessing sequence for standard bipolartransistor and advancedbipolar
`devices,
`
`
`
`* The processing sequence for MOSFETwithspecial emphasis on CMOSand
`
`nemory deviccs.
`* Theprocessing sequence for high-performance MESFET and monolithic
`microwave IC,
`
`* The major challenges for future microclectronics, including ultrashallowjrme-
`tion, ultrathin oxide, newinterconnection materials, low power dissipation,
`andl isolation.
`
`
`
`
`
`ONSEMI EXHIBIT 1042, Page 4
`
`

`

` 490
`
`Figure 1 illustrates the interrelationship between the major process steps used for
`IC fabrication. Polished wafers with a specific resistivity andorientation are used ay the
`starting material. ‘be film formation steps include thermally grown oxide films, deposite“<
`polysilicon, dielectric, and metalfilms (Chapter 11). Filmformationis often followed hy:
`lithography (Chapter 12) or impurity doping (Chapter 13). Lithographyis generally fol.
`lowedbyetching, whichiin tunis often followedby another impurity dopingorfilmfor.
`
`mation. The final IC is made by sequentially trausterring the patterns from each mask
`|x—______+|- 2 to 10 Lun
`level bylevel, onto the surface of the semiconductor water,
`,
`Bipolar
`After processing, cach wafer contains hundreds ofidentical rectangularchips (or dice},
`transistor
`typically between 1 and 20 mmoneachside, as shownin Fig, 2a. Thechips are sepa-
`Collector
`rated lysawing orlaser cutting; Figure 26 shows a separatedchip. Schematic top views
`of a single MOSFETandasingle bipolartransistor arc shown in Fig. 2c to give some
`perspective of therelative size of a component in an IC chip. Prior to chip separation,
`each chipis electrically tested. Defective chips are usually marked with a dab ofblack
`ink. Good chips are selected and packagedto provide an appropriate thermal, electrical,
`andinterconnection environmentfor electronic applications.?
`TC chips ney contain from a few components (transistors, diodes, resistors. capaci-
`tors, etc.) to as manyasabillion or more. Since the invention of the monolithic IC in
`1959, the munherof components on a state-of-the-art IC chip has grown exponentially,
`We usually refer to the complexity of an ICassinall-scale integration (SSL)lor up to 100
`compoucuts per chip, medium-scale integration (MSI) tor up to 1000 components per
`chip, large-scale integration (IS!) for up to 100,000 components per chip, very-large-
`scale integrated (VLSI) lor up to 10" components per chip, and. ultra large-scale inte-
`gration (ULST) for larger numbers of components per chip. In Section 11.3, we show
`two ULSI chips, a 32-bit microprocessorchip, which contains over 42 iillion compo-
`neuts, and a 1 Gbit dynamic random access memory (DRAM) chip, which contains over
`2 billion components.
`
`
`
`
` —] te lum
`
`
`1to 20 mm
`
`Rice
`
`{h}
`
`7
`Base
`
`y
`Enilier
`(e)
`
`Size corupurison of a wafer to individual componcats. (@) Semiconduetor wafer, (b) Chip
`Fig. 2
`{ci} MOSFET andbipolar transistor.
`
`14.1 PASSIVE COMPONENTS
`
`14.1.1.
`
`The Integrated-Circuit Resistor
`
`‘Toform an IC resistor, we can deposite a resistive Inver on asilicon substrate, then pat-
`tern the layerby lithographyandetching, We can also define a windowinasilicon diox-
`ide layer grown theemally onasilicon substrate andthen iuplant (or diffuse) impurities
`
`ofthe opposite conductivi
`type into the water. Figure 3 shows the top and cross-see-
`tional views of Avo resistors formed by the latter approach: one has a meander shape and
`the other Tuas a bar shupe.
`Considerthe bar-shapedresistorfirst. ‘he differential conductance dCofa thin laver
`ofthe p-type material that is ofthickness dx parallel to the surface andat a depth x (as
`shownby the B-B cross section) is
`
`.
`WW
`»
`(1)
`dC= qHpps a.
`where Wis the width ofthe bar, L is the length ofthe bar (we neglect the end contact
`areas for the time being), HL, is mobility of hole, and p(x) is the doping concentration.
`Thetotal conductance ofthe entire implanted region of the haris given by
`
`
`
`where x, is the junction depth, If the value of 4, , which is a function ofthe hole con-
`centration, and the distribution ofp(x) are known, the total conductance can be evalu-
`ated from Eq. 2. We can write
`
`W
`g—
`Gag
`
`(3)
`
`Maskset
`
`
`
`
`
`
` ¥
`
`
`Wafer
`
`Y
`Film
`
`formation
`
`Impurity
`doping
`
`Lithography
`Y
`Ftching
`
`Waler
`out
`
`
`
`Fig.
`
`Schematic flowdiagramofintegrated-circuit fabrication.
`
`where g =qJ Hy pOody is the conductance of a square resistor pattern, that is, G =
`eg when L= W.
`
`Chapter 14. Integrated Devices
`
`Chapter 14. Integrated Devices
`
`491
`
`
`
`Gale
`Drain
`|
`Source
`a
`
`Ne [a] yi
`“Toll.
`
`
`MOSFET
`
`La! to 10"
`’
`components a
`
`~50 lo 1N00chips
`
`100 to 300 nm
`(0.5 to 0.753 mmthick}
`(a)
`
`
`
`
`
`
`
`
`
`
`
`ONSEMI EXHIBIT 1042, Page 5
`
`

`

`ee
`
`.
`Chapter 14. Integrated Devices
`
`493
`
`EXAMPLE1
`
`>
`Find the value of a resistor 90 pun long and 16 Lum wide, such as the bar-shapedresistor in Fig, 3
`The sheet resistance is | kQ/4
`
`SOLUTION Theresistor contains 9 squares. The two end contacts correspondte 1.3 0. The value
`of the resistoris (9 + 1.3) | kQ/D = LOS kQ,
`
`14.1.2 The Integrated-Circuit Capacitor
`
`
`
`}
`'
`
`|
`
`
`
`|
`
`||
`
`{
`
`
`
`|
`
`(5)
`
`is the dielectric permittivity ofsilicon dioxide (the dielectric constant &,,/€, is
`where &,,
`3.9) anddis the thin-onide thickness. To increase the capacitance further, insulators with
`
`higher dielectric constants are being studied, such as Si;N,, and Ta,O,, with dielectric
`constants of 7 and 23, respectively. The MOS capacitance is essentially independent of
`the applied voltage, because the lowerplate of the capacitor is made ofheavily doped
`material, This also recluces the series resistance associated withit.
`Ap-n junctionis sometimes used as a capacitorin anintegratedcircuit. The top and
`cross sectional views of an n*-p junction capacitor are shown in Fig. 4b. The detailed
`
`Metal
`electrode
`
`
`
`{a)
`
`(b)
`
`Fig.4
`
`(a) Integrated MOScapacitor. (b) Integrated p-n junction capacitor.
`
`‘There arebasically tvotypes of capacitors used in integrated circuits: MOS capacitors
`and p—n junctions, The MOS (metal-oxide-semiconductor) capacitor can be fabricated
`byusing a heavily doped region (such as an emitter region) as one plate, the top metal
`electrode as the otherplate, andthe intervening oxide layer as the diclectric. The top
`ancl cross-sectional views of a MOS capacitorarc shownin Fig. :ta. To form a MOS capac-
`itor, a thick oxide layeris thermally grownomasilicon substrate, Next, a windowis litho-
`graphically defined andthen etchedin the oxide. Diffusion or ion implantation is used
`to form a p--region in the windowarea, whereas the surrounding thick oxide serves as a
`:
`:
`.
`:
`toe
`mask, A thin oxide layeris then thermally grownin the windowarea, followed by a met-
`allization step. The capacitance per unit area is given by
`‘
`0
`; apn
`——
`_€&
`
`'
`Pearl
`'
`WoW OWWow Ww owwow
`SiO,
`: +A
`
`=
`
`ie
`
`a-Si
`
`A.
`
`B— Bcross section
`
`_- aoe
`
`
`
`}
`|
`
`|
`|
`
`492,
`
`Chapter 14. Integrated Devices
`
`SiO,
`
`‘s rl
`1
`1
`
`7
`
`Cantact
`
`Pp
`
`
`
`A io
`
`
`
`Aerosssection
`
`a pP
`‘
`
`a-Si
`
`)
`ae
`
`Integrated-circnit resistors, All narrowlines in the large square area have the samewidth
`Fig.3
`W, andall contacts are the samesize,
`
`‘The resistance is therefore given by
`
` )
`
`where I/g usuallyis defined bythe syinbol Rg andis called the sheetresistance. Thesheet
`resistance has units of ohms but is conventionally specified in units of ohms per square
`(Q/3).
`Manyresistors in an integratedcircuit are fabricatedsinultancously by defining dif
`ferent geometricpatterns in the masksuchas those shownin Fig. 3. Since the same pro-
`cessing cycle is usedforall these resistors, it is conveniont to separate the resistance into
`two parts: the sheet resistance RB,
`, determined bythe implantation (ordiffusion) pro-
`cess; and the ratio LAV, determinedbythe pattern dimensions. Once the value ol R-is
`known, the resistanceis yiven by the ratio LAV, or the numberof squares (cach square
`has an area of Wx W)in the resistor pattern. The endcontact areas will introduce addi-
`tional resistance to the ICresistors. For the type shown in Fig. 3, each end contact cor
`responds to approximately0.65 square. For the meander-shaperesistor, theelectric- field
`lines at the bends arc not spaceduniformly across the width ofthe resistor but are crowded
`toward the inside corner. A square at the bend does not contribute exactly 1 square. but
`rather 0.65 square.
`
`ONSEMI EXHIBIT 1042, Page 6
`
`

`

`Chapter 14. Integrated Devices
`
`Chapter 14. Integrated Devices
`
`495
`
`
`
` 494
`
`fabrication process is considered in Section 14.2. because this structure forms part of g
`bipolartransistor. As a capacitor, the deviceis usually reversebiased, that is, the P-Fegion
`is reverse-biasedwith respect to the r'-region. Thecapacitanceis not a constant but varies
`as (V_ +V, 17, where Vis the appliedreverse voltage and V,, is the built-in potenti,
`Theseries resistance is considerably higher than that of a MOScapacitorbecausethe p-
`region has higherresistivity than docs the p*-region.
`EXAMPLE 2
`
`Whatis the stored charge and the aumberof electrons on an MOS capacitor with an area of 4
`in’, for (a) a dielectric of 10 umthick SiO, and(hb) a 5 nmthick Ta,O;, The appliedvoltageiy 5
`Vfor bathcases.
`
`SOLUTION
`
`i
`= BV
`fa) O =F, Ax =3.9«8.85« 10Fem x4 10em? x
`—2
`e
`1x 107% em
`or
`
`=6.9x10 MC
`
`), = 6.9 * 10-4 Crq = 4.3 x 10° electrons,
`‘
`t
`
`(b) Changing thedielectric constant from 3.9 to 25 andthe thickness from 10 nm to 5 um, we
`obtain Q, = §.85 x LOC, and Q, = 8.85 x 10 'S Cg = 5.53 x 10° electrons.
`
`14.1.3 The Integrated-Circuit Inductor
`
` he metal lines and the substrate, and RB.
`
`IC inductors have been widely used in TH-Vbased monolithic microwave integratedcir-
`cuits (MMIC. With the increased speedofsilicon devices and advancement in mullti-
`evel interconnection technology, JC inductors have started to receive more and more
`attcutions in silicon-basedradio frequency (rf) and high-frequencyapplications. Many
`inds of inductors can befabricatedusing IC processes. The mast popular methedis the
`hin-film spiral inductor, Figure 5a and b shows the top-viewandthe cross section ofa
`silicon-based, two-level-metal spiral inductor. To forma spiral inductor, a thick oxideis
`hermally grownordeposited ona silicon substrate. Thefirst nictalis then deposited and
`defined as one endof the inductor. Next, anotherdielectric is deposited onto the metal
`_A via holeis detinedlithographically and etchedin the oxide. Metal 2 is deposited and
`lie via holeis filled. The spiral patterned can be clefined and etched on the metal 2 as
`he second endof the inductor.
`To evaluate the inductor, an importantfigure ofmerit is the quality factor, Q. The
`Q is defined as O = La /R, where L, R, and @ are the inductance, resistance, and fre-
`quency, respectively. The higher the Q values, the lowerthe loss from resistance, hence
`he better the performanceofthe circuits. Figure 5¢ shows the equivalentcireuit model.
`R, is the inherentresistivity ofthe metal, C,, and C.y are the coupling capacitances between
`wap, and R,,,9 are the resistances ofthe silicon
`substrateassociated with the metal lines, respectively. The Q ineveaseslinearly with fre-
`quencyinitially and then dropsat higher frequencies because ofparasitic resistances and
`capacitances.
`There are someapproaches to improve the QO value. Thefirst is to use low-dielec-
`tric-constant materials (<3.9) to reduce the C,. The otheris to use a thick film metal
`orlow-resistivity metals (e.g., Cu, Au to replace Al) to reduce the R, Thethird app roach
`
`
`
`Metal 1
`
`
`
`
`
`
`
`
`L
`
`Ry
`
`
`Cn
`
`Roubt
`
`Metal 2
`Onicle
`
`= Cyp
`
`B Bats
`
`|
`
`(@) Schematic viewofa spiral inductoronasilicon substrate. (bi Perspective view along
`Fig. 5
`A-A’. (c) Anequivalentcircuit model for an integrated inductor,
`
`(c)
`
`uses an insulating substrate (e.g., silicon-on-sapphire, silicon-on-glass, or quartz) to
`reduce R,,,,.
`To obtain the exact value of a thin-film inductor, complicated sinnilation tool, such
`as computer aided design, must be employed for both circuit simulation and inductor
`optimization. The model for thin-film inductor must take into account the resistance of
`the metal, the capacitanceofthe oxide,line-to-line capacitance, theresistance of the sub-
`strate, the capacitance to the substrate, and the inductance and mutual inductance of
`the metal lines. Hence, it is more difficult to calculate the integrated inductance com-
`pared withthe integrated capacitors or resistors. However, a simple equationto estimate
`the square planarspiral inductoris given as*
`
`(6)
`
`
`
`ONSEMI EXHIBIT 1042, Page 7
`
`

`

`Chapter 14. Integrated Devices©497
`
`
`
`EXAMPLE3
`
`For an integrated inductor with an inductance of 10 nH, whatis the required radius if the mun.
`berofturns is 20?
`
`
`
`SOLUTION According to the Eq.6,
`10x 10°
`p= = 2.08 x 108 (m) = 20.8 um.
`1.2 10° x 20°
`
`14.2 BIPOLAR TECHNOLOGY
`
`For IC applications, especially for VLSI and ULSI, the size of bipolartransistors must
`be reduced to mectthe high-density requirement. Figure6 illustrates the reductionin
`the size ofthe bipolar transistor in recent years.* The main differences in a bipolartran-
`sistorin an IC cornpared witha discretetransistor are that all electrode contacts are located
`on the top surface of the IC wafer, and each transistor must beelectrically isolated to
`prevent interactions betweendevices. Prior to 1970, both thelateral and vertical isola-
`tions were provided by p—njunctions (Fig, 6z) and the lateral p-isolation region was always
`reverse biased with respect to the n-type collector. In 1971, thermal oxide was usedfor
`lateral isolation, resulting in a substantial reduction in device size (Fig, 6b), because the
`base andcollectorcontacts abuttheisolation region. In the mid-1970s, the emitter extended
`to the walls of the oxide,resulting in an additional reductionin area (Fig. 6c). At the pre-
`senttime,all the lateral and vertical dimensions have beenscaled down andemitterstripe
`widths have dimensions in the submicron region-(Fig. 6d).
`
` He 20Lly Emitter if |H \ I
`
`I\'\1
`
`
`
`
`|
`I
`
`
`
`
`
`
`
`\
`,
`|
`|
`1
`1 Base
`05
`A {
`Base ae
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`14.2.1 The Basic Fabrication Process
`where #y is the permeability in vacuum (4% x 10“ H/m),L is in henries, n is the num.
`| ber of turns, andris the radius of the spiral in meters.
`The majority of bipolartransistor used in [Cs are of the n-p-n type becausethe higher
`mobility of minority carriers (electrons) in the base region results in higher-speed per-
`formance than can be obtaincd with p-n-p types. Figure 7 shows a perspective view of
`an n-p-n bipolartransistor, in whichlateral isolation is provided by oxide walls and ver-
`tical isolationis provided by the n*~junction. Thelateral oxide isolation approach reduces
`not onlythe device size but also the parasitic capacitance because of the smaller dielec-
`tric constantof silicon dioxide (3.9, compared with 11.9 forsilicon). We consider the major
`process steps that are used to fabricate the device shown in Fig.7.
`For an n-p-n bipolartransistor, the starting material is a p-type lightly doped
`(~10" cm), (111)- or (100)-oriented, polishedsilicon wafer. Because the junctions are
`formed inside the semiconductor, the choice of crystal orientationis not as critical as for
`MOSdevices. Thefirst step is to form a buried layer. The main purposeofthis layeris
`to minimizethe series resistance of the collector. A thick oxide (0.5-1 jim)is thermally
`grown on the wafer, and a window is then openedin the oxide. A precisely controlled
`amountof low-energy arsenic ions (~30 keV, ~10% cm) is implanted into the window
`region to serve as a predeposit (Fig. 8a). Next, a high temperature (~1100°C) drive-in
`step forms the n*-buried layer, which hasa typical sheet resistance of 20 Q/O.
`The second step is to deposit an n-type epitaxial layer. The oxide is removed and the
`waferis placed in an epitaxial reactor for epitaxial growth. The thickness and the doping
`concentration ofthe epitaxial layer are determined bytheultimate use ofthe device. Analog
`circuits (with their higher voltages for amplification) require thicker layer (~10 |tm) and
`lower dopings (~5 x 10" cm), whereasdigital circuits (with their lowervoltages for switch-
`ing) require thinner layers (~3 jum) and higher dopings (~2 x 10' em~). Figure 8b shows
`a cross-sectional view of the device after the epitaxial process. Note that there is some
`outdiffusion from the buriedlayer into the epitaxial layer. To minimize the outdiffusion,
`a low-temperature epitaxial process should be employed, and low-diffusivity impurities
`should be used in the buried layer(e.g., As).
`Thethirdstep is to formthe lateral oxide isolation region. A thin-oxide pad (~50 nm)
`is thermally grownonthe epitaxial layer, followed bya silicon-nitride deposition (~100 nm).
`If nitride is deposited directly onto thesilicon without the thin-oxide pad,the nitride may
`cause damagesto thesilicon surface during the subsequenthigh-temperature steps. Next,
`the nitride-oxide layers and abouthalf of the cpitaxial layer are etched using a photoresist
`
` 496©Chapter 14. Integrated Devices
`
`1
`
`!
`
`{c)
`
`(d)
`
`
`
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`n* buried layer
`
`Fig.6 Reduction of the horizontal and vertical dimensionsof a bipolartransistor. (a) Junction
`isolation. (b) Oxideisolation. (c and d) Scaled oxideisolation?
`
`Fig.7 Perspective view of an oxide-isolated bipolar transistor.
`
`
`
`ONSEMI EXHIBIT 1042, Page 8
`
`

`

` 498
`
`Chapter 14. Integrated Devices
`
`Chapter 14. Integrated Devices
`
`499
`
`Arsenicimplant
`Hed td tee so,
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`Pig, 8 Cross-sectional views ofbipolartransistorfabrication. (a) Buried-layer implantation
`(b) Epitaxial layer. (¢) Photoresist mask. (ed) Chanstop implant.
`
`as mask (Fig. Sc and 8d). Boron ions are then inrplantedinto the exposedsilicon areas
`(Fig. 8d).
`The photoresist is removed and the wafer is placed in an oxidation furnace. Since
`the nitride layerhas a very low oxidationrate, thick oxides will be grown onlyin the areas
`not protectedbythenitride layer, ‘Theisolation oxide is usually grownto a thickness such
`that the top ofthe oxide becomes coplanar with the original silicon surface to minimize
`the surface topography. This oxide isolation process is called local oxidation of silicon
`(LOCOS). Figure 9a shows the cross section oftheisolation oxide after the removal of
`the nitride layer. Becaucofsegregation effects, most ofthe implanted boronions are pushed
`underneath the isolation oxide to form a p*-layer. This is called p* channel stop (or
`chanstop), because the high concentration ofp-type semiconductorwill prevent surface
`inversion audeliminate possible high-conductivity paths (or channels) among neighber-
`ing buriedlayers.
`© The fourth step is to formthe base region. A photoresist is used as a mask to pro
`
`tect the right halfofthe device; then, boron ions (~10'? em?) are implantedto form the
`baseregions, as shownin Fig. 9b. Anotherlithographic process removes all the thin-pad
`oxide except a small area near the centerofthe base region (Fig, 9c).
`Thefifth step is to formthe emitter region. As shownin Fig. 9d, the base gentle
`areais protected by a photoresist mask; then, a low-energy, high-arsenic—dose (~10!% em ‘
`implantation forms the n*-emitter and the n*-collector contact regions. The photoresis!
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`Fig. 9 Cross-section views afbipular transistor fabrication. (a) Oxideisolation, (1) Base
`implant, (¢) Removal of thin oxide, (¢) Emitter aud collectorimplant.
`
`is removed, anda final metallization step forms the contacts to the base, emitter. anil
`collector as shownin Fig. 7.
`In this basic bipolar process, there aresix filu fonnation operations. sia lithographic
`operations, four ion implantations, and four etching operations. Each operation must be
`IS.
`precisely controlled and monitored, Failure of any one of the operations generallywill
`renderthe wafer uselc
`The doping profiles of the completedtransistor along a coordinate perpendicularto
`the surtace andpassing throngh the emitter, base, and collector are shown in Fig. 10.
`‘Lhe emitterprofile is abrupt because of the concentration-dependent diffusivity ofarsenic.
`The base doping protile bencath the cmitter can be approximated bya Gaussian distri-
`bution fora limited-sourcediffusion. The collector doping is given bythe epitaxial dop-
`ing level (~2 10!cur) fora representative switching transistor; however, al larger depths.
`the collector doping concentration increases because ofoutdiffusion from the buried Tayer.
`
`14.2.2 Dielectric Isolation
`
`Inthe isolation scheme described previouslyfor the bipolar transistor, the device is iso-
`lated from other devices by the oxide layer aroundits peripheryandlis isolated fromits
`common substrate by a n*p junction (buriedlayer). In high-voltage applications, a different
`
`
`
`
`
`
`
`ONSEMI EXHIBIT 1042, Page 9
`
`

`

` 500
`
`Chapter 14. Integrated Devices
`
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`Chapter 14. Integrated Devices
`
`501
`
`Oxygenion implantation
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`Fig. 11
`high-voltage application.
`(4) Oxygen ion implantation. (b) Annealing at high temperature to
`form the isolation dielectric. (¢} Trench isolation formed by a dry-cteluing process. (d) Buse,
`cimitter, and collector formation.
`
`Theiost widely used self-aligned structure is the double-polysilicon structure with
`the advancedisolation provided by a trenchrefilled with polysilicon,® shown in Fig. 12.
`Figure 13 showsthe detail sequence ofthe stepslor the sellaligned double-polysilicon
`(n-p-n) bipolarstructure.® Thetransistoris built on an n-type epitaxial layer. A trench of
`3.0 jimin depthis etched byreactive ion etching throughthe n'-subcollectorregion into
`the posubstrate region. A thin layer of thermaloxide is then grown andservesas the screen
`oxide for the channel stop implant of boron at the bottomofthe trench. The trenchis
`
`then filled with mdoped poly: silicon aul capped by a thick pla Lea field oxide.
`Thefirst polysilicon layeris depositedand heavily doped with boron. The p*-polysil-
`icon (called poly 1) will be usedas asolid-phase diffusion source to form theextrinsic
`base region andthe base electrode. This layeris covered with a chemical-vapordeposition
`
`a poly
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`Fig.12 Cross-section ofa self-aligned, double-polvsilicon bipolar transistor with advanced
`trenchisolation?
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`-p-n transistorcoping profiles.
`
`approach,calleddielectric isolation,is used to form insulating tnbs to isolate a number
`ofpockets ofsingle-crystal semiconductors, In this approach the device is isolated from
`both its common substrate andits surrounding neighbors byadielectric layer
`Aprocess sequence for the dielectricisolation is shown in Fig. 11. Anoxicle layeris
`formed inside a <100>-oriented n-type silicon substrate using high-energy oxygen ion
`implantation (Fig. La). Next, the wafer undergoes a high-temperature annealing pro-
`cess sothat the implanted oxygen will react withsiliconto formtheoxide layer. Lhe dam-
`age resulting from implantationis also aunealecl out in this process (Fig, 1b), After this,
`sve can obtain an n-silicon layerthat is Tullyisolated on an oxide [namely,silicon-on-insu-
`lator, (SOT). This process is called SIMOX (separation by implanted oxygen). Sincethe
`topsilicon is sothin, the isolation region is casily formedby the LOC aS process illus-
`trated in Fig. 8¢ or by ctching a trench (Fig. Le) andrefilling it with oxide (Fig, Lid).
`The other processes are almost the same as those from Fig. Se through Fig. 9 to form
`the p-type base, n7-cmitter, andcollector.
`The main advantageofthis techniqueis its high breakdownvoltage between the emit:
`ter andthe collector, which can be in exce