United States Patent (19)
`Gibson
`
`54 QUADRATURE DEMODULATION DATA
`RECEIVER WITH PHASE ERROR
`CORRECTION
`
`75) Inventor: Rodney W. Gibson, Burgess Hill,
`England
`
`73) Assignee: U.S. Philips Corporation, New York,
`N.Y.
`
`(21) Appl. No.: 858,849
`
`22 Filed:
`
`Apr. 30, 1986
`
`63
`
`Related U.S. Application Data
`Continuation of Ser. No. 662,861, Oct. 19, 1984, aban
`doned.
`
`Foreign Application Priority Data
`30
`Oct. 21, 1983 GB United Kingdom ................. 832862
`
`51 Int. Cl." ............................................... HO3D 3/00
`52 U.S. Cl. ...................................... 329/50; 329/124;
`375/80; 455/214
`58 Field of Search ......................... 329/50, 122, 124;
`375/80, 81, 94, 120; 455/214, 260, 264, 265
`
`11
`45
`
`Patent Number:
`Date of Patent:
`
`4,682,117
`Jul. 21, 1987
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,971,996 7/1976 Motley et al. ....................... 328/55
`4,054,838 10/1977 Tretter ..........
`... 375/120 X
`4,359,692 11/1982 Ryan ..................................... 329/50
`4,521,892 6/1985 Vance et a
`329/124 X
`4,570,125 2/1986 Gibson .................................. 329/50
`FOREIGN PATENT DOCUMENTS
`2502680 7/1976 Fed. Rep. of Germany .
`1529284 10/1978 United Kingdom.
`Primary Examiner-Siegfried H. Grimm
`Attorney, Agent, or Firm-David R. Treacy
`57
`ABSTRACT
`A data receiver in which the phase of the carrier signal
`is controlled so that the threshold levels used for coher
`ent demodulation occur at the quarter points, that is 0,
`90, 180 and 270. An input signal is mixed with a local
`oscillator signal in a pair of mixers and the outputs
`therefrom are low pass filtered and subsequently de
`modulated. Any phase errors between the local oscilla
`tor signal and the input carrier signal are corrected by a
`correction loop. The carrier phase error is corrected
`after (or downstream of) the low pass filters, so that the
`phase can be corrected rapidly without the risk of insta
`bility.
`
`6 Claims, 3 Drawing Figures
`
`
`
`PHASE SHIFTING
`NETWORK
`
`LIMITNG
`AMPFER
`
`DATA
`DEMODULAOR
`
`
`
`DAIA &
`SERY
`: CIRCUIT
`
`
`
`DATA
`SIGNAL
`
`LOCAL
`OSCATOR 30
`
`LMTNG
`PHASE
`HFTING AMPLIFER
`ETWORK
`
`CONTROL
`SIGNAL
`CIRCUIT
`
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`U.S. Patent Jul 21, 1987
`
`Sheet 1 of 2
`
`4,682,117
`
`PHASE SHIFTNG
`NETWORK
`
`MITING
`AMPFER
`
`DAA
`DEMODULATOR
`
`
`
`
`
`
`
`LMTNG
`PHASE
`SHIFTING AMPLEFER
`NETWORK
`
`
`
`SIGNAL
`CIRCUIT
`
`DAA
`DEMODULATOR
`
`LIMITING
`AMPL FIER
`
`
`
`LOCAL
`
`OSCILLATOR
`
`-
`
`aw
`
`RCUIT
`SINE/COSINE
`GENERATOR
`
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`U.S. Patent Jul. 21, 1987
`
`Sheet 2 of 2
`
`4,682,117
`
`
`
`
`
`
`
`sinACOSB
`DAA
`DEMODULATOR
`
`SinAsin B
`
`-
`
`in A+B) > 80
`
`LOCAL
`OSCILLATOR
`
`
`
`AUXLARY
`OSCILLATOR
`
`
`
`42
`
`CONTROL
`SGNAL
`CIRCUIT
`
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`

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`1.
`
`QUADRATURE DEMODULATION DATA
`RECEIVER WITH PHASE ERROR CORRECTION
`
`This is a continuation of application Ser. No. 662,861,
`filed Oct. 19, 1984, now abandoned.
`BACKGROUND OF THE INVENTION
`The present invention relates to a data receiver.
`European Patent Specification Publication No. 0 098
`649, to which U.S. Pat. No. 4,570,125 corresponds,
`discloses a coherent data demodulator for digital signals
`wherein correction signals for clock and carrier oscilla
`tors are derived by comparing the times of the Zero
`crossings at the outputs of two orthogonal channels
`with the nominal times at which these crossings should
`occur. In the case of correcting the phase of the carrier
`signals, a correction signal is fed back to the local oscil
`lator so that its frequency is adjusted in the desired
`manner. Although the demodulator disclosed in EP
`Specification No. 0 098 649 and corresponding U.S. Pat.
`No. 4,570,125 operates satisfactorily, it does not have a
`limitation which is concerned with the rate at which the
`carrier phase can be adjusted. The carrier control loop
`includes quadrature mixers and low pass filters which
`25
`have an inherent filter delay. If the carrier phase, is
`adjusted quickly compared to the filter delay then the
`carrier control loop will go unstable. In some applica
`tions it is important for the receiver to have fast acquisi
`tion.
`
`15
`
`35
`
`30
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`4,682,117
`2
`tor having an input coupled to receive the control signal
`and first, second and third outputs on which are pro
`duced respectively the sine, cosine and minus sine of the
`phase correction angle. First and second multipliers are
`coupled to the output of the first mixer and third and
`fourth multipliers are coupled to the output of the sec
`ond mixer. The first generator output is coupled to the
`second multiplier, the second generator output is cou
`pled to the first and fourth multipliers and the third
`generator output is coupled to the third multiplier. Ad
`ditionally first and second summing means are pro
`vided. Inputs of the first summing means are coupled
`respectively to the outputs of the first and third multi
`pliers and inputs of the second summing means are
`coupled respectively to the inputs of the second and
`fourth multipliers. The outputs of the first and second
`summing means are coupled to the data demodulator.
`In a further embodiment of the present invention in
`which the data demodulator includes means for deter
`mining the phase error in the carrier signal and produc
`ing a control signal in response to the phase error deter
`mined, a controllable frequency generator having an
`output frequency corresponding to substantially one
`quarter of the received bit rate is provided and has an
`input for receiving the control signal. First and second
`quadrature multipliers are provided, the first multiplier
`being coupled to the output of the first mixer and the
`second multiplier being coupled to the output of the
`second mixer, an output of the controllable frequency
`generator being coupled to the first and second multipli
`ers. Summing means are provided, the summing means
`having first and second inputs coupled respectively to
`outputs of the first and second multipliers.
`By feeding a frequency of one quarter of the bit rate
`into the multipliers, the phase of the summed output is
`rotated by 90° every bit period. Consequently one has a
`built-in demultiplexer.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention will now be described, by way
`of example, with reference to the accompanying draw
`ings, wherein
`FIG. 1 is a block schematic circuit of an embodiment
`of a data receiver made in accordance with the present
`invention,
`e
`FIG. 2 is a block schematic circuit diagram of an
`other embodiment of a data receiver made in accor
`dance with the present invention, and
`FIG. 3 is a block schematic circuit diagram of a fur
`ther embodiment of a data receiver made in accordance
`with the present invention.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Referring to FIG. 1, a signal, which may be a fre
`quency modulated, differentially encoded input signal
`ft. Af, is applied to quadrature mixers 10, 12 to which
`a frequency fl, substantially equal to carrier frequency
`fo, is applied from a local oscillator 30. The outputs of
`the mixers 10, 12 are filtered in low pass filters 14, 16
`which will pass the modulation frequency Af. In an
`alternative arrangement, not shown, the low pass filters
`14, 16 may be omitted and the low pass filtering is done
`in the mixers 10, 12. Thus in the in-phase channel I the
`signal is -- Afor -Afand in the quadrature channel Q
`the signal is --Af-n/2 or - Af-77/2. By the way of
`example, f may be 900 MHz and the deviation fre
`
`SUMMARY OF THE INVENTION
`An object of the present invention is to obtain fast
`acquisition in a coherent data demodulator,
`According to the present invention there is provided
`a data receiver including quadrature mixers having
`outputs coupled by signal paths to a coherent data de
`modulator, wherein correction of carrier phase errors is
`effected after the outputs from the mixers have been
`pass filtered.
`40
`In the data receiver made in accordance with the
`present invention, the signal phase can be adjusted
`downstream of the mixers and filters, with negligible
`loop delay and hence without the risk of instability
`which would occur if the phase of the local oscillator
`was adjusted too quickly.
`In an embodiment of the present invention, phase
`shifting networks are provided in the signal paths to the
`data demodulator which includes means for determin
`ing the phase error in the carrier signal and producing a
`control signal in response to the phase error deter
`mined, which control signal is used to determine a phase
`correction to be applied by said phase shifting net
`works.
`If desired, each phase shifting network has a plurality
`of parallel outputs and means are provided for selecting
`one of the outputs in response to the control signal and
`thereby altering the phase of the signal being applied to
`the data demodulator. An advantage of using phase
`shifting networks having parallel outputs over networks
`60
`having serially arranged outputs is that the networks
`can be designed to produce a substantially constant time
`delay irrespective of the phase shift selected.
`In another embodiment of the present invention in
`which the data demodulator includes means for deter
`65
`mining the phase error in the carrier signal and produc
`ing a control signal in response to the phase error deter
`mined, a sine/cosine generator is provided, the genera
`
`45
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`50
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`55
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`O
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`4,682,117
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`quency Afwould be a quarter of the bit rate, e.g. for a
`oscillator 30 is not good enough, then a slow AFC can
`be applied via an input 46 from an output of the data
`bit rate of 16 Kb/s Af is 4 kHz.
`In order to control the phase of the signals in the I
`demodulator 36.
`and Q channels, the outputs of the filters 14, 16 are
`FIG. 2 illustrates another embodiment of the inven
`applied to phase shifting networks 18, 20 which have a
`tion in which the phase of the signal is corrected down
`plurality of parallel outputs 22, 24. The selection of a
`stream of the low pass filters 14, 16. In the interests of
`particular output 22, 24 is determined in accordance
`brevity only the features of difference between FIGS. 1
`with the phase error in the local oscillator 30 output. As
`and 2 will be described. The output from means 42
`indicated, output selecting devices 26, 28 are ganged
`providing the carrier control signal is coupled to a
`together so that the same phase shift is applied to both
`sine/cosine generator 50 which produces sine, cosine
`the I and Q channels. The signals on the devices 26, 28
`and minus sine of the desired phase angled for correct
`are hard limited in limiting amplifiers 32, 34 and thereaf
`ing the error in the carrier signal on outputs 52,54,56.
`ter the signals are applied to a data demodulator 36
`Multipliers 58,60 are coupled to the output of the low
`which includes means 44 for recovering the data and
`pass filter 14 on which the signal cos A is present, and
`the clock signals which are provided on outputs 38, 40
`multipliers 62, 64 are coupled to the output of the low
`and means 42 for providing a carrier control signal
`pass filter 16 on which the signal sin A is present. The
`which is applied to the output selecting devices 26, 28.
`outputs of the multipliers 58, 62 are coupled to a sum
`In the method described for fast acquisitions, it is
`ming circuit 66 whose output is coupled to the limiting
`necessary that the phase of the quadrature signals fed to
`amplifier 32. Similarly, the outputs of the multipliers 60,
`the limiting amplifiers 32, 34 be pulled quickly into
`64 are coupled to the summing circuit 68 whose output
`phase lock; otherwise data will be lost.
`is coupled to the limiting amplifier 34. The output 52 of
`In the circuit in accordance with the present inven
`the sine/cosine generator 50 is connected to the multi
`tion, the phase of the carrier and clock signals is deter
`pier 60, the output 54 is applied to the multipliers 58, 64
`mined from the information contained in the times of
`and the output 56 is applied to the multiplier 62. Thus
`the zero crossings at the hard limited outputs of the
`the inputs to the summing circuit 66 are:
`25
`amplifiers 32, 24. Demodulator arrangements for doing
`Cos A cos db and -sin A sin db which combine to
`this are described in EP Patent Specification No. 0 098
`form the output cos (A+d); the inputs to the summing
`649, and corresponding U.S. Pat. No. 4,570,125 details
`circuit 68 are:
`of which arrangements are incorporated by way of
`Cos A sin d and sin A cos d which combine to form
`reference. A description of these arrangements will, in
`the output sin (A--d).
`30
`the interests of brevity, not be given herein as they are
`These signals are then demodulated in the data de
`not relevant to the understanding of the present inven
`modulator 36.
`tion.
`In implementing the circuit shown in FIG. 2 the
`In the demodulator arrangements disclosed in EP
`sine/cosine generator 50 can be either an analogue func
`Patent Specification No. 0 098 649, and corresponding
`tion generator or, particularly if a digital output is pro
`35
`U.S. Pat. No. 4,570,125 the carrier phase correction
`duced by the means 42, a digital function generator
`signal is fed back to the local oscillator to correct its
`formed by a register, a ROM and digital-to-analogue
`output. In consequence, as low pass filters are part of
`converters.
`the correction loop, they impose a time limit on the rate
`FIG. 3 illustrates a further embodiment of the present
`at which the phase can be corrected, which time limit is
`40
`invention wherein the carrier phase is adjusted down
`undesirable if the data receiver is used to recover short
`stream of the low pass filters 14, 16. The outputs from
`burst data.
`these filters comprise cos A and sin A, respectively,
`In the embodiment shown in FIG. 1, by arranging
`where A=(a)c-col)t--d--0t and 0t is the modulation.
`phase shifting networks 18, 20 downstream of the low
`These outputs are applied to multipliers 70, 72 to which
`pass filters 14, 16, the rate of phase correction is not
`the output of an auxiliary oscillator 74 is connected; in
`45
`limited by filters 14, 16.
`the case of the multiplier 72, the auxilary oscillator
`In implementing the phase shifting networks 18, 20, it
`output is shifted in phase by TM2 in a phase shifter 76.
`is preferred that the outputs 22, 24be arranged in paral
`The frequency of the auxiliary oscillator 74 is nominally
`lel because the time delay of the networks 18, 20 can be
`fb/4 which corresponds to a quarter of the bit frequency
`substantially constant irrespective of the applied phase
`fb. However, the frequency and phase of this signal is
`shift. The phase shifting networks may be of any suit
`adjusted in response to a carrier control signal applied
`able type, for example transformers and networks of the
`to the auxiliary oscillator on an input 78. In FIG. 3 the
`Dome type. Although each network has been illustrated
`auxiliary oscillator output is referred to as sin B and the
`as comprising 6 outputs 22, 24, in reality there might be
`quadrature phase shifted output is referred to as cos B
`say 8 to 16 equally spaced outputs to provide 45 or 22
`55
`where
`of phase shift within an overall range of 360. The out
`put selecting devices 26, 28 comprise switches which
`are operated in response to the carrier control signal
`from the means 42 in the data demodulator 36, to select
`the appropriate phase output.
`In a non-illustrated alternative embodiment, the
`phase shifting networks 18, 20 may be of a series type;
`but a disadvantage of such an arrangement is that the
`time delay will vary in accordance with the amount of
`delay required.
`65
`It is not essential for automatic frequency control
`(AFC) to be applied to the local oscillator 30. However
`if it is found that the frequency stability of the local
`
`The outputs cos Asin B and sin Acos B from the multi
`pliers 70, 72 are combined in a summing amplifier80 to
`produce an output sin (A+B) which equals sin
`cobt/4--6t).
`Thus by feeding a frequency of one quarter the bit
`rate (fb/4) into the multipliers, the phase of the summed
`output from the amplifier80 is rotated by 90° every bit
`period in addition to the modulation 6t. In the data
`demodulator the data is recovered by alternately strob
`ing the two quadrature signals. This is equivalent to
`
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`10
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`4,682,117
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`5
`observing alternately the signal and (the signal -- at/2).
`pass filter means to the output of the first of the
`quadrature mixers, the second multiplier being
`The introduction of a 90° phase shift every bit period
`effectively carries out this demultiplexing operation and
`coupled through the respective other low pass
`replaces the switches normally used for the purpose (as
`filter means to the output of the second of the quad
`for example in EP Patent Specification No. 0 098 649
`rature mixers, and the output of the controllable
`and corresponding U.S. Pat. No. 4,570,125).
`frequency generator being coupled to the first and
`second multipliers; and
`I claim:
`1. A data receiver comprising quadrature mixers hav
`the summing means has first and second inputs cou
`ing outputs coupled by signal paths to a coherent data
`pled respectively to outputs of the first and second
`demodulator, means for applying an incoming signal to
`multipliers and an output coupled to the data de
`each of said mixers, low pass filter means in each of said
`modulator.
`signal paths, and means for correcting phase errors after
`3. A data receiver as claimed in claim 2, comprising
`the outputs from the mixers have been low pass filtered
`local oscillator means for generating quadrature outputs
`in said filter means, the data demodulator including
`independent of the signals propagating in said signal
`means for determining the phase error in the incoming
`paths and individually supplying such quadrature out
`signal and producing a control signal in response to the
`puts to said quadrature mixers for mixing therein with
`phase error determined;
`the incoming signals, and
`wherein said means for correcting phase errors com
`means coupled to the data demodulator for applying
`prises a controllable frequency generator having an
`a slow automatic frequency control signal to the
`output frequency corresponding to substantially
`20
`local oscillator.
`one quarter of the received bit rate of the incoming
`4. A data receiver as claimed in claim 2, comprising
`signal, said generator having an output and an in
`local oscillator means for generating quadrature outputs
`put; and first and second multipliers and summing
`independent of the signals propagating in said signal
`means;
`paths and individually supplying such quadrature out
`said control signal is applied to the input of the con
`25
`puts to said quadrature mixers for mixing therein with
`trollable frequency generator, the first multiplier
`the incoming signals, and
`being coupled to the output of the first of the quad
`means in the data demodulator for determining the
`rature mixers through the respective low pass filter
`incoming signal phase error by comparing the time
`means, the second multiplier being coupled to the
`of the zero crossings in the inputs thereto with the
`output of the second of the quadrature mixers
`nominal times at which these crossings should oc
`through the respective other low pass filter means,
`C.
`the output of the controllable frequency generator
`5. A data receiver comprising quadrature mixers hav
`being coupled to the first and second multipliers;
`ing outputs coupled by signal paths to a coherent data
`and
`demodulator, means for applying an incoming signal to
`the summing means has first and second inputs cou
`35
`each of said mixers, low pass filter means in each of said
`pled respectively to outputs of the first and second
`signal paths, and means for correcting phase errors after
`multipliers and an output coupled to the data de
`the outputs from the mixers have been low pass filtered
`modulator.
`in said filter means, the data demodulator including
`2. A data receiver comprising quadrature mixers hav
`means for determining the phase error in the incoming
`ing outputs coupled by signal paths to a coherent data
`40
`signal and producing a control signal in response to the
`demodulator, means for applying an incoming signal to
`phase error determined;
`each of said mixers, low pass filter means in each of said
`wherein said correcting means includes phase shifting
`signal paths, and means for correcting phase errors after
`networks in said signal paths to the data demodula
`the outputs from the mixers have been low pass filtered
`tor, and said receiver further comprises means for
`in said filter means, the data demodulator including
`45
`using said control signal to determine a phase cor
`means for determining the phase error in the incoming
`rection to be applied to said phase shifting net
`signal and producing a control signal in response to the
`works.
`phase error determined;
`6. A data receiver as claimed in claim 5, wherein each
`wherein said correcting means includes a controllable
`phase shifting network has a plurality of parallel out
`frequency generator having an output frequency
`puts, the phase being shifted by respectively different
`corresponding to substantially one quarter of the
`values at respective outputs; and wherein said using
`received bit rate of the data in the incoming signal,
`means includes means for selecting one of the outputs of
`said generator having an output and an input; first
`the respective phase shifting network in response to said
`and second quadrature multipliers and summing
`control signal to alter the phase of the signal being
`means; said control signal is applied to the input of 55
`applied to the data demodulator.
`the controllable frequency generator, the first mul
`tiplier being coupled through the respective low
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