U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`MERCEDES-BENZ USA, LLC,
`Petitioner
`v.
`
`DAEDALUS PRIME LLC
`Patent Owner
`
`Case (to be assigned)
`U.S. Patent No. 10,049,080
`
` DECLARATION OF ROBERT HORST IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF
`US. PATENT NO. 10,049,080
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`Petitioner Mercedes Ex-1034
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`TABLE OF CONTENTS
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`Page
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`I.
`
`II.
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`INTRODUCTION ........................................................................................... 1
`A. Qualifications ........................................................................................ 2
`B. Materials Considered ............................................................................. 5
`LEGAL STANDARDS ................................................................................... 8
`A. Anticipation ........................................................................................... 8
`B.
`Obviousness ........................................................................................... 9
`C.
`Level of Ordinary Skill in the Art ....................................................... 12
`D.
`Claim Construction.............................................................................. 13
`SUMMARY OF GROUNDS ........................................................................ 14
`III.
`IV. THE ’080 PATENT ....................................................................................... 16
`A. Overview of the ’080 Patent ................................................................ 16
`B.
`Prosecution History of the ‘’080 Patent .............................................. 19
`TECHNOLOGY BACKGROUND ............................................................... 22
`A.
`Relationship between power, voltage, and frequency ......................... 22
`B. Multi-core processing approaches ....................................................... 24
`C.
`Processor Microarchitectures .............................................................. 27
`D. Heterogeneous multi-core processors ................................................. 29
`VI. THE PRIOR ART IN THE APPLIED INVALIDITY GROUNDS ............. 32
`A. Mathieson (Ex-1005) ........................................................................... 32
`B.
`Carmack (Ex-1006) ............................................................................. 34
`C.
`Sutardja – Sutardja ’748 (Ex-1007) and Sutardja ’785 (Ex-1008) ..... 37
`D.
`Rychlik (Ex-1009) ............................................................................... 39
`VII. CLAIM CONSTRUCTION .......................................................................... 40
`VIII. DETAILED EXPLANATION OF THE UNPATENABILITY GROUNDS
` ....................................................................................................................... 41
`A. Ground 1: Claims 1-4, 7-12, 15-20, 23-24 are rendered obvious by
`Sutardja (Ex-1007, incorporating Ex-1008) ........................................ 41
`1.
`Independent Claim 1 ................................................................. 41
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`V.
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`d.
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`e.
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`a.
`b.
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`c.
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`Element 1[pre]: A multi-core processor comprising: ..... 41
`Element 1[a][i]: a first plurality of cores and a second
`plurality of cores that support a same instruction set, .... 42
`Element 1[a][ii]: wherein the second plurality of cores
`consume less power, for a same applied operating
`frequency and supply voltage, than the first plurality of
`cores; and ........................................................................ 53
`Element 1[b][i]: power management hardware to, from a
`state where the first plurality of cores and the second
`plurality of cores are enabled, disable all of the first
`plurality of cores for a drop in demand below a threshold
`without disabling any of the second plurality of cores, .. 55
`Element 1[b][ii]: wherein an operating system to execute
`on the multi-core processor is to monitor a demand for
`the multi-core processor and control the power
`management hardware based on the demand. ................ 66
`Dependent Claim 2: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates that
`have narrower logic gate driver transistors than corresponding
`logic gates of the first plurality of cores. .................................. 69
`Dependent Claim 3: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates that
`consume less power than corresponding logic gates of the first
`plurality of cores. ...................................................................... 72
`Dependent Claim 4: The multi-core processor of claim 1,
`wherein the second plurality of cores each have a maximum
`operating frequency that is less than a maximum operating
`frequency of the first plurality of cores. ................................... 73
`Dependent Claim 7: The multi-core processor of claim 1,
`wherein the first plurality of cores are at a maximum operating
`frequency in the state. ............................................................... 74
`Dependent Claim 8: The multi-core processor of claim 1,
`wherein ...................................................................................... 75
`a.
`Element 8[a]: the power management hardware is to
`enable all of the first plurality of cores for an increase in
`demand above the threshold without disabling any of the
`second plurality of cores, ................................................ 75
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`b.
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`c.
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`d.
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`Element 8[b]: wherein an operating system is to monitor
`a demand for the multi-core processor and control the
`power management hardware based on the demand. ..... 80
`Independent Claims 9 and 17:................................................... 80
`a.
`Element 9[preamble]: A method comprising: ................ 80
`b.
`Element 17[preamble]: A non-transitory machine
`readable medium containing program code that when
`processed by a machine causes a method to be
`performed, the method comprising: ............................... 80
`Elements 9[a][i] and 17[a][i]: operating a multi-core
`processor such that a first plurality of cores and a second
`plurality of cores execute a same instruction set, ........... 81
`Elements 9[a][ii] and 17[a][ii]: wherein the second
`plurality of cores consume less power, for a same applied
`operating frequency and supply voltage, than the first
`plurality of cores; and ..................................................... 81
`Elements 9[b][i] and 17[b][i]: disabling with power
`management hardware, from a state where the first
`plurality of cores and the second plurality of cores are
`enabled, all of the first plurality of cores for a drop in
`demand below a threshold without disabling any of the
`second plurality of cores, ................................................ 81
`Element 9[b][ii] and 17[b][ii]: wherein an operating
`system executing on the multi-core processor monitors a
`demand for the multi-core processor and controls the
`power management hardware based on the demand. ..... 81
`Dependent Claims 10 and 18: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating of the second plurality of cores comprises
`driving logic gates that have narrower logic gate driver
`transistors than corresponding logic gates of the first plurality
`of cores. ..................................................................................... 82
`Dependent Claims 11 and 19: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating of the second plurality of cores comprises
`driving logic gates that consume less power than corresponding
`logic gates of the first plurality of cores. .................................. 82
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`10. Dependent Claims 12 and 20: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating comprises operating the second plurality
`of cores at a maximum operating frequency that is less than a
`maximum operating frequency of the first plurality of cores. .. 82
`11. Dependent Claims 15 and 23: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating comprises operating the first plurality of
`cores at a maximum operating frequency in the state. .............. 82
`12. Dependent Claims 16 and 24: The [method of claim
`9/nontransitory machine readable medium of claim 17], further
`comprising ................................................................................. 83
`a.
`Elements 16[a] and 24[a]: enabling, with the power
`management hardware, all of the first plurality of cores
`for an increase in demand above the threshold without
`disabling any of the second plurality of cores, ............... 83
`Elements 16[b] and 24[b]: wherein an operating system
`is to monitor a demand for the multi-core processor and
`control the power management hardware based on the
`demand. ........................................................................... 83
`Ground 2: Claims 5-6, 13-14, and 21-22 are rendered obvious by
`Sutardja in view of Rychlik ................................................................. 83
`1.
`Dependent Claims 5, 13, and 21: .............................................. 83
`a.
`Elements 5[a], 13[a], 21[a]: The [multi-core processor of
`claim 1/method of claim 9/non-transitory machine
`readable medium of claim 17], [wherein the power
`management hardware is to disable/further comprising
`disabling, with the power management hardware,] an
`additional core of the second plurality of cores for each
`continued drop in demand below a next lower threshold
`until one core of the second plurality of cores remains
`enabled, and .................................................................... 83
`Elements 5[b], 13[b], 21[b]: [lower/lowering] an
`operating frequency or a supply voltage of the one core
`of the second plurality of cores as demand drops below a
`next lower threshold. ...................................................... 90
`Dependent Claims 6, 14, 22: [The multi-core processor of claim
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`b.
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`b.
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`B.
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`5/method of claim 13/The non-transitory machine readable
`medium of claim 21], [wherein the power management
`hardware is to raise/further comprising raising, with the power
`management hardware,] a supply voltage or an operating
`frequency of said one core in response to higher demand. ....... 93
`C. Ground 3: Claims 7, 15, and 23 Are Rendered Obvious By
`Sutardja/Carmack ................................................................................ 93
`1.
`Dependent Claims 7, 15, 23: The [multi-core processor of claim
`1/method of claim 9/non-transitory machine readable medium
`of claim 17], wherein [the operating comprises operating] the
`first plurality of cores [are] at a maximum operating frequency
`in the state. ................................................................................ 94
`D. Ground 4: Claims 1-4, 7-12, 15-20, and 23-24 Are Rendered Obvious
`By Mathieson/Sutardja ........................................................................ 95
`1.
`A POSITA would have been motivated to combine Mathieson
`with Sutardja ............................................................................. 96
`Independent Claim 1 ................................................................. 98
`a.
`Element 1[preamble]: A multi-core processor
`comprising: ..................................................................... 98
`Element 1[a][i]: a first plurality of cores and a second
`plurality of cores that support a same instruction set, .... 99
`Element 1[a][ii]: wherein the second plurality of cores
`consume less power, for a same applied operating
`frequency and supply voltage, than the first plurality of
`cores; and ...................................................................... 104
`Element 1[b][i]: power management hardware to, from a
`state where the first plurality of cores and the second
`plurality of cores are enabled, disable all of the first
`plurality of cores for a drop in demand below a threshold
`without disabling any of the second plurality of cores, 107
`Element 1[b][ii]: wherein an operating system to execute
`on the multi-core processor is to monitor a demand for
`the multi-core processor and control the power
`management hardware based on the demand. .............. 115
`Dependent Claim 2: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates that
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`4.
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`5.
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`6.
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`7.
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`8.
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`b.
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`c.
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`d.
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`have narrower logic gate driver transistors than corresponding
`logic gates of the first plurality of cores. ................................ 118
`Dependent Claim 3: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates that
`consume less power than corresponding logic gates of the first
`plurality of cores. .................................................................... 122
`Dependent Claim 4: The multi-core processor of claim 1,
`wherein the second plurality of cores each have a maximum
`operating frequency that is less than a maximum operating
`frequency of the first plurality of cores. ................................. 123
`Dependent Claim 7: The multi-core processor of claim 1,
`wherein the first plurality of cores are at a maximum operating
`frequency in the state. ............................................................. 125
`Dependent Claim 8: The multi-core processor of claim 1,
`wherein .................................................................................... 127
`a.
`Element 8[a]: the power management hardware is to
`enable all of the first plurality of cores for an increase in
`demand above the threshold without disabling any of the
`second plurality of cores, .............................................. 127
`Element 8[b]: wherein an operating system is to monitor
`a demand for the multi-core processor and control the
`power management hardware based on the demand. ... 133
`Independent Claims 9 and 17:................................................. 133
`a.
`Element 9[preamble]: A method comprising: .............. 133
`b.
`Element 17[preamble]: A non-transitory machine
`readable medium containing program code that when
`processed by a machine causes a method to be
`performed, the method comprising: ............................. 133
`Elements 9[a][i] and 17[a][i]: operating a multi-core
`processor such that a first plurality of cores and a second
`plurality of cores execute a same instruction set, ......... 134
`Elements 9[a][ii] and 17[a][ii]: wherein the second
`plurality of cores consume less power, for a same applied
`operating frequency and supply voltage, than the first
`plurality of cores; and ................................................... 134
`Elements 9[b][i] and 17[b][i]: disabling with power
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`f.
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`9.
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`management hardware, from a state where the first
`plurality of cores and the second plurality of cores are
`enabled, all of the first plurality of cores for a drop in
`demand below a threshold without disabling any of the
`second plurality of cores, .............................................. 134
`Element 9[b][ii] and 17[b][ii]: wherein an operating
`system executing on the multi-core processor monitors a
`demand for the multi-core processor and controls the
`power management hardware based on the demand. ... 134
`Dependent Claims 10 and 18: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating of the second plurality of cores comprises
`driving logic gates that have narrower logic gate driver
`transistors than corresponding logic gates of the first plurality
`of cores. ................................................................................... 135
`10. Dependent Claims 11 and 19: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating of the second plurality of cores comprises
`driving logic gates that consume less power than corresponding
`logic gates of the first plurality of cores. ................................ 135
`11. Dependent Claims 12 and 20: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating comprises operating the second plurality
`of cores at a maximum operating frequency that is less than a
`maximum operating frequency of the first plurality of cores. 135
`12. Dependent Claims 15 and 23: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating comprises operating the first plurality of
`cores at a maximum operating frequency in the state. ............ 135
`13. Dependent Claims 16 and 24: The [method of claim
`9/nontransitory machine readable medium of claim 17], further
`comprising ............................................................................... 136
`a.
`Elements 16[a] and 24[a]: enabling, with the power
`management hardware, all of the first plurality of cores
`for an increase in demand above the threshold without
`disabling any of the second plurality of cores, ............. 136
`Elements 16[b] and 24[b]: wherein an operating system
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`E.
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`is to monitor a demand for the multi-core processor and
`control the power management hardware based on the
`demand. ......................................................................... 136
`Ground 5: Claims 5-6, 13-14, and 21-22 Are Rendered Obvious By
`Mathieson/Sutardja/Rychlik .............................................................. 136
`1.
`Dependent Claims 5, 13, and 21: ............................................ 136
`a.
`Elements 5[a], 13[a], 21[a] ........................................... 136
`b.
`Elements 5[b], 13[b], 21[b] .......................................... 137
`Dependent Claims 6, 14, 22 .................................................... 138
`2.
`IX. CONCLUSION ............................................................................................ 138
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`
`I.
`
`INTRODUCTION
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`1.
`
`I have been retained by Mercedes-Benz USA, LLC (“Mercedes” or
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`“Petitioner”), as an independent expert in this proceeding before the Patent Trial
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`and Appeal Board (“PTAB” or “Board”). I understand that Mercedes is requesting
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`that the Board institute an inter partes review (“IPR”) proceeding of U.S. Patent
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`No. 10,049,080 (“the ’080 Patent”) (Ex-1001), currently assigned to Daedalus
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`Prime LLC (“Patent Owner” or “PO”).
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`2.
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`I am not and have never been an employee of Mercedes. I am being
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`compensated at my usual and customary rate of $650 per hour. No part of my
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`compensation depends on the outcome of this proceeding, and I have no other
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`interest in this proceeding.
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`3.
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`Specifically, I have been retained as a technical expert by Mercedes to
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`study and provide my opinions on the technology claimed in, and the patentability
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`or unpatentability of, claims 1-24 of the ’080 patent (“the challenged claims”).
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`This declaration is directed to the challenged claims of the ’080 patent, and sets
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`forth the opinions I have formed, the conclusions I have reached, and the bases for
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`each. For purposes of this declaration, I was not asked to provide any opinions that
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`are not expressed herein. I was further asked to review and opine on the documents
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`filed and positions taken in IPR2023-00567 filed by Samsung Electronics Co.,
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`Ltd., Samsung Electronics America, Inc., and Qualcomm, Inc., including the
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`Declaration of Trevor Mudge, Ph.D. (“Dr. Mudge”), EX1002, and the exhibits
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`cited therein, and form an opinion of whether I agreed with the facts, analysis, and
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`conclusions in that declaration. In general, as set forth below, I agree with the
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`analysis and conclusion of Dr. Mudge. For sake of efficiency, I have incorporated
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`parts of Dr. Mudge’s analysis with which I agree into this declaration.
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`4.
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`I am familiar with the technology described in the ’080 patent as of its
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`earliest possible priority date of December 22, 2001. I have been asked to provide
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`my technical review, analysis, insights, and opinions regarding the ’080 patent. I
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`have used this experience and insight along with the above-noted references as the
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`basis for the grounds of unpatentability set forth in the Petition for inter partes
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`review of the ’080 patent.
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`5.
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`For my efforts in connection with the preparation of this declaration, I
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`have been compensated at my standard hourly consulting rate. My compensation is
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`in no way contingent on the results of these or any other proceedings relating to the
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`above- captioned patent. I have no expectation or promise of additional business
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`with the petitioner in exchange for the positions explained herein.
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`A. Qualifications
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`6.
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`I am currently Principal at Horst Tech LLC, where I perform research,
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`design, and manufacturing of electronic systems and devices. I also serve as an
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`Adjunct Research Professor at the University of Illinois at Urbana-Champaign in
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`the Department of Electrical and Computer Engineering. All of my opinions stated
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`in this declaration are based on my own personal knowledge and professional
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`judgment. In forming my opinions, I have relied on my 47 years of experience as
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`an engineer, technical director, researcher, chief technology officer, consultant, and
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`research professor in the processor, CPU, cache, memory and input/output (I/O)
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`systems, and computer hardware field.
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`7.
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`I am over 18 years of age and, if I am called up on to do so, I would
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`be competent to testify as to the matters set forth herein. I understand that a copy of
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`my current curriculum vitae, which details my education and professional and
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`academic experience, is being submitted by Petitioner as Exhibit 1035. The
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`following provides an overview of some of my experience that is relevant to the
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`matters set forth in this declaration.
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`8.
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` I earned my M.S. (1978) in electrical engineering and Ph.D. (1991) in
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`computer science from the University of Illinois at Urbana-Champaign after
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`earning my B.S. (1975) in electrical engineering from Bradley University. During
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`my master’s program, I designed, constructed, and debugged a shared memory
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`parallel microprocessor system. During my doctoral program, I designed and
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`simulated a massively parallel, multi-threaded task flow computer.
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`9.
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`After receiving my bachelor’s degree and while pursuing my master’s
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`degree, I worked for Hewlett-Packard Company. While at Hewlett-Packard, I
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`designed the micro-sequencer and cache of the HP3000 Series 64 Processor. From
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`1980 to 1999, I worked at Tandem Computers, which was acquired by Compaq
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`Computers in 1997. While at Tandem, I was a designer and architect of several
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`generations of fault-tolerant computer systems and was the principal architect of
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`the NonStop Cyclone superscalar processor.
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`10.
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` I also have various publications, including publications related to
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`CPU architecture and storage. I have also received the Distinguished Alumni
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`Award from the University of Illinois Department of Electrical and Computer
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`Engineering for “Pioneering Contributions to Fault-tolerant Computer
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`Architecture.” I have served on various IEEE committees and was elected as an
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`IEEE fellow “for contributions to the architecture and design of fault tolerant
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`systems and networks.
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`11.
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`I have my own patents directed to processor and memory system
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`design and aspects of circuit chip design, including U.S. Pat. No. 5,146,589, U.S.
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`Pat. No. 5,287,472, U.S. Pat. No. 5,329,629, U.S. Pat. No. 5,034,964, and U.S. Pat.
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`No. 9,893,604. I have testified as an expert witness on over 85 patent matters
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`related to processor, storage, and network systems. I have also served as an expert
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`witness in patent and intellectual property litigation as well as on several inter
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`partes review matters, including IPR2018-01249, IPR2018-01315, IPR2018-
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`01316, IPR2018-00371, IPR2018-00372, IPR2018-00374, IPR2018-00375,
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`IPR2018-00327, IPR2018-00328, IPR2018-00329, IPR2017-01707, IPR2017-
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`01711, IPR2017-01714, IPR2017-01718, IPR2017-01728, IPR2017-01729,
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`IPR2017-01732, IPR2017-01733, IPR2017-01391, IPR2017-01392, IPR2017-
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`01393, IPR2017-01395, IPR2017-01406, IPR2017-01559, IPR2017-01705,
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`IPR2017-01713, IPR2016-0897, IPR2016-0902, IPR2016-0903, IPR2014-01469,
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`IPR2015-00159, IPR2015-00161, IPR2015-00163, IPR2015-00172, IPR2014-
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`00949, IPR2014-00901, and IPR2013-00440.
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`12. Based on my experience and education, I am familiar with the design,
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`operation, and functionality of processor systems described in the ’080 Patent. I
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`believe that I am qualified to opine as to the knowledge and level of skill of one of
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`ordinary skill in the art at the time of the alleged invention of the ’080 Patent, as
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`well as the state of the art at that time.
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`13. Further details regarding my employment and professional experience
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`are attached as EX1035.
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`B. Materials Considered
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`14.
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`In forming my opinions, I have reviewed the following documents:1
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`1 Four-digit pin citations that begin with 0 are to the branded numbers added by
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`Mercedes in the bottom right corner of the exhibits. All other pin citations are to
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`original page, column, paragraph, or line numbers.
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`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`
`Ex-1001
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`U.S. Patent No. 10,049,080 to George et al. (“the ’080 Patent”)
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`Ex-1002
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`Declaration of Dr. Trevor Mudge submitted in IPR2023-00567
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`Ex-1003
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`INTENTIONALLY BLANK
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`Ex-1004
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`Ex-1005
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`Prosecution History of the ’080 Patent (Application No.
`15/431,527)
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`U.S. Patent Pub. No. 2011/0213950 to Mathieson et al.
`(“Mathieson”)
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`Ex-1006
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`U.S. Patent Pub. No. 2009/0309243 to Carmack et al. (“Carmack”)
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`Ex-1007
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`U.S. Patent Pub. No. 2008/0288748 to Sutardja et al. (“Sutardja
`’748”)
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`Ex-1008
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`U.S. Patent Pub. No. 2007/0083785 to Sutardja (“Sutardja ’785”)
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`Ex-1009
`
`U.S. Patent Pub. No. 2011/0145615 to Rychlik et al. (“Rychlik”)
`
`Ex-1010
`
`Prosecution History of U.S. Patent No. 9,569,278 (“the ’278
`Patent”)
`
`Ex-1011
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`INTENTIONALLY LEFT BLANK
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`Ex-1012
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`INTENTIONALLY LEFT BLANK
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`Ex-1013
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`INTENTIONALLY LEFT BLANK
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`Ex-1014
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`INTENTIONALLY LEFT BLANK
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`Ex-1015
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`INTENTIONALLY LEFT BLANK
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`Ex-1016
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`INTENTIONALLY LEFT BLANK
`
`Ex-1017
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`INTENTIONALLY LEFT BLANK
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`Ex-1018
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`INTENTIONALLY LEFT BLANK
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`Ex-1019
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`INTENTIONALLY LEFT BLANK
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`Ex-1020
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`Claim Mapping Table
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`
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`- 6 -
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`Petitioner Mercedes Ex-1034
`
`

`

`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`
`Ex-1021
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`INTENTIONALLY LEFT BLANK
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`Ex-1022
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`U.S. Patent Pub. No. 2006/0095807 to Grochowski
`(“Grochowski”)
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`Ex-1023
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`U.S. Patent Pub. No. 2012/0317568 to Aasheim (“Aasheim”)
`
`Ex-1024
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`Ex-1025
`
`Jeffrey C. Mogul et al., Operating Systems and Asymmetric Single-
`ISA CMPs: The Potential for Saving Energy, Hewlett-Packard
`Development Company, L.P. (2007)
`
`Juan Carlos Saez et al., Operating System Support for Mitigating
`Software Scalability Bottlenecks on Asymmetric Multicore
`Processors, ACM 978-1-4503-004-5/10/05 (2010)
`
`Ex-1026
`
`U.S. Patent No. 7,093,147 to Farkas et al. (“Farkas”)
`
`Ex-1027
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`Ex-1028
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`Ex-1029
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`Ex-1030
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`Ex-1031
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`Ex-1032
`
`Charles Lefurgy et al., Energy Management for Commercial
`Servers, Computer 39 (Dec. 2003).
`
`Yushi Shen et al., Enabling the New Era of Cloud Computing:
`Data Security, Transfer, and Management (Information Science
`Reference 2014).
`
`Stefanos Kaxiras and Margaret Martonosi, Computer Architecture
`Techniques for Power-Efficiency, in Synthesis Lectures on
`Computer Architecture #4 (Morgan & Claypool 2008).
`
`Vasanth Venkatachalam and Michael Franz, Power Reduction
`Techniques For Microprocessor Systems, 37 ACM Computing
`Surveys 195 (2005).
`
`Euiseong Seo et al., Energy Efficient Scheduling of Real-Time
`Tasks on Multicore Processors, 19 IEEE Transactions on Parallel
`and Distributed Systems 1540 (Nov. 2008).
`
`Rakesh Kumar et al., Single-ISA Heterogeneous Multi-Core
`Architectures: The Potential for Processor Power Reduction,
`Proceedings of the 36th International Symposium on
`Microarchitecture (MICRO-36 2003), IEEE Computer Society
`(2003).
`
`
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`- 7 -
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`Petitioner Mercedes Ex-1034
`
`

`

`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`
`Ex-1033
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`U.S. Patent No. 8,615,647 to Hum et al. (“Hum”)
`
`Ex-1034
`
`Declaration of Dr. Robert Horst
`
`Ex-1035
`
`Curriculum Vitae of Dr. Robert Horst
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`
`
`II. LEGAL STANDARDS
`
`15.
`
`In forming my opinions and considering the subject matter of the ’080
`
`Patent and its claims in light of the prior art, I am relying on certain legal principles
`
`that counsel in this case explained to me. My understanding of these concepts is
`
`summarized below.
`
`16.
`
`I understand that earlier publications and patents may act to render a
`
`patent unpatentable for one of two reasons: (1) anticipation, and (2) obviousness.
`
`A. Anticipation
`
`17.
`
`It is my understanding that the claims of a patent are anticipated by a
`
`prior art reference if each and every element of the claim is found either explicitly
`
`or inherently in the reference. I understand that inherency requires a showing that
`
`the missing descriptive matter in the claim is necessarily present in the allegedly
`
`anticipating reference, and that it would have been so recognized by a person of
`
`ordinary skill in the art (“POSITA”).
`
`18.
`
`I understand that when a challenged claim covers several structures,
`
`either generically or as alternatives, the claim is deemed anticipated if any of the
`
`structures within the scope of the claim is found in the prior art reference.
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`Petitioner Mercedes Ex-1034
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`

`

`U.S. Patent No. 10,049,080
`Declaration of Robert Horst
`19. Although anticipation typically involves the analysis of a single prior
`
`art reference, I understand that additional references may be used to show that the
`
`prior art reference has enabling disclosure (i.e., allows a POSITA to make the
`
`invention without undue experimentation), to explain the meaning of a term used
`
`in the prior art reference, and/or to show that a characteristic is inherent in the prior
`
`art reference.
`
`B. Obviousness
`
`20.
`
`I understand that a claim is invalid as obvious if it would have been
`
`obvious to a person of ordinary skill in the art at the time the alleged invention was
`
`made. This means that even if all of the elements of the claim cannot be found in a
`
`single prior art reference that would anticipate the claim, a person of ordinary skill
`
`in the art who was aware of the prior art would have been able to come up with the
`
`claimed invention. This may be the case, for example, where the missing element
`
`represents only an insubstantial different over the prior art or a reconfiguration of a
`
`known system. I understand that in an obviousness determination, the person of
`
`ordinary skill in the art is presumed to have knowledge of all material prior art.
`
`21.
`
`I understand that an obviousness analysis requires an understanding of
`
`the scope and content of the prior art, any differences between the alleged
`
`invention and the prior art, and the level of ordinary skill in evaluating the
`
`pertinent art.
`
`
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`- 9 -
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`Petitioner Mercedes Ex-1034
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`

`

`U.S. Patent No. 10,049