1[pre]. A multi-core processor
`comprising:
`
`U.S. Patent No. 10,049,080
`9[pre]. A method comprising:
`
`1[a][i]. a first plurality of cores and a
`second plurality of cores that support a
`same instruction set,
`
`1[a][ii]. wherein the second plurality of
`cores consume less power, for a same
`applied operating frequency and supply
`voltage, than the first plurality of cores;
`and
`1[b][i]. power management hardware to,
`from a state where the first plurality of
`cores and the second plurality of cores are
`enabled, disable all of the first plurality of
`cores for a drop in demand below a
`threshold without disabling any of the
`second plurality of cores,
`
`9[a][i]. operating a multi-core processor
`such that a first plurality of cores and a
`second plurality of cores execute a same
`instruction set,
`9[a][ii]. wherein the second plurality of
`cores consume less power, for a same
`applied operating frequency and supply
`voltage, than the first plurality of cores;
`and
`9[b][i]. disabling with power management
`hardware, from a state where the first
`plurality of cores and the second plurality
`of cores are enabled, all of the first
`plurality of cores for a drop in demand
`below a threshold without disabling any
`of the second plurality of cores,
`
`1[b][ii]. wherein an operating system to
`execute on the multi-core processor is to
`monitor a demand for the multi-core
`processor and control the power
`management hardware based on the
`demand.
`2. The multi-core processor of claim 1,
`wherein the second plurality of cores
`
`9[b][ii]. wherein an operating system
`executing on the multi-core processor
`monitors a demand for the multi-core
`processor and controls the power
`management hardware based on the
`demand.
`10. The method of claim 9, wherein the
`operating of the second plurality of cores
`
`17[pre]. A non-transitory machine
`readable medium containing program
`code that when processed by a machine
`causes a method to be performed, the
`method comprising:
`17[a][i]. operating a multi-core processor
`such that a first plurality of cores and a
`second plurality of cores execute a same
`instruction set,
`17[a][ii]. wherein the second plurality of
`cores consume less power, for a same
`applied operating frequency and supply
`voltage, than the first plurality of cores;
`and
`17[b][i]. disabling with power
`management hardware, from a state where
`the first plurality of cores and the second
`plurality of cores are enabled, all of the
`first plurality of cores for a drop in
`demand below a threshold without
`disabling any of the second plurality of
`cores,
`17[b][ii]. wherein an operating system
`executing on the multi-core processor
`monitors a demand for the multi-core
`processor and controls the power
`management hardware based on the
`demand.
`18. The non-transitory machine readable
`medium of claim 17, wherein the
`
`Petitioner Mercedes Ex-1020, 0001
`
`

`

`comprise logic gates that have narrower
`logic gate driver transistors than
`corresponding logic gates of the first
`plurality of cores.
`
`comprises driving logic gates that have
`narrower logic gate driver transistors than
`corresponding logic gates of the first
`plurality of cores.
`
`3. The multi-core processor of claim 1,
`wherein the second plurality of cores
`comprise logic gates that consume less
`power than corresponding logic gates of
`the first plurality of cores.
`
`11. The method of claim 9, wherein the
`operating of the second plurality of cores
`comprises driving logic gates that
`consume less power than corresponding
`logic gates of the first plurality of cores.
`
`4. The multi-core processor of claim 1,
`wherein the second plurality of cores each
`have a maximum operating frequency that
`is less than a maximum operating
`frequency of the first plurality of cores.
`
`12. The method of claim 9, wherein the
`operating comprises operating the second
`plurality of cores at a maximum operating
`frequency that is less than a maximum
`operating frequency of the first plurality
`of cores.
`
`5[a]. The multi-core processor of claim 1,
`wherein the power management hardware
`is to disable an additional core of the
`second plurality of cores for each
`continued drop in demand below a next
`lower threshold until one core of the
`second plurality of cores remains enabled,
`and
`
`13[a]. The method of claim 9, further
`comprising disabling, with the power
`management hardware, an additional core
`of the second plurality of cores for each
`continued drop in demand below a next
`lower threshold until one core of the
`second plurality of cores remains enabled,
`and
`
`5[b]. lower and operating frequency or a
`supply voltage of the one core of the
`second plurality of cores as demand drops
`below a next lower threshold.
`
`13[b]. lowering an operating frequency or
`a supply voltage of the one core of the
`second plurality of cores as demand crops
`below a next lower threshold.
`
`operating of the second plurality of cores
`comprises driving logic gates that have
`narrower logic gate driver transistors than
`corresponding logic gates of the first
`plurality of cores.
`19. The non-transitory machine readable
`medium of claim 17, wherein the
`operating of the second plurality of cores
`comprises driving logic gates that
`consume less power than corresponding
`logic gates of the first plurality of cores.
`20. The non-transitory machine readable
`medium of claim 17, wherein the
`operating comprises operating the second
`plurality of cores at a maximum operating
`frequency that is less than a maximum
`operating frequency of the first plurality
`of cores.
`21[a]. The non-transitory machine
`readable medium of claim 17, further
`comprising disabling, with the power
`management hardware, an additional core
`of the second plurality of cores for each
`continued drop in demand below a next
`lower threshold until one core of the
`second plurality of cores remains enabled,
`and
`21[b]. lowering an operating frequency or
`a supply voltage of the one core of the
`second plurality of cores as demand drops
`below a next lower threshold.
`
`Petitioner Mercedes Ex-1020, 0002
`
`

`

`6. The multi-core processor of claim 5,
`wherein the power management hardware
`is to raise a supply voltage or an operating
`frequency of said one core in response to
`higher demand.
`
`14. The method of claim 13, further
`comprising raising, with the power
`management hardware, a supply voltage
`or an operating frequency of said one core
`in response to higher demand, wherein an
`operating system executing on the multi-
`core processor monitors a demand for the
`multi-core processor and controls the
`power management hardware based on the
`demand.
`
`7. The multi-core processor of claim 1,
`wherein the first plurality of cores are at a
`maximum operating frequency in the
`state.
`
`15. The method of claim 9, wherein the
`operating comprises operating the first
`plurality of cores at a maximum operating
`frequency in the state.
`
`8[pre]. The multi-core processor of claim
`1, wherein
`
`16[pre]. The method of claim 9, further
`comprising
`
`8[a]. the power management hardware is
`to enable all of the first plurality of cores
`for an increase in demand above the
`threshold without disabling any of the
`second plurality of cores,
`
`8[b]. wherein an operating system is to
`monitor a demand for the multi-core
`processor and control the power
`management hardware based on the
`demand.
`
`16[a]. enabling, with the power
`management hardware, all of the first
`plurality of cores for an increase in
`demand above the threshold without
`disabling any of the second plurality of
`cores,
`16[b]. wherein an operating system is to
`monitor a demand for the multi-core
`processor and control the power
`management hardware based on the
`demand.
`
`
`
`22. The non-transitory machine readable
`medium of claim 21, further comprising
`raising, with the power management
`hardware, a supply voltage or an operating
`frequency of said one core in response to
`higher demand, wherein an operating
`system executing on the multi-core
`processor monitors a demand for the
`multi-core processor and controls the
`power management hardware based on the
`demand.
`23. The non-transitory machine readable
`medium of claim 17, wherein the
`operating comprises operating the first
`plurality of cores at a maximum operating
`frequency in the state.
`24[pre]. The non-transitory machine
`readable medium of claim 17, further
`comprising
`24[a]. enabling, with the power
`management hardware, all of the first
`plurality of cores for an increase in
`demand above the threshold without
`disabling any of the second plurality of
`cores,
`24[b]. wherein an operating system is to
`monitor a demand for the multi-core
`processor and control the power
`management hardware based on the
`demand.
`
`Petitioner Mercedes Ex-1020, 0003
`
`