(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2007/0083785 A1
`Sutardja
`(43) Pub. Date:
`Apr. 12, 2007
`
`US 20070083785A1
`
`(54)
`
`(76)
`
`(21)
`(22)
`
`(63)
`
`(60)
`
`SYSTEM WITH HIGH POWER AND LOW
`POWER PROCESSORS AND THREAD
`TRANSFER
`
`Inventor: Sehat Sutardja, Los Altos Hills, CA
`(US)
`Correspondence Address:
`HARNESS, DICKEY & PIERCE P.L.C.
`5445 CORPORATE DRIVE
`SUTE 200
`TROY, MI 48098 (US)
`Appl. No.:
`11/523,996
`Filed:
`Sep. 20, 2006
`
`Related U.S. Application Data
`Continuation-in-part of application No. 1 1/503,016,
`filed on Aug. 11, 2006, and which is a continuation
`in-part of application No. 10/865.368, filed on Jun.
`10, 2004, and which is a continuation-in-part of
`application No. 11/322,447, filed on Dec. 29, 2005.
`Provisional application No. 60/825,368, filed on Sep.
`12, 2006. Provisional application No. 60/823,453,
`filed on Aug. 24, 2006. Provisional application No.
`
`60/822,015, filed on Aug. 10, 2006. Provisional appli
`cation No. 60/820,867, filed on Jul. 31, 2006. Provi
`sional application No. 60/799,151, filed on May 10,
`2006. Provisional application No. 60/678.249, filed
`on May 5, 2005.
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F I/00
`(52) U.S. Cl. .............................................................. 713/323
`
`(57)
`
`ABSTRACT
`
`A system on chip (SOC) includes first and second processors
`and a control module. The first processor implemented by
`the SOC has active and inactive states and processes first and
`second sets of threads during the active state. The second
`processor implemented by the SOC has active and inactive
`states, wherein the second processor consumes less power
`when operating in the active state than the first processor
`operating in the active state. The control module, imple
`mented by the SOC communicates with the first and second
`processors, selectively transfers the second set of threads
`from the first processor to the second processor and selects
`the inactive state of the first processor. The second processor
`processes the second set of threads.
`
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`Patent Application Publication Apr. 12, 2007 Sheet 1 of 47
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`
`Petitioner Mercedes Ex-1008, 0041
`
`

`

`Patent Application Publication Apr. 12,2007 Sheet 41 of 47
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`US 2007/0083785 A1
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`Petitioner Mercedes Ex-1008, 0042
`
`Petitioner Mercedes Ex-1008, 0042
`
`
`
`
`
`

`

`Patent Application Publication Apr. 12, 2007 Sheet 42 of 47
`
`US 2007/0083785 A1
`
`1500
`
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`mode?
`
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`to LP mode?
`
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`to HP mode?
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`
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`
`1544
`
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`and other info
`transferred?
`
`1546
`
`Transition LP
`processor or GPU to
`inactive mode.
`
`Petitioner Mercedes Ex-1008, 0043
`
`

`

`Patent Application Publication Apr. 12, 2007 Sheet 43 of 47
`
`US 2007/0083785 A1
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`
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`
`Petitioner Mercedes Ex-1008, 0044
`
`

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`Patent Application Publication Apr. 12,2007 Sheet 44 of 47
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`US 2007/0083785 A1
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`Petitioner Mercedes Ex-1008, 0045
`
`Petitioner Mercedes Ex-1008, 0045
`
`
`

`

`Patent Application Publication Apr. 12, 2007 Sheet 45 of 47
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`US 2007/0083785 A1
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`Petitioner Mercedes Ex-1008, 0046
`
`

`

`Patent Application Publication Apr. 12,2007 Sheet 46 of 47
`
`US 2007/0083785 A1
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`Petitioner Mercedes Ex-1008, 0047
`
`Petitioner Mercedes Ex-1008, 0047
`
`
`
`
`
`
`
`

`

`Patent Application Publication Apr. 12,2007 Sheet 47 of 47
`
`US 2007/0083785 A1
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`Petitioner Mercedes Ex-1008, 0048
`
`Petitioner Mercedes Ex-1008, 0048
`
`
`
`

`

`US 2007/0O83785 A1
`
`Apr. 12, 2007
`
`SYSTEM WITH HIGH POWER AND LOW POWER
`PROCESSORS AND THREAD TRANSFER
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`0001. This application claims the benefit of Provisional
`Application No. 60/825,368, filed Sep. 12, 2006, 60/823,
`453, filed Aug. 24, 2006, and 60/822,015, filed Aug. 10,
`2006 and is a continuation-in-part of U.S. patent application
`Ser. No. 11/503,016, filed on Aug. 11, 2006, which claims of
`the benefit of Provisional Application Ser. No. 60/820,867
`filed on Jul. 31, 2006, and Provisional Application Ser. No.
`60/799,151 filed on May 10, 2006, which is a continuation
`in-part of U.S. patent application Ser. No. 10/865,368, filed
`on Jun. 10, 2004, and a continuation-in-part of U.S. patent
`application Ser. No. 1 1/322,447, which was filed on Dec. 29.
`2005 and which claims the benefit of Provisional Applica
`tion Ser. No. 60/678.249 filed on May 5, 2005.
`0002 This application is related to U.S. patent applica
`tion Ser. No. 10/779,544, which was filed on Feb. 13, 2004,
`and is related to U.S. patent application Ser. No. 10/865,732,
`which was filed on Jun. 10, 2004. The disclosures of these
`applications are all hereby incorporated by reference in their
`entirety.
`
`FIELD OF THE INVENTION
`0003. The present invention relates to data storage sys
`tems, and more particularly to low power data storage
`systems.
`
`BACKGROUND OF THE INVENTION
`0004 Laptop computers are powered using both line
`power and battery power. The processor, graphics processor,
`memory and display of the laptop computer consume a
`significant amount of power during operation. One signifi
`cant limitation of laptop computers relates to the amount of
`time that the laptop can be operated using batteries without
`recharging. The relatively high power dissipation of the
`laptop computer usually corresponds to a relatively short
`battery life.
`0005 Referring now to FIG. 1A, an exemplary computer
`architecture 4 is shown to include a processor 6 with
`memory 7 Such as cache. The processor 6 communicates
`with an input/output (I/O) interface 8. Volatile memory 9
`such as random access memory (RAM) 10 and/or other
`Suitable electronic data storage also communicates with the
`interface 8. A graphics processor 11 and memory 12 Such as
`cache increase the speed of graphics processing and perfor
`aCC.
`0006. One or more I/O devices such as a keyboard 13 and
`a pointing device 14 (Such as a mouse and/or other Suitable
`device) communicate with the interface 8. A high power disk
`drive (HPDD) 15 such as a hard disk drive having one or
`more platters with a diameter greater than 1.8" provides
`nonvolatile memory, stores data and communicates with the
`interface 8. The HPDD 15 typically consumes a relatively
`high amount of power during operation. When operating on
`batteries, frequent use of the HPDD 15 will significantly
`decrease battery life. The computer architecture 4 also
`includes a display 16, an audio output device 17 Such as
`audio speakers and/or other input/output devices that are
`generally identified at 18.
`
`0007 Referring now to FIG. 1B, an exemplary computer
`architecture 20 includes a processing chipset 22 and an I/O
`chipset 24. For example, the computer architecture may be
`a Northbridge/Southbridge architecture (with the processing
`chipset corresponding to the Northbridge chipset and the I/O
`chipset corresponding to the Southbridge chipset) or other
`similar architecture. The processing chipset 22 communi
`cates with a processor 25 and a graphics processor 26 via a
`system bus 27. The processing chipset 22 controls interac
`tion with volatile memory 28 (such as external DRAM or
`other memory), a Peripheral Component Interconnect (PCI)
`bus 30, and/or Level 2 cache 32. Level 1 cache 33 and 34
`may be associated with the processor 25 and/or the graphics
`processor 26, respectively. In an alternate embodiment, an
`Accelerated Graphics Port (AGP) (not shown) communi
`cates with the processing chipset 22 instead of and/or in
`addition to the graphics processor 26. The processing chipset
`22 is typically but not necessarily implemented using mul
`tiple chips. PCI slots 36 interface with the PCI bus 30.
`0008. The I/O chipset 24 manages the basic forms of
`input/output (I/O). The I/O chipset 24 communicates with an
`Universal Serial Bus (USB) 40, an audio device 41, a
`keyboard (KBD) and/or pointing device 42, and a Basic
`Input/Output System (BIOS) 43 via an Industry Standard
`Architecture (ISA) bus 44. Unlike the processing chipset 22,
`the I/O chipset 24 is typically (but not necessarily) imple
`mented using a single chip, which is connected to the PCI
`bus 30. A HPDD 50 such as a hard disk drive also commu
`nicates with the I/O chipset 24. The HPDD 50 stores a
`full-featured operating system (OS) such as Windows XPR)
`Windows 2000(R), Linux and MAC(R)-based OS that is
`executed by the processor 25.
`SUMMARY OF THE INVENTION
`0009. A system on chip (SOC) comprises a first processor
`implemented by the SOC that has active and inactive states
`and that processes first and second sets of threads during the
`active state and a second processor implemented by the SOC
`that has active and inactive states, wherein the second
`processor consumes less power when operating in the active
`state than the first processor operating in the active state. The
`SOC further comprises a control module, implemented by
`the SOC that communicates with the first and second
`processors, that selectively transfers the second set of
`threads from the first processor to the second processor and
`selects the inactive state of the first processor. The second
`processor processes the second set of threads.
`0010. In another feature, the SOC further comprises a
`register file implemented by the SOC that communicates
`with the first processor and the second processor, and that
`stores thread information for the first and second processors.
`The thread information includes at least one of registers,
`checkpoints, and program counters for the threads of the first
`and second processors.
`0011. In another feature, the SOC further comprises a
`first register file that communicates with the first processor
`and that stores first thread information for the first processor
`and a second register file that communicates with the second
`processor and that stores second thread information for the
`second processor. The first and second thread information
`includes at least one of registers, checkpoints, and program
`counters for the threads of the first and second processors,
`respectively.
`
`Petitioner Mercedes Ex-1008, 0049
`
`

`

`US 2007/0O83785 A1
`
`Apr. 12, 2007
`
`0012. In another feature, the control module transfers the
`thread information from the first register file to the second
`register file when transferring the threads from the first
`processor to the second processor.
`0013 In another feature, the first processor includes first
`transistors and the second processor includes second tran
`sistors, and wherein the first transistors have a higher
`leakage current than the second transistors.
`0014. In another feature, the first processor includes first
`transistors and the second processor includes second tran
`sistors, and wherein the second transistors have a greater
`size than the first transistors.
`0015. In another feature, the SOC is in a high-power
`mode when the first processor is in an active state and a
`low-power mode when the first processor is in an inactive
`State.
`In another feature, the first and second processors
`0016.
`comprise first and second graphics processing units, respec
`tively.
`0017. In still other features, a method for processing data
`comprises implementing first and second processors on a
`system on chip (SOC), wherein the first and second proces
`sors have active and inactive states, and wherein the second
`processor consumes less power when operating in the active
`state than the first processor operating in the active state. The
`method further comprises processing first and second sets of
`threads during the active state using the first processor,
`selectively transferring the second set of threads from the
`first processor to the second processor; selecting the inactive
`state of the first processor; and processing the second set of
`threads using the second processor.
`0018. In another feature, the method further comprises
`implementing a register file using the SOC and storing
`thread information for the first and second processors in the
`register file. The thread information includes at least one of
`registers, checkpoints, and program counters for the threads
`of the first and second processors.
`0019. In another feature, the method further comprises
`implementing a first register file using the SOC, storing first
`thread information for the first processor in the first register
`file, implementing a second register file using the SOC, and
`storing second thread information for the second processor.
`The first and second thread information includes at least one
`of registers, checkpoints, and program counters for the
`threads of the first and second processors, respectively.
`0020. In another feature, the method further comprises
`transferring the thread information from the first register file
`to the second register file when transferring the threads from
`the first processor to the second processor.
`0021. In another feature, the first processor includes first
`transistors and the second processor includes second tran
`sistors, and wherein the first transistors have a higher
`leakage current than the second transistors.
`0022. In another feature, the first processor includes first
`transistors and the second processor includes second tran
`sistors, and wherein the second transistors have a greater
`size than the first transistors.
`0023. In another feature, the method further comprises
`operating in a high-power mode when the first processor is
`
`in an active state and in a low-power mode when the first
`processor is in an inactive state.
`0024. In another feature, the first and second processors
`comprise first and second graphics processing units, respec
`tively.
`0025. In still other features, a system on chip (SOC)
`comprises first processing means, implemented by the SOC
`that has active and inactive states, for processing first and
`second sets of threads during the active state. The SOC
`further comprises second processing means for processing,
`that is implemented by the SOC and that has active and
`inactive states, wherein the second processing means con
`Sumes less power when operating in the active state than the
`first processing means operating in the active state. The SOC
`further comprises control means, implemented by the SOC,
`for communicating with the first and second processing
`means, for selectively transferring the second set of threads
`from the first processing means to the second processing
`means and selecting the inactive state of the first processing
`means. The second processing means processes the second
`set of threads.
`0026.
`In another feature, the SOC further comprises
`register means, implemented by the SOC and that commu
`nicates with the first processing means and the second
`processing means, for storing thread information for the first
`and second processing means. The thread information
`includes at least one of registers, checkpoints and program
`counters for the threads of the first and second processing
`CaS.
`0027. In another feature, the SOC further comprises first
`register means that communicates with the first processing
`means for storing first thread information for the first
`processing means and second register means that commu
`nicates with the second processing means for storing second
`thread information for the second processing means. The
`first and second thread information includes at least one of
`registers, checkpoints, and program counters for the threads
`of the first and second processing means, respectively.
`0028. In another feature, the control means transfers the
`thread information from the first register means to the
`second register means when transferring the threads from
`the first processing means to the second processing means.
`0029. In another feature, the first processing means
`includes first transistors and the second processing means
`includes second transistors, and wherein the first transistors
`have a higher leakage current than the second transistors.
`0030. In another feature, the first processing means
`includes first transistors and the second processing means
`includes second transistors, and wherein the second transis
`tors have a greater size than the first transistors.
`0031. In another feature, the SOC is in a high-power
`mode when the first processing means is in an active state
`and a low-power mode when the first processing means is in
`an inactive state.
`0032. In another feature, the first and second processing
`means comprise first and second graphics processing means
`for processing graphics, respectively.
`0033. In still other features, a processing system com
`prises a first processor that has active and inactive states and
`
`Petitioner Mercedes Ex-1008, 0050
`
`

`

`US 2007/0O83785 A1
`
`Apr. 12, 2007
`
`that processes at least one thread during the active state and
`a second processor that has active and inactive states,
`wherein the second processor consumes less power when
`operating in the active state than the first processor operating
`in the active state. The processing system further comprises
`a control module that communicates with the first and
`second processors, and that selectively transfers the at least
`one thread from the first processor to the second processor
`and selects the inactive state of the first processor. The
`second processor processes the at least one thread.
`0034. In another feature, the processing system further
`comprises a register file implemented by the SOC that
`communicates with the first processor and the second pro
`cessor and that stores thread information for the first and
`second processors, wherein the thread information includes
`at least one of registers, checkpoints, and program counters
`for the threads of the first and second processors.
`0035) In another feature, a system on chip (SOC) com
`prises the first and second processors and the register file.
`0036). In another feature, the processing system further
`comprises a first register file that communicates with the first
`processor and that stores first thread information for the first
`processor and a second register file that communicates with
`the second processor and that stores second thread informa
`tion for the second processor, wherein the first and second
`thread information includes at least one of registers, check
`points, and program counters for the threads of the first and
`second processors, respectively.
`0037. In another feature, a system on chip (SOC) com
`prises the first and second processors and the first and second
`register files.
`0038. In another feature, the control module transfers the
`thread information from the first register file to the second
`register file when transferring the threads from the first
`processor to the second processor.
`0039. In another feature, the first processor includes first
`transistors and the second processor includes second tran
`sistors, and wherein the first transistors have a higher
`leakage current than the second transistors.
`0040. In another feature, the first processor includes first
`transistors and the second processor includes second tran
`sistors, and wherein the second transistors have a greater
`size than the first transistors.
`0041. In another feature, the processing system is in a
`high-power mode when the first processor is in an active
`state and a low-power mode when the first processor is in an
`inactive state.
`0042. In another feature, the first and second processors
`comprise first and second graphics processing units, respec
`tively.
`0043. In still other features, a method of processing data
`comprises providing first and second processors, wherein
`the first and second processors have active and inactive
`states, and wherein the second processor consumes less
`power when operating in the active state than the first
`processor operating in the active state. The method further
`comprises processing at least one thread during the active
`state using the first processor, selectively transferring the at
`least one thread from the first processor to the second
`
`processor and selecting the inactive state of the first proces
`Sor, and processing the at least one thread using the second
`processor.
`0044) In another feature, the method further comprises
`implementing a register file using the SOC and storing
`thread information for the first and second processors in the
`register file, wherein the thread information includes at least
`one of registers, checkpoints and program counters for the
`threads of the first and second processors.
`0045. In another feature, the method further comprises
`implementing the register file, the first processor and the
`second processor in a system on chip.
`0046.
`In another feature, the method further comprises
`implementing a first register file using the SOC, storing first
`thread information for the first processor in the first register
`file, implementing a second register file using the SOC, and
`storing second thread information for the second processor,
`wherein the first and second thread information includes at
`least one of registers, checkpoints, and program counters for
`the threads of the first and second processors, respectively.
`0047. In another feature, the method further comprises
`implementing the first and second register files, the first
`processor and the second processor in a system on chip.
`