(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2004/0249964 A1
`Mougel
`(43) Pub. Date:
`Dec. 9, 2004
`
`US 2004O249964A1
`
`(54) METHOD OF DATA TRANSFER AND
`APPARATUS THEREFOR
`
`(76) Inventor: Thibault Mougel, West Lothian (GB)
`Correspondence Address:
`PERMAN & GREEN
`425 POST ROAD
`FAIRFIELD, CT 06824 (US)
`
`(21)
`(22)
`
`(51)
`
`Appl. No.:
`Filed:
`C
`
`10/382,547
`Mar. 6, 2003
`ar. 0,
`Publication Classification
`
`Int. Cl. ................................................ G06F 15/16
`
`(52) U.S. Cl. .............................................................. 709/231
`
`(57)
`
`ABSTRACT
`
`In the field of programmable devices, such as FPGAs,
`comprising multi-gigabit transceiver units, it is desirable to
`communicate a data Stream of a first data rate between the
`programmable devices at a Second data rate. In order to
`achieve this aim, the data Stream is read from a first buffer
`at the Second data rate by a first device and communicated
`to a second device at the second data rate. When the buffer
`empties, idle bits are inserted in the absence of data. Upon
`receipt by the second device, the idle bits are identified and
`removed prior to buffering.
`
`Optical
`Optical -----Transmission
`clock
`Transmitter
`102
`105
`
`
`
`
`
`Optical
`Receiver
`103
`
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`is
`
`O
`t
`t
`
`
`
`cg..." a
`Transmitter
`101
`
`a
`
`area
`
`A.
`Transceiver
`FPGA
`104.
`
`Recovered
`Clock from
`Optical
`Receiver
`
`110
`Processing
`FPGA 1
`112
`
`TX
`Processing
`FPGA2
`126
`
`S.
`
`
`
`100
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`To Main Processor
`
`114
`Processing
`FPGA1
`116
`
`RX
`Processing
`FPGA2
`132
`
`138
`
`Data to be processed
`Control, status and
`error signals
`
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`Patent Application Publication Dec. 9, 2004 Sheet 1 of 3
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`US 2004/0249964 A1
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`Optical
`Transmitter
`102
`
`Optical
`---Transmission
`clock
`105
`
`
`
`
`
`Optical
`Receiver
`103
`
`C
`s
`
`Clock from
`--------
`Optical
`Transmitter
`
`
`
`Transceiver
`
`FPGA
`104
`
`a
`
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`
`a
`
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`
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`
`- Clock from
`
`Recovered
`Optical
`Receiver
`
`
`
`
`
`
`
`Processing
`T
`FPGA1
`112
`
`TX
`Processing
`FPGA2
`126
`
`
`
`
`
`
`
`Bridge
`150
`
`148
`
`To Main Processor
`
`Processing
`R
`FPGA1
`116
`
`RX
`Processing
`FPGA2
`132
`
`138
`
`Data to be processed
`Control, status and
`error signals
`
`Fig 1
`
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`Patent Application Publication Dec. 9, 2004
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`US 2004/0249964 A1
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`Patent Application Publication Dec. 9, 2004 Sheet 3 of 3
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`US 2004/0249964 A1
`
`
`
`
`
`Receive SONET
`data stream
`
`Buffer <
`half full
`
`
`
`
`
`Insert idle
`bytes
`
`
`
`
`
`Split data
`Stream
`
`
`
`Clock data
`to databuS
`
`30
`
`308
`
`30
`4
`
`Fig. 3
`
`
`
`
`
`Receive Sub
`data Streams
`
`ReCOnstitute
`data Stream
`
`400
`
`402
`
`
`
`
`
`ldle bytes s Clock data
`?
`to FIFO
`
`408
`
`404
`
`
`
`
`
`Yes
`Remove idle
`bytes
`
`406
`
`F. 4
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`US 2004/0249964 A1
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`Dec. 9, 2004
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`METHOD OF DATA TRANSFER AND APPARATUS
`THEREFOR
`
`FIELD OF THE INVENTION
`0001. The present invention relates, in general, to a
`method of transferring a data Stream of a first data rate over
`a data link at a Second data rate. The present invention also
`relates, in general, to an apparatus for transferring a data
`Stream of a first data rate over a data link at a Second data
`rate.
`
`DESCRIPTION OF THE BACKGROUND ART
`0002. In the field of optical communications, an optical
`communications network is formed from a large number of
`different hardware and Software components. Clearly, there
`is therefore a need for test equipment in order to measure the
`integrity of Signals generated in the network. Such test
`equipment is able to transmit test Signals comprising test
`frames representative of actual Signals communicated in the
`network. The test equipment may also receive the test
`frames, and detect and record any errors.
`0003) Certain test equipment comprises a number of
`Field Programmable Gate Arrays (FPGAS) and/or Applica
`tion Specific Integrated Circuits (ASICs) in order to com
`plete certain high-speed computational tasks associated with
`the tests to be performed. For example, it is known for Some
`test equipment to generate a So-called Bit-Error-Ratio Test
`(BERT) set, and/or error performance data. However, such
`tests are processing power intensive due to the amount of
`data that needs to be processed by a single FPGA at high
`Speed.
`0004) Of recent, manufacturers of FPGAs have begun to
`design the FPGAs with multi-gigabit serial transceivers that
`Support a communications protocol, Such as a So-called
`XAUIs (pronounced “Zowies'; X Attachment Unit Inter
`faces; the “X” representing the Roman numeral for ten)
`protocol to enable communication of data between FPGAs
`at high Speed, thereby allowing the computational burden to
`be shared between the FPGAs. The XAUI is a low pin count,
`self-clocked, serial bus protocol directly evolved from the
`Gigabit Ethernet (GbE). The XAUI protocol supports data
`rates 2.5 times that of GbE, and by Supporting communica
`tions over four serial “lanes” a 10 GbE communications link
`is achieved.
`0005. As mentioned above, for certain tests, it is desirable
`to communicate data between FPGAS in order to share a
`computational process, and multi-gigabit Serial transceivers
`provide a mechanism to achieve the desired data transfer via
`a relatively Small number of differential tracks constituting
`a communications link coupling the transceivers. Also, at
`least one known test requires data received by the test
`equipment from a network under test to be sent back to the
`network under test. Therefore, another application exists for
`an FPGA, that is part of a receiver unit of the test equipment,
`to comprise a first multi-gigabit Serial transceiver So as to
`permit communication of received data to another FPGA,
`that is part of a transmitter unit of the test equipment, the
`another FPGA comprising a Second multi-gigabit Serial
`transceiver.
`0006 The speed of the multi-gigabit serial transceivers
`permits the test equipment to process data borne using, for
`
`example, the American National Standards Institute (ANSI)
`Synchronous Optical NETwork (SONET) standard. Of
`course, data conforming to other Standards, Such as the
`Synchronous Digital Hierarchy (SDH) standard can also be
`processed. Indeed, in the case of a network analyser unit
`capable of testing both 10 GbE signals and SONET/SDH
`signals, the communications link between the FPGAs should
`be able to Support the respective data rates associated with
`the signal types to be tested, for example 10 Gbps for the
`GbE packets, or 9.953280 Gbps for SONET OC-192 frames.
`0007 One known multi-gigabit serial communications
`Specification for communicating data between FPGAS Sup
`ports data communications at a rate of 10 Gbps. AS men
`tioned above, one of the various data rates Supported by the
`SONET standard is 9.953280 Gbps for OC-192 frames. A
`data rate mismatch therefore clearly exists if an inter-FPGA
`multi-gigabit Serial communications link is used to commu
`nicate SONET OC-192 frames, which if not removed, will
`result in discrete-time jitter and data loSS.
`0008. In order to facilitate the transfer of an incoming
`data Stream, between FPGAS using the multi-gigabit Serial
`transceivers, when the data rate of the incoming data Stream
`and the data rate of the multi-gigabit Serial transceivers are
`different, it is known to provide an apparatus which adapts
`a clocking frequency of the multi-gigabit Serial transceivers
`to match the clock frequency of the incoming data Stream.
`The frequency matching is performed, for example, by
`coupling FPGAS to external components Such as a Phase
`Locked Loop (PLL) based clock generator, or a Voltage
`Controlled X Oscillator based clock generator, both of
`which are described in the XILINX Application Note
`entitled “SONET Rate Conversation in Virtex-II Pro
`Devices” (Application Note: Virtex-II Pro Family, XA
`pp649 (v1.1), May 14, 2002).
`0009. However, such known apparatus disadvanta
`geously use external components, thereby increasing manu
`facturing overheads. Also, maintaining accuracy of clock
`Synchronization is difficult and complex to achieve. Further
`more, once the apparatus is programmed to be adaptive to a
`Specific incoming data Stream dock frequency, the apparatus
`must be reprogrammed should a data Stream of a different
`frequency be received.
`0010. According to a first aspect of the present invention,
`there is provided a method of communicating a data Stream
`from a first communications unit of a first programmable
`logic device to a Second communications unit of a Second
`programmable logic device at a first data rate, the data
`Stream comprising a plurality of data units and having a
`Second data rate associated there with, the method compris
`ing the Steps of the first communications unit receiving the
`data Stream; generating idle units and transmitting the idle
`units to the Second communications unit when data is
`unavailable to be transmitted to the Second communications
`unit, and wherein the first data rate is greater than or
`Substantially equal to the Second data rate.
`0011. In the context of communication of a data stream,
`an idle unit is a bit pattern indicative of an absence of bits
`constituting the communication of at least part of the data
`Stream.
`0012. The method may further comprise the step of:
`temporarily Storing the data constituting the data Stream
`prior to transmission of the data Stream to the Second
`communications unit.
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`0013 The method may further comprise the step of:
`generating and transmitting the idle units in response to a
`quantity of the temporarily Stored data being equal to or leSS
`than a predetermined level.
`0.014. The communication of the data steam from the first
`communications unit to the Second communications unit
`may be in accordance with a predetermined communications
`protocol; the generation of the idle units may be in accor
`dance with the protocol. A combination of types of idle units
`may be in accordance with the protocol.
`0.015 The data may be temporarily stored in a first buffer;
`the buffer mat have a read-out rate corresponding to the first
`data rate.
`0016. The method may further comprise the step of:
`transmitting the data Stream to the Second communications
`unit at the first data rate.
`0.017. The method may further comprise the step of the
`Second communications unit receiving the data Stream from
`the first communications unit.
`0.018. The method may further comprise the step of:
`removing the idle units from the received data Stream.
`0019. The method may further comprise the step of:
`temporarily Storing the received data Stream after removal of
`the idle units therefrom.
`0020. The plurality of data units may be a plurality of
`packets.
`0021. The plurality of data units may be a plurality of
`frames.
`0022. The first device may be an ASIC or an FPGA.
`0023 The second device may be an ASIC or an FPGA.
`0024 Communication of the idle units between the first
`and Second communications units may result in the idle units
`being interleaved with the data constituting the data Stream.
`0.025 According to a second aspect of the present inven
`tion, there is provided a programmable logic device for
`communicating at a first data rate a data Stream comprising
`a plurality of data units and having a Second data rate
`asSociated there with, the device comprising: a communica
`tions unit arranged to receive, when in use, the data Stream
`at the Second data rate; wherein the communications unit is
`further arranged to generate idle units and transmit the idle
`units at the first data rate when data is unavailable for
`transmission to another programmable logic device at the
`first data rate; and the first data rate being greater than or
`Substantially equal to the Second data rate.
`0026. The communications unit may further comprise: a
`temporary Store for Storing the data constituting the data
`Stream prior to transmission of the data Stream.
`0027. The temporary store may be a first buffer, the first
`buffer may have a read-out rate corresponding to the first
`data rate.
`0028. The communications unit may further comprise: an
`idle unit insertion unit arranged to receive the data Stream
`prior to transmission, and to generate the idle units when
`data is unavailable for transmission to another program
`mable logic device.
`
`0029. The idle units may be generated and transmitted in
`response to a quantity of the temporarily Stored data being
`equal to or less than a predetermined level.
`0030 The idle unit insertion unit may be arranged to
`monitor the amount of data being Stored by the temporary
`StOre.
`0031. The communication of the data steam from the first
`communications unit to the Second communications unit
`may be in accordance with a predetermined communications
`protocol; the generation of the idle units may be in accor
`dance with the protocol. A combination of types of idle units
`may be in accordance with the protocol.
`0032. The idle units may be generated so as to be
`interleaved with data constituting the data Stream when the
`data constituting the data Stream is transmitted by the
`communications unit.
`0033 According to a third aspect of the present inven
`tion, there is provided a programmable logic device for
`receiving at a first data rate a data Stream comprising a
`plurality of data units and having a Second data rate asso
`ciated there with, the device comprising: a communications
`unit arranged to receive, when in use, the data Stream at the
`first data rate; wherein the communications unit is further
`arranged to remove idle units from the data Stream for
`onward communication of the data Stream at the Second data
`rate; and the first data rate is greater than or Substantially
`equal to the Second data rate.
`0034.
`It should be appreciated that onward communica
`tion of the data Stream embraces communication internal of
`a recipient programmable logic device and/or communica
`tion to an entity exterior to the recipient programmable logic
`device.
`0035. The communications device may comprise: an idle
`unit removal unit arranged to remove idle units from the data
`Stream.
`0036) The communications unit may further comprise: a
`temporary Store for receiving the received data Stream after
`removal of the idle units therefrom.
`0037. The temporary store may be arranged so as to
`permit, when in use, data to be read-out of the temporary
`Store at the Second data rate.
`0038. The temporary store may be a buffer having a
`read-out rate associated there with, the read-out rate corre
`sponding, when in use, to the Second data rate.
`0039. According to a fourth aspect of the present inven
`tion, there is provided a communications System for com
`municating at a first data rate a data Stream comprising a
`plurality of data units and having a Second data rate asso
`ciated there with, the System comprising: a first program
`mable logic device comprising a first communications unit
`capable of communicating the data Stream to a Second
`communications unit of a Second programmable logic
`device at the first data rate; wherein the first communications
`unit comprises an idle unit insertion unit arranged to receive
`the data Stream at the Second data rate prior to transmission
`to the Second communications unit, and generate, when in
`use, idle units when data is unavailable for transmission to
`the Second communications unit; the Second communica
`tions unit comprises an idle unit removal unit arranged to
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`remove the idle units from the data stream for onward
`communication of the data Stream at the Second data rate;
`and the first data rate is greater than or Substantially equal to
`the Second data rate.
`0040 According to a fifth aspect of the present invention,
`there is provided a communications network analyser com
`prising the communications System as Set forth above in
`relation to the fourth aspect of the present invention.
`0041. It is thus possible to provide an apparatus for
`transferring incoming data of a first data rate between
`programmable logic devices at different data rate, and a
`method of transferring incoming data of the first data rate
`between programmable logic devices at the different data
`rate. The complexity of the hardware constituting the appa
`ratus is therefore simplified considerably, without the diffi
`culties of clock synchronization. Additionally, the FPGAs do
`not require reprogramming in order to enable the data link
`between the programmable devices to communicate the
`incoming data when the data rate of the incoming data
`changes. It will be appreciated that the greater Simplicity
`reduces the cost of manufacture of test equipment.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0.042 At least one embodiment of the present invention
`will now be described, by way of example only, with
`reference to the accompanying drawing, in which:
`0.043
`FIG. 1 is a Schematic diagram of an apparatus
`constituting a first embodiment of the invention;
`0044 FIG. 2 is a schematic diagram of a communica
`tions link of FIG. 1 in greater detail; and
`004.5 FIGS. 3 and 4 are flow diagrams of methods for
`use with the apparatus of FIG. 2.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Referring to FIG. 1, a telecommunications net
`0.046
`work analyser, capable of testing 10 GbE packets and
`SONET frames, comprises a processing card 100 interfaced
`with an optical transceiver card 101. The optical transceiver
`card 101 comprises, inter alia, an optical transmitter module
`102 comprising a transmitter port (not shown) and an optical
`receiver module 103 comprising a receiver port (not shown).
`The optical transmitter module 102 and the optical receiver
`module 103 are respectively coupled to a transceiver FPGA
`104 by respective standard bus interfaces, such as of a
`SERDES (Serializer-Dezerializer) Framer Interfaced (SFI
`4) type. The transceiver FPGA 104 has an input port 106 and
`an output port 108, the input port 106 of the transceiver
`FPGA 104 being coupled to an output port 110 of a first
`transmitter FPGA 112, and the output port 108 of the
`transceiver FPGA 104 being coupled to a first input port 114
`of a first receiver FPGA116. The input and output ports 106,
`108 of the transceiver FPGA 104 are respectively coupled to
`the output port 110 and the first input port 114 by a
`multi-gigabit data link that is supported by the XAUI
`protocol.
`0047 A first output port 118 of the first receiver FPGA
`116 is coupled to a first input port 120 of the first transmitter
`FPGA 112, a second input port 122 of the first transmitter
`FPGA112 being coupled to an output port 124 of a second
`
`transmitter FPGA 126. A first input port 128 of the second
`transmitter FPGA 126 is coupled to an output port 130 of a
`second receiver FPGA 132, a first input port 134 of the
`second receiver FPGA132 being coupled to a second output
`port 136 of the first receiver FPGA 116.
`0048. The inter-coupling of the first and second transmit
`ter FPGAS 112, 126 and the first and second receiver FPGAs
`116, 132 is by means of a further multi-gigabit data link that
`is supported by the XAUI protocol. A further data bus 138
`for communicating control, Status and/or error Signals is
`coupled to a third input port 140 of the first transmitter
`FPGA112, a second input port 142 of the second transmitter
`FPGA 126, a second input port 144 of the first receiver
`FPGA 116 and a second input port 146 of the second
`receiver FPGA132. The further data bus 138 is also coupled
`to an input port 148 of a bridge FPGA150, the bridge FPGA
`150 being coupled to a main processing unit (not shown), the
`details of which need not be described in further detail for
`the purposes of describing this embodiment of the invention.
`0049. Although not shown, the processing card 100 com
`prises Suitable circuitry, for example oscillator circuits, to
`generate a System clock Signal and a transmission clock
`Signal, the processing card 100 being appropriately config
`ured to communicate the System and transmission clock
`signals to the FPGAs populating the processing card 100.
`0050. The above example will now be described, for the
`purposes of clarity of description and Simplicity, in the
`context of a communications link between the first trans
`mitter FPGA112 and the first receiver FPGA116. However,
`it should be appreciated that the principles of the following
`example is applicable to other communications links
`between devices incorporating transceivers, Such as FPGAS
`and ASICs, and more particularly between the first and
`Second transmitter FPGAS 112, 126 and the first and second
`receiver FPGAs 116, 132.
`0051 Referring to FIG.2, the first transmitter FPGA112
`Supports a multi-gigabit data link 200 by comprising a first
`multi-gigabit Serial transceiver unit 202. In this example, the
`first transmitter FPGA112 is a XilinxCE) Virtex II Pro FPGA
`comprising a Xilinx(R) Rocket I/O transceiver as the first
`transceiver unit 202. The first transceiver unit 202 is pro
`grammed to Support the XAUI protocol.
`0052 The transceiver unit 202 is coupled to an idle byte
`insertion unit 204, via a first internal databuS 206, the idle
`byte insertion unit 204 being coupled to a first First-In-First
`Out (FIFO) buffer 208 via a second internal databus 210.
`The first FIFO buffer 208 comprises a first data-in port 212,
`a first data-out port 214 (coupled to the Second internal
`databus 210), a first write-in clock port 216, a first write
`enable clock port 218, a first read-out clock port 220, a first
`read-enable clock port 222 and a first FIFO status port 224.
`The read-out clock port 220 is coupled to a first serial
`transmission clock port 226 of the idle byte insertion unit
`204, and a first transceiver clock port 227 of the transceiver
`unit 202; the first read-enable clock port 222 is coupled to a
`“Read Data” port 228 of the idle byte insertion unit 204. A
`“Data Request” port 230 of the idle byte insertion unit 204
`is coupled to the first FIFO status port 224 of the first FIFO
`buffer 208.
`0053) The first receiver FPGA 116 also supports the data
`link 200 by comprising a Second multi-gigabit Serial trans
`
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`ceiver unit 232. In this example, the first receiver FPGA 116
`is also a Xilinx(R) Virtex II Pro FPGA also comprising a
`Xilinx(E) Rocket I/O transceiver as the second transceiver
`unit 232, the Second transceiver unit 232 being programmed
`to support the XAUI protocol. The second transceiver unit
`232 is coupled to an idle byte removal unit 234, via a third
`internal databus 236, the idle byte removal unit 234 being
`coupled to a second FIFO buffer 238 via a fourth internal
`databus 240. The second FIFO buffer 238 comprises a
`Second data-in port 242, a Second data-out port 244, a Second
`write-in clock port 246, a Second write-enable clock port
`250, a second read-out clock port 252, a second read-enable
`clock port 254 and a second FIFO status port 256.
`0.054 The second write-in clock port 246 is coupled to a
`second serial transmission clock port 258 of the idle byte
`removal unit 234 and a second transceiver clock port 260 of
`the second transceiver 232. The second write-in clock port
`246, the second serial transmission clock port 258, the
`Second transceiver clock port 260, the first transceiver clock
`port 227, the first serial transmission clock port 226 and the
`first read-out clock port 220 are coupled to a Source of the
`transmission clock signal (not shown) already mentioned
`above in relation to FIG. 1. The second write-enable clock
`port 250 is coupled to a “Write Data” port 262 of the idle
`byte removal unit 234.
`0055. The first transceiver unit 202 is capable of com
`municating with the Second transceiver unit 232 via the
`muti-gigabit data link 200. The first transceiver unit 202 and
`the second transceiver unit 232 are therefore both coupled to
`the data link 200 at opposite ends. The data link 200
`comprises four data lanes 262 provided in accordance with
`the multi-gigabit Serial communications Specification being
`employed, in this example that Supporting the Rocket I/O
`transceivers.
`0056. The above described apparatus will now be
`described in the context of communication between the first
`transmitter FPGA 112 and the first receiver FPGA 116.
`However, as previously Stated, it should be appreciated that
`the following example is applicable to communications
`between other FPGAs comprising transceivers.
`0057. In operation, an incoming data stream (not shown)
`is received (step 300) by the first transmitter FPGA 112. In
`this example, the incoming data stream is a SONET OC-192
`Signal. The incoming data Stream is communicated to the
`first FIFO buffer 208 via the first data-in port 212 and written
`into the first FIFO buffer 208 at a first data rate of the
`incoming data Stream by applying the System clock signal to
`the first write-in clock port 216 and a first clock enable
`signal to the first write-enable port 218. Since the first
`transmitter FPGA112 can process data at a far greater Speed
`than the first data rate of the incoming datastream, the first
`clock enable signal is used to control the writing-in of data
`into the first FIFO buffer 208. The first clock enable signal
`is, in this example, generated Separately by the first trans
`mitter FPGA 112. For example, in the case of the SONET
`OC-192 Signal, the first data rate at which the incoming data
`Stream is written into the first FIFO buffer 208 is 9.953280
`Gbps. Given that the system clock frequency is 84 MHZ and
`the first transmitter FPGA112 can process 128 bits per cycle
`of the System clock, the first clock enable Signal is set to
`enable the system clock with respect to the first FIFO buffer
`208 once every 1.08 clock cycles of the system clock.
`
`0.058. In the first transmitter FPGA112, the transmission
`clock signal is applied to the first read-out clock port 220 of
`the first FIFO buffer 208, first serial transmission clock port
`226 of the idle byte insertion unit 204 and the transceiver
`clock port 227 in order to clock data from the first FIFO
`buffer 208 into the idle byte insertion unit 204 prior to
`communication to the first transceiver unit 202. The idle
`byte insertion unit 204 controls when data is read-out of the
`first FIFO buffer 208 by issuing a “read data” control signal
`at the read data port 228. The status of the read data control
`signal at the first read-enable port 222 of the first FIFO
`buffer 208 determines whether or not the transmission clock
`signal is enabled with respect to the first FIFO buffer 208 to
`allow data to be read-out of the first FIFO buffer 208. The
`transmission clock Signal is predetermined and corresponds
`to a Second data rate that is greater than or equal to, the
`maximum data rate of the incoming data Stream, i.e. the first
`data rate. Consequently, in this example, the frequency of
`the transmission clock signal is 156.25 MHz to accommo
`date a 10 Gbps data throughput across the four lanes 262 of
`the data link 200.
`0059) Clearly, the first FIFO buffer 208 is therefore being
`emptied at a rate greater than the first FIFO buffer 208 is
`being filled. Consequently, data is only read-out of the first
`FIFO buffer 208 when the first FIFO buffer 208 is half-full.
`The status of the first FIFO buffer 208 is monitored (step
`302) by the idle byte insertion unit 204 by monitoring the
`depth of the first FIFO buffer 208 via the first FIFO status
`port 224.
`0060. When the first FIFO buffer 208 is determined to be
`less than half-full by the idle byte insertion unit 204, the idle
`byte insertion unit 204 stops reading data out of the first
`FIFO buffer 208. Consequently, data to be communicated to
`the first transceiver unit 202 is absent, and so the idle byte
`insertion unit 204 replaces (step 304) the absence of data
`with one or more predetermined idle byte. In this example,
`the idle bytes can be a random distribution of the different
`types of idle bytes in accordance with rules Specified for the
`use of idle bytes by the XAUI protocol. For example, under
`the XAUI protocol three different types of idle bytes having
`different functions are specified and are termed types R, A
`and K.
`0061. In this example, the data is being transmitted
`between the first and second transceivers 202, 232 in pack
`ets, prior to the interleaving of the idle bytes. Each packet of
`data is preceded by a “Start’ octet and followed by a
`“Terminate” octet. The idle byte insertion unit 204 ensures
`that the idle bytes being interleaved are distributed in Such
`a manner that the distribution of idle bytes conforms to the
`Specification for multi-gigabit communications using the
`first and second transceivers 202,232. Once idle bytes have
`been interleaved, a number of the Start and terminate octets
`are separated by a group of bytes constituting at least one
`valid idle sequence as defined by the XAUI protocol.
`0062) The data stream, as adapted by the idle byte inser
`tion unit 204, is divided (step 306) into four separate sub-bit
`Streams for respective communication via the four lanes 262
`in accordance with the multi-gigabit communication Speci
`fication, the divided data being transmitted (step 308) to the
`Second transceiver unit 232. At the Second transceiver unit
`232, the Sub-bit streams are received (step 400) at the second
`data rate corresponding to the transmission clock frequency
`
`Ex.1033
`CISCO SYSTEMS, INC. / Page 8 of 10
`
`

`

`US 2004/0249964 A1
`
`Dec. 9, 2004
`
`and reconstituted (Step 402) to a single bit stream that was
`the incoming bit stream to the first transceiver 202. The
`reconstituted bit Stream is then communicated to the idle
`byte removal unit 234 of the first receiver FPGA 116 at the
`transmission clock frequency. The idle bytes interleaved
`amongst the packets of data of the reconstituted data Stream
`are then identified (step 404) by the idle byte removal unit
`234 and removed (step 406), when present, from the recon
`stituted stream prior to communication (step 408) of the
`processed data stream to the second FIFO buffer 238 at the
`transmission dock frequency. In this example, the idle bytes
`are removed by Simply not providing a write-enable Signal
`at the write data port 262, thereby preventing the idle bytes
`from being clocked into the second FIFO buffer 238.
`0.063. The data stream is clocked out of the idle byte
`removal unit 234 at the transmission clock frequency, which
`corresponds to a higher data rate than that of the originating
`SONET signal. Consequently, the data written into the
`Second FIFO buffer 218 is then readout of the Second FIFO
`buffer 218 at the clock frequency of the SONET signal, by
`the combined use of the System clock signal and a Second
`read-enable Signal applied to the Second read-out clock port
`252 and the second read-enable port 254 respectively,
`thereby reconstituting the SONET signal. The SONET sig
`nal is then processed further by the first receiver FPGA 116.
`In this example, the Second read-enable Signal is generated
`separately by the first receiver FPGA 116.
`0064. The above described technique for communicating
`SONET data streams between FPGAs is employed, in the
`embodiment described in relation to FIG. 2, in order to
`transmit a SONET data stream received from a network
`under test back to the network under test, with or without
`alterations as necessary for the particular test being carried
`out by the test equipment.
`0065. Alternatively, the same communications technique
`can be employed to communicate SONET data streams
`between the first transmitter FPGA 112 and the second
`transmitter FPGA 126 in order to reduce the processing
`burden on the first transmitter FPGA 112 when checking
`Transport Overhead (TOH) and payload data for errors
`during a test. In Such an example, the payload data can be
`transmitted from the first transmitter FPGA 112 to the
`second transmitter FPGA126 for analysing the payload data
`for errors and, for example, reporting the Status of certain
`bits in the payload, whilst the first transmitter FPGA 112
`analyses the TOH data for errors and, for example, reporting
`the status of certain bits. In the TOH data.
`0.066
`Status information and any errors found in the TOH
`data by the first transm