(12) United States Patent
`Curd et al.
`
`USOO6907595 B2
`US 6,907,595 B2
`Jun. 14, 2005
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) PARTIAL RECONFIGURATION OFA
`PROGRAMMABLE LOGIC DEVICE USING
`AN ON-CHIP PROCESSOR
`
`(75) Inventors: Derek R. Curd, Woodside, CA (US);
`Punit S. Kalra, Superior, CO (US);
`Richard J. LeBlanc, Longmont, CO
`(US); Vincent P. Eck, Loveland, CO
`(US); Stephen W. Trynosky, Boulder,
`CO (US); Jeffrey V. Lindholm,
`Longmont, CO (US); Trevor J. Bauer,
`Boulder, CO (US)
`Assignee: Xilinx, Inc., San Jose, CA (US)
`Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 12 days.
`
`(73)
`(*)
`
`(21)
`(22)
`(65)
`
`(51)
`(52)
`
`(58)
`
`(56)
`
`Appl. No.:
`10/319,051
`Dec. 13, 2002
`Filed:
`Prior Publication Data
`
`US 2004/0113655 A1 Jun. 17, 2004
`Int. Cl................................................. G06F 17/50
`U.S. Cl. ............................. 716/16; 716/17; 716/18;
`326/39; 326/41
`Field of Search ................................. 716/1-2, 7–8,
`71.6/12, 16–18, 20; 326/40, 41, 38
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`Baxter ........................... 71.6/3
`Hartmann
`Agrawal et al. .............. 716/17
`Nishihara
`... 326/41
`Schultz et al. ................ 326/41
`Young et al.
`... 716/16
`Young et al. ...
`Turner et al. ................. 716/17
`
`:
`
`:
`
`:
`
`:
`
`:
`
`6,078,735 A *
`6/2000
`6,096,091 A
`8/2000
`6,128,770 A
`10/2000
`6,304,101 B1
`10/2001
`6,429,682 B1
`8/2002
`6,493,862 B1
`12/2002
`6,526,557 B1 * 2/2003
`6,629,311 B1 * 9/2003
`OTHER PUBLICATIONS
`Virtex-II Pro, Platform FPGA Handbook, Oct. 14, 2002, pp.
`1-589, (v2.0), Xilinx, Inc., 2100 Logic Drive, San Jose, CA
`95124.
`
`“Advance Product Specification,” Virtex-II ProTM Platform
`FPGA Documentation, (Mar. 2002 Release), pp. 1-342,
`Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
`“PPC 405 User Manual,” Virtex-II ProTM Platform FPGA
`Documentation, (Mar. 2002 Release), pp. 343-870, Xilinx,
`Inc., 2100 Logic Drive, San Jose, CA 95124.
`“PPC 405 Processor Block Manual Virtex-II ProTM Plat
`form FPGA Documentation, (Mar. 2002 Release), pp.
`871-1058, Xilnix, Inc., 2100 Logic Drive, San Jose, CA
`95124.
`
`Rocket I/O Transceiver User Guide Virtex-II ProTM Plat
`form FPGA Documentation, (Mar. 2002 Release), pp.
`1059-1150, Xilinx, Inc., 2100 Logic Drive, San Jose, CA
`95124.
`
`* cited by examiner
`
`Primary Examiner Vuthe Siek
`ASSistant Examiner Binh Tat
`(74) Attorney, Agent, or Firm-E. Eric Hoffman; B.
`Hoffman
`ABSTRACT
`(57)
`A programmable logic device, Such as a field programmable
`gate array, is partially reconfigured using a read-modify
`write Scheme that is controlled by a processor. The partial
`reconfiguration includes (1) loading a base set of configu
`ration data values into a configuration memory array of the
`programmable logic device, thereby configuring the pro
`grammable logic device; (2) reading a first frame of con
`figuration data values from the configuration memory array;
`(3) modifying a Subset of the configuration data values in the
`first frame of configuration data values, thereby creating a
`first modified frame of configuration data values, and (4)
`overwriting the first frame of configuration data values in the
`configuration memory array with the first modified frame of
`configuration data values, thereby partially reconfiguring the
`programmable logic device. The Steps of reading, modifying
`and overwriting are performed under the control of a pro
`CCSSO.
`
`19 Claims, 5 Drawing Sheets
`
`200
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`Ex. 1006
`CISCO SYSTEMS, INC. / Page 1 of 13
`
`

`

`U.S. Patent
`
`Jun. 14, 2005
`
`Sheet 1 of 5
`
`US 6,907,595 B2
`
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`CONFIG.
`INTERFACE
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`(PRIOR ART)
`
`Ex. 1006
`CISCO SYSTEMS, INC. / Page 2 of 13
`
`

`

`U.S. Patent
`
`Jun. 14, 2005
`
`Sheet 2 of 5
`
`US 6,907,595 B2
`
`
`
`CONFIGURATION LOGIC 1 O1
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`Ex. 1006
`CISCO SYSTEMS, INC. / Page 3 of 13
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`

`

`U.S. Patent
`
`Jun. 14, 2005
`
`Sheet 3 of 5
`
`US 6,907,595 B2
`
`42O
`
`POWER-UP &
`STANDARD
`CONFIGURAON END
`
`402
`PROCESSOR 1 O3
`READS INTERNAL/
`EXTERNAL SIMULUS
`(E.G., PORT D)
`
`PROCESSOR O3
`NATES MG T PARTAL
`RECONFIGURATION
`
`
`
`PROCESSOR 1 O3
`WRITES OUTPUT
`RESULTS AND FLAGS
`(E.G., CONFIG DONE)
`
`
`
`FPGA ENTERS
`NORMALOPERATION
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`BTSTREAM HEADER WITH
`FRAME LOCATION
`I
`WRITE READ-BACK
`BSTREAM HEADER FROM
`MEMORY TO CAP
`
`READ-BACK MG
`CONFIGURATION FRAME
`FROM CAP TO MEMORY
`
`414 PROCESSOR 103 MOD FES
`MGTATTRIBUTE BITS IN
`MEMORY IN RESPONSE TO
`CONFIGURATION CONTROL
`STIMULUS (E.G., PORT ID)
`
`415
`
`WRITE WRITE BISTREAM
`HEADER FROMMEMORY TO
`ICAP
`
`WRITE MGT CONFIGURATION
`FRAMES FROMMEMORY TO
`CAP
`
`WRITE WRITE BITSTREAM
`TRALER COMMANDS FROM
`MEMORY TO CAP -/
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`
`Ex. 1006
`CISCO SYSTEMS, INC. / Page 4 of 13
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`

`

`U.S. Patent
`
`Jun. 14, 2005
`
`Sheet 4 of 5
`
`US 6,907,595 B2
`
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`Ex. 1006
`CISCO SYSTEMS, INC. / Page 5 of 13
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`

`

`U.S. Patent
`U.S. Patent
`
`Jun. 14, 2005
`
`Sheet 5 of 5
`
`US 6,907,595 B2
`US 6,907,595 B2
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`Ex. 1006
`CISCO SYSTEMS, INC./ Page 6 of 13
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`Ex. 1006
`CISCO SYSTEMS, INC. / Page 6 of 13
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`US 6,907,595 B2
`
`1
`PARTIAL RECONFIGURATION OFA
`PROGRAMMABLE LOGIC DEVICE USING
`AN ON-CHIP PROCESSOR
`
`2
`two separate external memories, especially if the configu
`ration data values Stored by these separate memories are
`practically identical (the only differences being in the con
`figuration data bits required to incrementally change the
`function of FPGA 100). In addition, there must be logic for
`selecting which of the two external memories will be used
`to configure or reconfigure FPGA 100. Moreover, the two
`Separate external memories only provide for one partial
`reconfiguration option, thereby limiting the flexibility of the
`partial reconfiguration process. This Scheme is also unde
`Sirably time consuming, because an entirely new full Set of
`configuration data values must be loaded into FPGA 100 in
`order to reconfigure a small portion of the FPGA.
`In another scheme, FPGA 100 is configured by loading a
`full Set of configuration data values into the configuration
`memory array from an external memory. These configura
`tion data values include one or more frames of reconfigu
`ration data, which is loaded into one or more of block RAMs
`121-125. For example, a first block RAM can be pro
`grammed to Store a first frame of reconfiguration data, and
`a Second block RAM can be programmed to Store a Second
`frame of reconfiguration data. The configuration data values
`also cause a plurality of configurable logic blocks to be
`configured to implement partial reconfiguration control
`logic. To implement partial reconfiguration, the partial
`reconfiguration control logic causes the desired frame or
`frames of reconfiguration data to be retrieved from the
`asSociated block RAM, and provided to internal configura
`tion access port 104. In response, internal configuration
`acceSS port 104 transmits each frame of reconfiguration data
`to configuration logic 101. In response, configuration logic
`101 loads each frame of reconfiguration data into the con
`figuration memory array, thereby overwriting previously
`loaded configuration data values. The interface between
`internal configuration access port 104 and configuration
`logic 101 is described in more detail in the Xilinx Libraries
`Guide available from Xilinx, Inc. at 2100 Logic Drive, San
`Jose, Calif. 95124.
`The above-described scheme undesirably consumes
`excessive resources on FPGA 100. For example, storing
`frames of reconfiguration data in the block RAM undesir
`ably consumes the block RAM resources of FPGA 100. In
`Some cases, it may not be possible to Store all of the desired
`frames of reconfiguration data in the available block RAM.
`Moreover, it is inefficient to store entire frames of recon
`figuration data in the block RAM, because it is likely that
`each frame of reconfiguration data is Substantially identical
`to the frame of configuration data being overwritten. That is,
`only a Small number of bits in each frame of reconfiguration
`data are different than the bits in each frame of configuration
`data values being overwritten.
`Accordingly, it would be desirable to have an improved
`Scheme for implementing the partial reconfiguration of
`FPGA 100, which overcomes the above-described deficien
`cies.
`
`SUMMARY
`Accordingly, the present invention provides a method of
`partially reconfiguring a programmable logic device that
`includes the steps of (1) loading a base set of configuration
`data values into a configuration memory array of the pro
`grammable logic device, thereby configuring the program
`mable logic device; (2) reading a first frame of configuration
`data values from the configuration memory array; (3) modi
`fying a Subset of the configuration data values in the first
`frame of configuration data values, thereby creating a first
`
`15
`
`FIELD OF THE INVENTION
`The present invention relates to partial reconfiguration of
`a programmable logic device, Such as a field programmable
`gate array (FPGA). More specifically, the present invention
`relates to the partial reconfiguration of a programmable logic
`device using an on-chip processor to perform a read-modify
`write flow to the configuration data.
`RELATED ART
`FIG. 1 is a block diagram of a conventional FPGA 100,
`which includes input/output (I/O) blocks (each labeled IO)
`located around the perimeter of the FPGA, multi-gigabit
`transceivers (MGT) 111-114 interspersed with the I/O
`blocks, configurable logic blocks (each labeled CLB)
`arranged in an array, block random access memory (BRAM)
`121-125 interspersed with the CLBs, configuration logic
`101, configuration interface 102, on-chip processor 103 and
`internal configuration access port (ICAP) 104. Although
`FIG. 1 shows a relatively small number of I/O blocks, CLBs
`and block RAMs for illustration purposes. It is understood
`25
`that an FPGA typically includes many more of these ele
`ments. On-chip processor 103 is an IBM PowerPC 405
`processor. FPGA 100 can include more than one of these
`processors (typically up to four of these processors). FPGA
`100 also includes other elements, Such as a programmable
`interconnect Structure and a configuration memory array,
`which are not illustrated in FIG. 1. FPGA 100 is described
`in more detail in “Virtex-IITM Pro, Platform FPGA
`Handbook”, (Oct. 14, 2002) which includes “Virtex-II ProTM
`Platform FPGA Documentation” (March 2002) “Advance
`Product Specification,” “Rocket I/O Transceiver User
`Guide”, “PPC 405 User Manual” and “PPC 405 Processor
`Block Manual” available from Xilinx, Inc., 2100 Logic
`Drive, San Jose, Calif. 95124.
`In general, FPGA 100 is configured in response to a set of
`configuration data values, which are loaded into a configu
`ration memory array of FPGA 100 (not shown), via con
`figuration interface 102 and configuration logic 101. Con
`figuration interface 102 can be, for example, a Select map
`interface, a JTAG interface, or a master Serial interface. The
`configuration data values are loaded into the configuration
`memory array one frame at a time. Typically, Several frames
`are required to configure a single column of the configura
`tion memory array. Each frame can include anywhere from
`about 2,000 to 20,000 configuration data values, depending
`on the size of FPGA 100.
`In certain cases, it is desirable to reconfigure Select
`portions of FPGA 100. That is, it is desirable to partially
`reconfigure FPGA 100. In the past, partial reconfiguration
`has been accomplished using the following methods.
`In one method, FPGA 100 is configured by loading a first
`full set of configuration data values from a first memory,
`such as a programmable read only memory (PROM). To
`reconfigure FPGA 100, a second full set of configuration
`data values are subsequently loaded into FPGA from a
`Second memory. The Second full Set of configuration data
`values is substantially identical to the first full set of con
`figuration data values, with the exception of the configura
`tion data values required to modify the behavior of the
`targeted portion of FPGA 100.
`The above-described Scheme has Several shortcomings.
`First, it is inefficient to Store the configuration data values in
`
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`3
`modified frame of configuration data values, and (4) over
`Writing the first frame of configuration data values in the
`configuration memory array with the first modified frame of
`configuration data values, thereby partially reconfiguring the
`programmable logic device. The Steps of reading, modifying
`and overwriting are performed under the control of a pro
`ceSSor located on the programmable logic device.
`In one embodiment, the modified Subset of configuration
`data values in the first modified frame are used to control the
`configuration of multi-gigabit transceivers of the program
`mable logic device. For example, the first modified frame of
`configuration data values can be used to adjust the pre
`emphasis and/or differential Voltage characteristics of the
`multi-gigabit transceivers.
`The subset of the configuration data values in the first
`frame can be modified in response to a control Signal
`generated external to the programmable logic device. For
`example, the control Signal may identify the location of the
`programmable logic device on a Serial back plane.
`Alternately, the control Signal may be provided by a user
`performing diagnostic tests on the multi-gigabit transceiv
`CS.
`In a particular embodiment, the processor can Store a
`plurality of different Subsets of configuration data values,
`wherein each of the Subsets represents a different partial
`reconfiguration of the programmable logic device.
`Advantageously, only the configuration data values being
`modified need to be stored.
`In accordance with another embodiment, a programmable
`logic device includes a configuration memory array having
`a plurality of frames for Storing configuration data values,
`and a processor configured to implement a partial recon
`figuration of the programmable logic device by reading a
`frame from the configuration memory array, modifying only
`a Select Subset of the frame, thereby creating a modified
`frame, and writing the modified frame back to the configu
`ration memory array. In one embodiment, the processor
`controls an internal configuration acceSS port coupled
`between the processor and the configuration memory array,
`wherein the internal configuration access port retrieves the
`frame from the configuration memory array under control of
`the processor. One or more block RAMs can be used as a
`data-Side on-chip memory, which Stores the frame and
`modified frame. CLB resources of the programmable logic
`device can be used to implement a direct memory acceSS
`(DMA) engine coupled between the data-Side on-chip
`memory and the internal configuration access port. CLB
`resources can also be used to implement a device control
`register coupled to the DMA engine and the processor,
`wherein the processor controls the DMA engine via the
`register.
`In yet another embodiment, the programmable logic
`device can be configured to implement a processor local bus
`coupled to the processor, and control logic coupled between
`the processor local bus and the internal configuration acceSS
`port. The block RAM can also be coupled to the processor
`local bus. A communications interface coupled to the pro
`ceSSor local bus can receive internal or external configura
`tion control Stimulus.
`The present invention will be more full understood in
`View of the following description and drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a conventional FPGA.
`FIG. 2 is a block diagram of an internal configuration
`access port control module in accordance with one embodi
`ment of the present invention.
`
`1O
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`US 6,907,595 B2
`
`4
`FIG. 3 is a block diagram of a device control register used
`in the internal configuration acceSS port control module of
`FIG. 2, in accordance with one embodiment of the present
`invention.
`FIG. 4 is a flow diagram that defines the operation of an
`internal configuration access port control module, in accor
`dance with one embodiment of the present invention.
`FIG. 5 is a block diagram of an FPGA, which is config
`ured to implement partial reconfiguration in accordance with
`another embodiment of the present invention.
`FIG. 6 is a block diagram illustrating an embodiment in
`which the FPGA of FIG. 2 or 5 is used to implement partial
`reconfiguration of another FPGA.
`DETAILED DESCRIPTION
`In accordance with the described embodiments of the
`present invention, a programmable logic device having an
`on-chip processor is configured to implement an efficient
`partial reconfiguration Scheme. In the described
`embodiments, a conventional Virtex-IITM Pro FPGA, avail
`able from Xilinx, Inc., is used to implement the partial
`reconfiguration Scheme. Thus, the present invention is
`described in connection with the use of FPGA 100 (FIG. 1).
`Although the present invention is described in connection
`with the partial reconfiguration of FPGAs, it is understood
`that the partial reconfiguration Scheme of the present inven
`tion may also be implemented using other programmable
`logic devices.
`The partial reconfiguration Scheme is described in con
`nection with the partial reconfiguration of the multi-gigabit
`transceivers (MGTs) 111-114 of FPGA 100. However, it is
`understood that other elements of FPGA 100 can be partially
`reconfigured in accordance with the principles described
`below.
`In the described embodiment, MGTS 111-114 are recon
`figured in order to optimize the operation of these transceiv
`ers. In general, MGTS 111-114 transmit differential signals
`to another chip at rates up to 3.125 Gigabits per Second
`(Gbps). The length of the traces used to transmit these
`differential Signals can vary, depending on the physical
`locations of the FPGA and the receiving chip. For example,
`FPGA 100 may be located on a printed circuit board that is
`plugged into a slot of a Serial back plane. In this case, the
`length of the traces between FPGA 100 and the receiving
`chip is determined by the particular slot into which the
`FPGA has been inserted.
`MGTS 111-114 can be configured to provide different
`levels of pre-emphasis to the transmitted differential Signals.
`In the present embodiment, two configuration memory cells
`in each MGT are used to select one of four levels of signal
`pre-emphasis. More Specifically, two “pre-emphasis' con
`figuration memory cells in each MGT can be set to have a
`value of “00” in order to provide 10 percent pre-emphasis to
`the differential transmit Signals. Similarly, these two pre
`emphasis configuration memory cells can be set to have
`values of “01”, “10” or “11” to provide 20 percent, 25
`percent or 33 percent pre-emphasis, respectively, to the
`differential transmit signals.
`MGTS 111-114 can also be configured to provide different
`differential output Voltages. In the present embodiment,
`three configuration memory cells in each MGT are used to
`select one of five differential output voltages. More
`Specifically, three "differential output voltage' configuration
`memory cells in each MGT can be set to have a value of
`“001” in order to provide an output signal having a differ
`ential voltage of 400 mV. Similarly, these three differential
`
`Ex. 1006
`CISCO SYSTEMS, INC. / Page 8 of 13
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`

`

`S
`output Voltage configuration memory cells can be set to have
`values of “010”, “011”, “100” or “101” to provide output
`signals having differential voltages of 500 mV, 600 mV, 700
`mV or 800 mV, respectively.
`In the described embodiments, the pre-emphasis and
`differential output Voltage configuration memory cells for
`each MGT are located in the same frame of the configuration
`memory array. Thus, the pre-emphasis and differential out
`put voltage configuration memory cells for MGTS 111, 112,
`113 and 114 are located in four corresponding frames
`Frame 1, Frame 2, Frame 3 and Frame 4 of the con
`figuration memory array.
`In general, the present invention operates as follows.
`FPGA 100 is initially configured in response to a base set of
`configuration data values, which are provided by an external
`15
`memory. In addition to configuring the rest of FPGA 100,
`this base Set of configuration data values configures MGTS
`111-114 in a predetermined base configuration. For
`example, in the base configuration, the pre-emphasis con
`figuration memory cells may be loaded with a value of “00”,
`and the differential output voltage configuration memory
`cells may be loaded with a value of “001'.
`A port identification signal (PORT ID), which is a static
`4-bit code provided on pins of FPGA 100, identifies the
`location of the FPGA in the serial back plane. Thus, the port
`identification signal is representative of the length of the
`transmission channel between the FPGA and a receiving
`chip. The port identification Signal is provided to processor
`103 on FPGA 100. Processor 103 is programmed to store
`different Sets of pre-emphasis and differential output voltage
`configuration data values, wherein each Set corresponds with
`a different port identification signal. Upon receiving the port
`identification signal, processor 103 accesses a corresponding
`Set of pre-emphasis and differential output Voltage configu
`ration data values. Processor 103 also causes a frame of
`configuration data values, which includes the pre-emphasis
`and differential output Voltage configuration data values for
`one of MGTS 111-114, to be read from the configuration
`memory array. Processor 103 then modifies the retrieved
`frame of configuration data values by overwriting the origi
`nal pre-emphasis and differential output Voltage configura
`tion data values with the Set of pre-emphasis and differential
`Voltage configuration data values associated with the port
`identification signal. Processor 103 then causes the modified
`frame of configuration data values to be written back to the
`configuration memory array, thereby modifying the proper
`ties of the associated MGT. The above-described read
`modify-write process is then repeated for the other MGTS on
`FPGA 100.
`Although the present embodiment describes the modifi
`cation of the MGTs in response to the port identification
`number, it is understood that the MGTS can also be tuned for
`other reasons, including characterization, changing System
`environments and diagnostics.
`The manner in which FPGA 100 is used to implement the
`read-modify-write process for partially reconfiguring the
`MGTS will now be described in more detail.
`FIG. 2 is a block diagram of an internal configuration
`access port (ICAP) control module 200 in accordance with
`one embodiment of the present invention. ICAP control
`module 200 enables MGTS 111-114 to be reconfigured using
`a read-modify-write scheme. Each of MGTS 111-114
`includes a corresponding Set of 5 configuration memory
`cells 211-214, which control the pre-emphasis and differ
`ential output voltage settings of the MGT.
`ICAP control module 200 is configured using various
`elements of FPGA 100 (FIG. 1). Thus, ICAP control module
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`200 includes processor 103 and internal configuration access
`port 104. Internal configuration access port 104, which is a
`hardwired module found in every Virtex-IITM and Virtex
`IITM Pro FPGA, has an interface similar to communications
`interface 102 (FIG. 1). Configuration logic 101 is coupled
`between ICAP 104 and the configuration memory cells
`211-214 of the configuration memory array. The ports of
`internal configuration access port 104 are accessible to the
`user logic of FPGA 100 via the general interconnect. ICAP
`control module 200 also includes a data side on-chip
`memory (DSOCM) 201, which is formed by a block RAM
`121, and an instruction side on-chip memory (ISOCM) 202,
`which is formed by two block RAMs 122-123. As described
`in more detail below, data-side OCM 201 is used to store
`program data, configuration frame data, and bit stream
`commands for read-back and write operations. Instruction
`side OCM 202 stores instruction code necessary to operate
`processor 103.
`ICAP control module 200 also includes a direct memory
`access (DMA) engine 203 and a device control register
`(DCR) 204. These elements 203-204 are formed by CLBs,
`which are configured in response to the base Set of configu
`ration data values. AS described in more detail below,
`commands are issued to DMA engine 203 through device
`control register 204. DMA engine 203 and device control
`register 204 use 2 percent or less of the programmable logic
`of FPGA 100.
`Because only three block RAMs are used to implement
`ICAP control module 200, this module does not consume
`excessive block RAM resources of FPGA 100. Moreover,
`the only CLB resources consumed by ICAP control module
`200 include those necessary to create DMA engine 203 and
`device control register 204. Thus, ICAP control module 200
`consumes minimal programmable logic resources on FPGA
`100.
`FIG. 3 is a block diagram of device control register 204.
`Device control register 204 is a 32-bit register that stores a
`4-bit port identification entry (PORT ID), a 1-bit write
`enable entry (WR), a 1-bit read-back enable entry (RB), a
`1-bit instruction done flag (DONE), a 1-bit reconfiguration
`done flag ((CONFIG DONE)), an 11-bit start address
`(START ADDR), an 11-bit end address (END ADDR),
`and two unused bits (not shown).
`FIG. 4 is a flow diagram that defines the operation of
`ICAP control module 200, in accordance with one embodi
`ment of the present invention. AS will become apparent in
`view of the following disclosure (FIG. 5), this flow diagram
`is equally applicable to other embodiments of present inven
`tion. Initially, FPGA 100 is powered-up, and standard con
`figuration is performed by loading a base Set of configura
`tion data values in a manner that is known in the art (Step
`401). An internal or external stimulus, such as the port
`identification value (PORT ID) provided on the pins of
`FPGA 100, is loaded into the PORT ID field of device
`control register 204. Processor 103 reads the PORT ID
`from device control register 204 (Step 402). In response to
`the PORT ID value read from device control register 204,
`processor 103 initiates the partial reconfiguration of MGTS
`111-114 (Step 403). This partial reconfiguration is accom
`plished as follows.
`First, processor 103 modifies a read-back bitstream
`header in data-side OCM 201 to identify an address of a
`frame (e.g., Frame 1) of the configuration memory array
`that includes the configuration data values for a Subset of the
`MGTs (e.g., MGT111) (Step 411). Then, processor 103 sets
`the write enable entry (WR) of device control register 204 to
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`a logic “1” value, clears the done flag (DONE) and the
`reconfiguration done flag (CONFIG DONE) in device con
`trol register 204, and Sets the Start and end addresses
`(START ADDR and END ADDR) in device control reg
`ister 204. The start address (START ADDR)) is set to
`identify the address in data-side OCM201 where the read
`back bitstream header begins, and the end address (END
`ADDR) is set to identify the address in data-side OCM 201
`where the read-back bitstream header ends. Upon detecting
`the logic “1” write enable entry (WR) in device control
`register 204, DMA engine 203 routes the read-back bit
`stream header stored in data-side OCM 201 to internal
`configuration access port 104 (Step 412). DMA engine 203
`then sets the DONE flag to a logic “1” state.
`Internal configuration access port 104 initiates a configu
`ration frame read-back operation in response to the received
`read-back bitstream header commands. As a result, a frame
`that includes the configuration data values 211 is retrieved
`from the configuration memory array, and provided to
`internal configuration access port 104.
`In response to the logic “1” DONE flag, processor 103
`resets the write enable entry (WR) to a logic low value, sets
`the read-back entry (RB) to a logic “1” value, resets the
`instruction done flag (DONE) to a logic “0” value, and sets
`the start and end addresses (START ADDR and END
`ADDR) in device control register 204. The start address and
`the end address (START ADDR and END ADDR) iden
`tify a block in data-side OCM201 where the retrieved frame
`is to be written. Upon detecting the logic “1” read-back entry
`(RB) in device control register 204, DMA engine 203 routes
`the retrieved frame from internal configuration access port
`104 to the location in data-side OCM 201 defined by
`START ADDR and END ADDR (Step 413). DMA
`engine 203 then sets the DONE flag to a logic “1” value.
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`Upon detecting the logic “1” DONE flag, processor 103
`modifies Select configuration bits (e.g., configuration bit set
`211) stored in data-side OCM 201, by overwriting these
`configuration bits with new configuration bits. These new
`configuration bits are Selected by processor 103 in response
`to the PORT ID value retrieved from device control reg
`ister 204 (Step 414). As described in more detail below,
`these new configuration bits can be Selected in response to
`other internal or external configuration control Stimulus in
`other embodiments. These new configuration bits define the
`new attributes of the associated MGT (e.g., MGT 111).
`Processor 103 then resets the DONE flag to a logic “0”
`value, resets the read-back entry (RB) to a logic “0” value,
`and sets the write enable entry (WR) to a logic “1” value in
`device control register 204. Processor 103 also sets the start
`and end addresses (START ADDR and END ADDR) in
`device control register 204. The start address (START
`ADDR) is set to identify the address in data-side OCM 201
`where the write bitstream header begins, and the end address
`(END ADDR) is set to identify the address in data-side
`OCM 201 where the write bitstream header ends. Upon
`detecting the logic “1” write enable entry (WR) in device
`control register 204, DMA engine 203 routes the write
`bitstream header stored in data-side OCM 201 to internal
`configuration access port 104, thereby initiating a write
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`access to the configuration memory array (Step 415). DMA
`engine 203 then sets the DONE flag to a logic “1” state.
`Upon detecting the logic “1” DONE flag, processor 103
`resets the DONE flag to a logic “0” state, sets the write
`enable signal (WR) to a logic “1” value, and sets the start
`and end addresses (START ADDR and END ADDR) in
`device control register 204. The start address (START
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`ADDR) is set to identify the address in data-side OCM 201
`where the modified frame begins, and the end address
`(END ADDR) is set to identify the address in data-side
`OCM 201 where the modified frame ends. Upon detecting
`the logic “1” write enable entry (WR) in device control
`register 204, DMA engine 203 routes the modified frame
`stored in data-side OCM201 to internal configuration access
`port 104. In response, internal configuration acceSS port 104
`writes the modified frame of configuration data values back
`to the configuration memory array, Such that this modified
`frame of configuration data values overwrites the previously
`retrieved frame of configuration data values (S