IPR2023-00975
`U.S. Pat. No. 6,874,014
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`APPLE INC.,
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`Petitioner
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`v.
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`SONRAI MEMORY LIMITED,
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`Patent Owner
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`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,874,014
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`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES ............................................................................ 1
`A.
`Real Party-in-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Counsel ................................................................................................. 2
`D.
`Service Information, Email, Hand Delivery, and Postal ...................... 2
`III. CERTIFICATION OF GROUNDS FOR STANDING ................................. 3
`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED ................... 3
`A.
`Prior Art Patents and Printed Publications ........................................... 3
`B.
`Grounds for Challenge ......................................................................... 4
`V. OVERVIEW OF THE ’014 PATENT AND THE PRIOR ART ................... 4
`A.
`Summary of the Alleged Invention ...................................................... 4
`B.
`Level of Ordinary Skill in the Art ........................................................ 7
`C.
`Prosecution History .............................................................................. 7
`D. Overview of Gulick .............................................................................. 8
`E.
`Overview of AAPA ............................................................................ 13
`VI. CLAIM CONSTRUCTION ......................................................................... 15
`A.
`"simultaneously executing two or more operating systems” ............. 16
`B.
`“multiple operating systems residing in a memory” .......................... 16
`C.
`“multiple processors are connected to said memory via a bus” ......... 16
`D.
`“processor means” in claim 12 ........................................................... 17
`E.
`“operating system means” in claim 12 ............................................... 18
`F.
`“memory means” in claim 12 ............................................................. 18
`VII. SPECIFIC GROUNDS FOR PETITION ..................................................... 19
`A. Ground 1: Claims 1, 3, 5, 7, 11-13, 15 are obvious over the
`combination of Gulick and AAPA ..................................................... 19
`1.
`Claim 1 ..................................................................................... 19
`2.
`Claim 3 ..................................................................................... 40
`3.
`Claim 5 ..................................................................................... 46
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`B.
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`Claim 7 ..................................................................................... 47
`4.
`Claim 11 ................................................................................... 49
`5.
`Claim 12 ................................................................................... 49
`6.
`Claim 13 ................................................................................... 58
`7.
`Claim 15 ................................................................................... 59
`8.
`Ground 2: Claims 1, 3, 5, 7, 11-13, 15 are obvious over the
`combination of AAPA and Gulick ..................................................... 59
`1.
`Claim 1 ..................................................................................... 60
`2.
`Claim 3 ..................................................................................... 74
`3.
`Claim 5 ..................................................................................... 75
`4.
`Claim 7 ..................................................................................... 77
`5.
`Claim 11 ................................................................................... 80
`6.
`Claim 12 ................................................................................... 80
`7.
`Claim 13 ................................................................................... 88
`8.
`Claim 15 ................................................................................... 88
`VIII. DISCRETIONARY DENIAL IS NOT APPROPRIATE ............................ 88
`A. General Plastic Denial is Inappropriate ............................................. 88
`B.
`Fintiv Discretionary Denial is Inappropriate ...................................... 89
`1.
`Fintiv Factor 1: Institution Will Enable a Stay ........................ 89
`2.
`Fintiv Factor 2: District Court Schedule .................................. 89
`3.
`Fintiv Factor 3: Parallel Proceeding Considerations ............... 90
`4.
`Fintiv Factor 4: The Petition Raises Unique Issues ................. 90
`5.
`Fintiv Factor 5: The Petition Will Enable Cancellation of
`Claims that Might Be Reasserted ............................................. 91
`Fintiv Factor 6: Other Considerations Support Institution ..... 91
`6.
`IX. CONCLUSION ............................................................................................. 92
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`I.
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`INTRODUCTION
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`Apple Inc. (“Apple” or “Petitioner”) petitions for inter partes review of U.S.
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`Patent No. 6,874,014 (“’014 patent”) (EX1001). The ’014 patent describes a chip
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`architecture having multiple processors on a single die that utilizes multiple
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`operating systems. As shown below, the system described in the ’014 patent was
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`known in the prior art.
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`II. MANDATORY NOTICES
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`A. Real Party-in-Interest
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`Pursuant to 37 C.F.R. § 42.8(b)(1), Petitioner certifies that Apple is the real
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`party-in-interest, and further certifies that no other party exercised control or could
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`exercise control over the filing of this petition or Apple’s participation in any
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`proceeding instituted on this petition.
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`B. Related Matters
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`According to assignment records at the United States Patent and Trademark
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`Office, the ’014 patent is currently owned by Sonrai Memory Limited (“Patent
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`Owner” or “PO”).
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`The ’014 patent is asserted in the matter Sonrai Memory Ltd. v. Apple Inc.,
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`6:22-cv-00787 (WDTX).
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`The ’014 patent was the subject of a previously filed inter partes review – IPR
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`2021-01454 (hereinafter “’1454 IPR”). In the ’1454 IPR, prior Petitioner requested
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`institution of inter partes review of the ’014 patent under the same grounds proposed
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`in the present Petition. On March 4, 2022, the Board issued their decision instituting
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`inter partes review of all of the challenged claims of the ’014 patent on all grounds
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`asserted in the former Petition. On October 12, 2022, the Board granted the joint
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`Motion to Terminate the ’1454 IPR proceeding following a settlement agreement
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`between the parties. Although the Board had instituted inter partes review of the
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`challenged claims, the Board did not decide the merits of the proceedings.
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`The present petition for inter partes review is also related to IPR2023-00819
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`that is substantially similar to the ’1454 IPR. The ’819 IPR was filed by Petitioner
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`and presents substantially the same grounds as the ’1454 IPR. The present petition
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`presents different grounds from the ’819 and ’1454 IPRs.
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`C. Counsel
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`Lead Counsel: Joseph Wolfe (Reg. No. 73,173)
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`Backup Counsel: James Heintz (Reg. No. 41,828)
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`D.
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`Service Information, Email, Hand Delivery, and Postal
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`Apple consents to electronic service at joseph.wolfe@us.dlapiper.com and
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`DLA-Apple-Sonrai-IPR@us.dlapiper.com
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`Petitioner can be reached at DLA Piper LLP (US), 1650 Market Street, Suite
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`5000, Philadelphia, PA 19103, Phone: 215-656-3359, Fax: 215-606-2059.
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`III. CERTIFICATION OF GROUNDS FOR STANDING
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`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which review
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`is sought is available for inter partes review, and that Petitioner is not barred or
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`estopped from requesting an inter partes review challenging the patent claims on the
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`grounds identified in this Petition.
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`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
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`Pursuant to Rules 42.22(a)(1) and 42.104(1)-(2), Petitioner challenges claims
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`1, 3, 5, 7, 11-13, and 15 of the ’014 patent.
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`A.
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`Prior Art Patents and Printed Publications
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`The ’014 patent issued from U.S. Patent Application No. 09/865,605 (“’605
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`application”), filed on May 29, 2001. Petitioner applies prior art with a priority date
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`earlier than the ’605 application’s filing date, May 29, 2001 (“Critical Date”).
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`The following references are pertinent to the grounds of unpatentability:1
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`1.
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`U.S. Patent No. 6,314,501 (“Gulick”), filed as Application No.
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`09/215,424 on December 18, 1998, and issued on November 6, 2001,
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`is prior art under at least 35 U.S.C. § 102(e).
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`2.
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`Applicant Admitted Prior Art (“AAPA”) in the ’014 Patent.
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`1 Because the ’014 patent issued from an application filed prior to enactment of the
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`America Invents Act (“AIA”), the pre-AIA statutory framework applies.
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`B. Grounds for Challenge
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`This Petition, supported by the declaration of Dr. Martin G. Walker (“Walker
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`Decl.”) (EX1002), requests cancellation of claims 1, 3, 5, 7, 11-13, and 15 as being
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`unpatentable under 35 U.S.C. § 103. See 35 U.S.C. § 314(a). The grounds for
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`challenge include the following:
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` Grounds References
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`Challenged Claims
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`1. §103
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`Gulick in view of Applicant
`Admitted Prior Art (AAPA)
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`1, 3, 5, 7, 11-13, 15
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`2. §103
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`AAPA in view of Gulick
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`1, 3, 5, 7, 11-13, 15
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`V. OVERVIEW OF THE ’014 PATENT AND THE PRIOR ART
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`A.
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`Summary of the Alleged Invention
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`The ’014 patent relates to “a multiprocessing chip utilizing multiple operating
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`systems.” EX1001, 1:6-10. The ’014 patent admits that multiprocessing systems
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`with multiple processors on a single die were well-known, and it depicts an example
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`of this known prior art single die multiprocessing system in Figure 2. EX1001, 1:34-
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`59; 1:41-42 (explaining that it was well-known in the art to use “multiple processors
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`on a single die” to conserve space in a system). EX1002, ¶38.
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`EX1001, FIG. 2 (annotated).
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`The prior art multiprocessing system (200) includes a chip multiprocessor 295
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`that “includes multiple processors 210-240 on a single die 290” (highlighted orange).
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`EX1001, 1:34-37. The processors 210-240 use an operating system 250 (highlighted
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`yellow) stored in memory 260 (highlighted blue). EX1001, 1:37-40. The processors
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`“may communicate with the memory 260 via a bus 270.” EX1001, 1:40-41. The
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`’014 patent states that “schemes that have placed multiple processors on a single
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`chip typically utilize a single operating system for tying all the processors together.”
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`EX1001, 1:44-47. The ’014 patent also acknowledges that it was known in the art
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`that multiprocessor systems could “support[] multiple processors executing multiple
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`operating systems.”EX1001, 1:60-63; EX1002, ¶39.
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`Unlike the AAPA system of FIG. 2 with multiple processors on a die and a
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`single operating system, the ’014 patent discloses a “multiprocessing system” where
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`“multiple processors are connected to a memory storing multiple operating
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`systems,” as illustrated in Figure 3 below. EX1001, 2:12-16 (emphasis added)2;
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`EX1002, ¶40.
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`EX1001, FIG. 3 (annotated), 2:54-55.
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`Like the prior-art system in FIG. 2, the computer system 300 in FIG. 3
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`includes a chip multiprocessor 350 having multiple processors 305-320 mounted on
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`a single die (highlighted orange). EX1001, 3:4-7. The purported advance of the
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`multiprocessing system is that it further includes multiple operating systems 325-
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`340 (highlighted yellow) stored in a memory 365 (highlighted blue), rather than a
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`single operating system 250 as shown in FIG. 2 above. EX1001, 3:10-11. The ’014
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`2 Unless otherwise noted, all emphases are added.
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`patent explains that “[d]uring operation, each processor 305-320 may access a
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`respective operating system 325-340 by communicating with the memory 365, for
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`example, via a bus 370.” EX1001, 3:11-14. The ’014 patent also explains that
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`“[e]ach processor may be … capable of simultaneously executing multiple operating
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`systems, for example, by context switching, which may include rapidly switching
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`between multiple operating systems.” EX1001, 3:47-51; EX1002, ¶41.
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`As explained below, all the limitations in the challenged claims were known
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`in the prior art and obvious. See infra Section VII; EX1002, ¶42; see also EX1002
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`¶¶18-.7 (technology background, citing Exhibits 1007-1017), ¶¶43-56 (discussing
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`the prior art at issue in this petition), ¶¶71-275 (discussing prior art disclosures in
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`view of each claim’s limitations).
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`B.
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`Level of Ordinary Skill in the Art
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`A person having ordinary skill in the art (“POSITA”) for the ’014 patent
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`would have had at least a bachelor’s degree in electrical engineering, computer
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`science, computer engineering, or an equivalent, and at least two years of experience
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`relating to the field of computer processor architecture. Additional education could
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`substitute for experience in the field, and vice versa. EX1002, ¶¶15-17
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`C.
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`Prosecution History
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`During prosecution, the Examiner issued a first Office Action mailed April
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`16, 2004. In the first Office Action, the pending claims were rejected under 35
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`U.S.C. § 102 as being anticipated by AAPA. EX1004, 121-126. In response,
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`Applicant argued over the rejection without amendments. EX1004, 110-119. The
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`Examiner issued a second Office Action mailed August 26, 2004. EX1004, 98-103.
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`In the second Office Action, the pending claims were rejected as obvious over
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`AAPA in view of US Patent No. 6,772,241 (“George”) (EX1011) and US Patent
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`No. 6,526,462 (“Elabd”) (EX1012). See id. In distinguishing prior art, Applicant
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`amended claim 1 to include the limitation “wherein . . . two or more of said
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`multiple processors are capable of simultaneously executing two or more operating
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`systems of said multiple operating systems.” EX1004, 87-97 (PO amended claims
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`7 and 13 in a similar fashion). PO argued that the prior art of record did not
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`disclose the “simultaneously executing” limitation. Id. Subsequently, the claims
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`were allowed. EX1004, 77-80.
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`D. Overview of Gulick
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`Gulick discloses a multi-processor computer system that includes “one or
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`more processor modules and a main memory having one or more memory storage
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`units . . . that allows a plurality of operating systems to concurrently execute in
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`different partitions within the computer system and allows the different partitions
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`to communicate with one another through shared memory.” EX1005, 8:47-53.
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`Gulick discloses a “multi-processor system that includes processor modules 110,
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`112, and 114” that “share access to main (or global) memory 160 . . . through a
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`system interconnection mechanism, such as system interconnection 130.”
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`EX1005, 10:53-67. Such arrangement allows processor modules 110-114 to
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`“communicate with each other through main memory 160.” EX1005, 10:64-67;
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`EX1002, ¶43.
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`Gulick discloses that the processor modules 110-114 “may be configured as
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`a separate partition within the computer system, such that multiple partitions may
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`exist within the computer system.” EX1005, 11:1-3. Each partition operates
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`“under the control of a separate operating system.” EX1005, 11:4-5. For example,
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`as shown below and disclosed in Gulick, “each processor module 110, 112, and
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`114 . . . can be defined as a separate partition controlled via a separate operating
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`system 170, 172, and 174.” EX1005, 11:5-10, FIG. 1; EX1002, ¶44.
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`EX1005, FIG. 1.
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`Gulick disclose that “[e]ach operating system 170, 172 and 174 views main
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`memory separately as though each is the only entity accessing main memory 160.”
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`EX1005, 11:8-10; EX1002, ¶45.
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`FIG. 2 illustrates components of an embodiment of the computing system
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`shown in FIG. 1 in more detail. Computer system 200 includes main memory 160
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`and a plurality of processing modules 240 connected to main memory via third
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`level cache modules 230 and crossbar interconnects 290. EX1005, 11:24-26;
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`EX1002, ¶46.
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`EX1005, FIG. 2.
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`Computer system 200 includes pairs of processors – processor
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`240A/processor 240B. Processor 240A and processor 240B “share a common bus
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`(e.g., 280A) with a single [third level cache application specific integrated circuits]
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`TCT (e.g., 270A) within a given [third level cache] TLC (e.g., 230A).” EX1005,
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`11:45-54. Gulick discloses that “each TLC 230 is connected to four processors”
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`and that “[e]ach TLC 230 and its respective four processors define a sub-Pod.”
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`EX1005, 11:57-60. Two sub-Pods “are connected via crossbar interconnect (e.g.,
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`crossbar interconnect 290A or 290B) to form a Pod.” EX1005, 11:60-62; EX1002,
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`¶47.
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`Computer system 200 includes “multiple partitions . . . each of which may
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`comprise one or more Pods or sub-pods, each operates under the control of a
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`separate operating system.” EX1005, 13:21-24. As shown in FIG. 5 (reproduced
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`below), the memory configuration of computer system 200 includes “three
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`operating systems” each of which “has its own address space 502.” EX1005,
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`13:30-36; EX1002, ¶48.
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`EX1005, FIG. 5.
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`FIG. 5 illustrates three memory windows (annotated red, green, blue,
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`respectively) that “are defined within the address space 504 of main memory 160”
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`and a shared memory (annotated yellow), “which is accessible by all three
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`operating systems.” EX1005, 13:37-43; FIG. 5. Gulick discloses that “the present
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`invention contemplates an environment wherein at least two of the operating
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`systems are different and one or more operating systems does not control or
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`manage the second operating system.” EX1005, 13:26-29. In this manner, Gulick
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`discloses a multi-processor computer system and method that allows for “multiple
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`operating systems, including different operating systems, to operate in different
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`partitions on the computer system.” EX1005, 2:37-56; EX1002, ¶49.
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`E. Overview of AAPA
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`The Memorandum entitled “Updated Guidance on the Treatment of
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`Statements of the Applicant in the Challenged Patent in Inter Partes Reviews
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`Under § 311” (hereinafter, “AAPA Memo”) (EX1006) published by Katherine
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`Vidal on June 9, 2022, establishes that it is appropriate for Petitioners to use
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`AAPA as either a primary reference or a secondary reference. EX1006, 5.
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`The ’014 patent admits that multiprocessing systems with multiple
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`processors on a single die were well-known, and it depicts a known prior art
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`system in FIG. 2 below. EX1001, 1:34-59; 1:41-42 (explaining that it was well-
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`known in the art to use “multiple processors on a single die” to conserve space in a
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`system); EX1002, ¶50.
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`EX1001, FIG. 2 (annotated).
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`Multiprocessing system 200 includes a chip multiprocessor 295 that
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`“includes multiple processors 210-240 on a single die 290” (highlighted orange).
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`EX1001, 1:34-37. Processors 210-240 use a single operating system 250
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`(highlighted yellow) stored in memory 260 (highlighted blue). EX1001, 1:37-40.
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`Processors “may communicate with the memory 260 via a bus 270.” EX1001,
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`1:40-41. The ’014 patent states that “schemes that have placed multiple processors
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`on a single chip typically utilize a single operating system for tying all the
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`processors together.” EX1001, 1:44-47. The ’014 patent also admits that it was
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`known in the art that multiprocessor systems could “support[] multiple processors
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`executing multiple operating systems”. EX1001, 1:60-63; EX1002, ¶51.
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`VI. CLAIM CONSTRUCTION
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`Claims subject to inter partes review are to be “construed using the same
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`claim construction standard that would be used to construe the claim in a civil action
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`under 35 U.S.C. 282(b), including construing the claim in accordance with the
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`ordinary and customary meaning of such claim as understood by one of ordinary
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`skill in the art and the prosecution history pertaining to the patent.” 37 C.F.R.
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`§ 42.100(b); Phillips v. AWH Corp., 415 F.3d 1303, 1312-16 (Fed. Circ. 2005). The
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`Board, however, only construes the claims when necessary to resolve the
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`controversy. Toyota Motor Corp. v. Cellport Sys., Inc., IPR2015-00633, Paper no.
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`11 at 16 (Aug. 14, 2015). Aside from the terms addressed below, Petitioner submits
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`that no express constructions of any of the terms are necessary and that the
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`challenged claims should be interpreted according to their plain and ordinary
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`meaning.3
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`3 Petitioner reserves all rights to raise claim construction and other arguments,
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`including challenges under 35 U.S.C. §§ 101 or 112, in district court as relevant to
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`those proceedings. See, e.g., Target Corp. v. Proxicom Wireless, LLC, IPR2020-
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`00904, Paper 11 at 11-13 (November 10, 2020). A comparison of the claims to
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`A.
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`"simultaneously executing two or more operating systems”
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`In the currently pending litigation, Petitioner and PO have agreed that
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`“simultaneously executing two or more operating systems” should be construed as
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`“simultaneously executing two or more independent operating systems.” The
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`Petition demonstrates that the challenged claims are obvious under this
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`construction or under the plain meaning of the claim language. EX1002, ¶¶58-59.
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`B.
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`“multiple operating systems residing in a memory”
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`In the currently pending litigation, Petitioner and PO have agreed that
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`“multiple operations systems residing in a memory” should be construed as
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`“multiple operating system residing in the same memory.” The Petition
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`demonstrates that the challenged claims are obvious under this construction or
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`under the plain meaning of the claim language. EX1002, ¶¶60-61.
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`C.
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`“multiple processors are connected to said memory via a bus”
`(claim 3)
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`In the currently pending litigation, Petitioner and PO have agreed that
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`“multiple processors are connected to said memory via a bus” should be construed
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`as “multiple processors are connected to said memory via the same bus.” The
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`any accused products in litigation may raise controversies that are not presented
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`here given the similarities between the references and the patent.
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`Petition demonstrates that the challenged claims are obvious under this
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`construction or under the plain meaning of the claim language. EX1002, ¶¶62-63.
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`D.
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`“processor means for executing a plurality of operating system
`means” (claim 12)
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`In the currently pending litigation, Petitioner and PO have an agreed upon 35
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`U.S.C. § 112 ¶6 construction for “processor means.” The agreed-upon function is
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`“executing a plurality of operating system means.” The agreed-upon structure is
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`“chip multiprocessor 350 having multiple processors 305-320 mounted on a single
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`die 360 as shown in Figure 3 and associated descriptions in the specification; or chip
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`multiprocessor 450 having multiple processors 405-420 mounted on a single die 460
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`shown in Figure 4 and associated descriptions in the specification; and equivalents
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`thereof.” The function and corresponding structure are substantially similar to those
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`proposed by petitioner in the ’1454 IPR. EX1002, ¶64.
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`Further, to the extent the Board does not adopt the agreed upon construction,
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`Petitioner submits
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`that an alternative function of “processor means”
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`is
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`“simultaneously execute two or more operating system means of said plurality of
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`operating system means.” The structure corresponding to this function is the same
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`as the agreed-upon construction. EX1002, ¶65.
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`Additionally, to the extent that “processor means” is not a means plus function
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`limitation, “processor means” should be construed according to its plain meaning.
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`EX1002, ¶66.
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`E.
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`“operating system means” (claim 12)
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`The “operating system means” phrase does not recite “means for” language.
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`Instead, the “operator system means” only recites “means” and does not recite a
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`function corresponding to the means. EX1001, 4:66, Claim 12. Accordingly,
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`“operating system means” does not invoke 35 U.S.C. § 112 ¶6 and should be given
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`its plain and ordinary meaning. See Rodime PLC v. Seagate Tech., Inc., 174 F.3d
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`1294, 1302 (Fed. Cir. 1999). Further, this term is not subject to any claim
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`construction dispute in the current litigation. EX1002, ¶68.
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`F.
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`“memory means for storing said plurality of operating system
`means” (claim 12)
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`The “memory means” phrase recites “means for” language, which invokes 35
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`U.S.C. § 112 ¶6. EX1001, 5:1, Claim 12. The identified function of the “memory
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`means” is “storing said plurality of operating system means.” EX1001, 5:1-2, Claim
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`12. The ’014 patent identifies as corresponding structure “SRAM and/or DRAM on
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`the same chip as one or more processors; SRAM and/or DRAM on separate chips
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`connected to one or more processors; magnetic media, such as tape or disk; optical
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`media, such as CD-ROM; and the like.” EX1001, 3:15-20. EX1002, ¶69.
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`18
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`VII. SPECIFIC GROUNDS FOR PETITION
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`Pursuant to Rule 42.104(b)(4)-(5), the following sections, detail the grounds
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`of unpatentability, the limitations of the challenged claims of the ’014 patent, and
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`how these claims are obvious in view of the prior art.
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`A. Ground 1: Claims 1, 3, 5, 7, 11-13, 15 are obvious over the
`combination of Gulick and AAPA
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`Gulick is highly relevant to claims 1, 3, 5, 7, 11-13, and 15 of the ’014
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`patent. EX1002, ¶71.
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`1.
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`Claim 1
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`a.
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`A multiprocessing system comprising
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`To the extent the preambles are limiting, the Gulick-AAPA combination
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`(hereinafter “Gulick-AAPA”) discloses the limitations therein. EX1002, ¶72.
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`Gulick discloses “a multi-processor system that includes processor modules
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`110, 112, and 114.” EX1005, 10:53-54; EX1002, ¶73.
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`EX1005, FIG. 1.
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`Gulick discloses a more detailed description of an embodiment of the multi-
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`processor system of FIG. 1. For example, as shown below, Gulick discloses “a
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`computing system 200 . . . [that] includes a main memory . . . and a plurality of
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`processing modules 240 connected to the main memory.” EX1005, 11:22-26, FIG.
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`2; EX1002, ¶74.
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`20
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`EX1005, FIG. 2.
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`Gulick states that “the processing modules and the main memory [as shown
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`in FIG. 2] are arranged in a symmetrical multiprocessing architecture. EX1005,
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`11:28-32; EX1002, ¶75.
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`AAPA Fig. 2 likewise shows a conventional chip multiprocessor 295 in a
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`computer system 200. EX1001, 1:34-59; 1:41-42; EX1002, ¶76.
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`
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`Therefore, Gulick-AAPA discloses and/or suggests this limitation. EX1002,
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`¶77.
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`21
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`b. multiple processors mounted on a single die
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`Gulick-AAPA discloses this limitation. EX1002, ¶78.
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`Gulick discloses a computer system that includes processor modules 110-
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`114 (highlighted green) labeled as “processor(s)” in Fig. 1. EX1005, 10:53-54.
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`Each processor module 110-114 “can . . . include a plurality of processors.”
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`EX1005, 10:59-60; EX1002, ¶79.
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`
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`EX1005, FIG. 1 (annotated).
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`
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`Gulick discloses computer system 200 that includes a plurality of processing
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`modules 240 comprising processors 240A/240B-240R/240S (highlighted green).
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`EX1005, 11:24-26; EX1002, ¶80.
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`22
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`EX1005, FIG. 2 (annotated).
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`Computer system 200 includes “multiple partitions . . . each of which may
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`comprise one or more Pods or sub-pods, each operates under the control of a
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`23
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`separate operating system.” EX1005, 13:21-24. Gulick discloses that a pod is
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`formed from multiple sub-pods. EX1005, 11:60-62 (Two sub-Pods “are connected
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`via crossbar interconnect (e.g., crossbar interconnect 290A or 290B) to form a
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`Pod”). Gulick’s pods and sub-pods are “both examples of processing modules.”
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`EX1005, 10:35-42. One or more processing modules form a partition operating
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`under the control of its own operating system. EX1005, 9:41-46, 10:27-34;
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`EX1002, ¶81.
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`
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`Gulick also teaches that “the present invention contemplates other
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`multiprocessing environments and configurations.” EX1005, 13:12-14. This
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`further demonstrates to a POSITA that Gulick contemplates implementing a
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`plurality of operating systems on a variety of conventional multiprocessors,
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`including those disclosed in the AAPA. EX1002, ¶82.
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`To the extent that Gulick does not explicitly provide that the multiple
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`processors are mounted on a single die, AAPA teaches doing so. EX1002, ¶83.
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`The ’014 patent discloses that it is well known for a computer system to
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`have multiple processors mounted on a single die. For example, the ’014 patent
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`discloses a “conventional multiprocessing scheme . . . [that] includes a computer
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`system having a chip multiprocessor 295.” EX1001, 1:34-36; EX1002, ¶84.
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`24
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`EX1001, FIG. 2 (annotated).
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`The ’014 patent provides that conventional multiprocessing schemes include
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`a chip multiprocessor 295 that “includes multiple processors 210-240 on a single
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`die 290” (highlighted orange). EX1001, 1:34-37; EX1002, ¶85.
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`As set forth in the AAPA Memo, patentee’s admissions regarding the scope
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`and content of the prior art can be used to supply missing claim limitations that
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`were generally known in the art prior to the invention. EX1006, 4. Accordingly,
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`Petitioner’s use of AAPA to supply a missing claim limitation (i.e., use of a single
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`die) is entirely proper.
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`A POSITA would have found it obvious in light of AAPA to configure the
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`system in Gulick so that its multiple processors are “mounted on a single die,” as
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`claimed, and would have had a reasonable expectation of success in so doing.
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`Such an implementation would have been a straightforward combination of well-
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`known technologies using known methods and would have had predictable results.
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`See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416-18 (2007). EX1002 ¶86.
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`A POSITA would have recognized that Gulick and AAPA disclose features
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`in a similar technological field. For example, both Gulick and AAPA relate to
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`multi-processor computing systems. EX1005, 10:53-54 (“FIG. 1 illustrates a multi-
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`processor system that includes processor modules 110, 112, and 114”); EX1005,
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`11:28-32 (“the processing modules and the main memory [as shown in FIG. 2] are
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`arranged in a symmetrical multiprocessing architecture”); EX1001, 1:34-36 (“A
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`second conventional multiprocessing scheme (shown in FIG. 2) includes a
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`computer system 200 having a chip multiprocessor 295.”). EX1002, ¶87.
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`Further, a POSITA would have been motivated to configure the system in
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`Gulick so that its multiple processors are “mounted on a single die” to obtain
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`benefits associated with using multiple processors on a single integrated circuit die
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`that are applicable to any multiprocessing architecture, including Gulick’s, that the
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`AAPA admits were known to a POSITA. For example, utilizing a single die is
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`beneficial because it allows system 200 to conserve space by providing multiple
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`processors on a single die. EX1001, 1:41-42. Additionally, in the AAPA
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`“mounting multiple processors on a single die reduces the cabling problem
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`inherent in connecting multiple processors on separate dies in separate houses,”
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`26
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`“reduces the latency for communication among the processors”, “improves the
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`efficiency of message passing”, “reduces chip-to-chip communication costs”,
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`“leads to further power efficiency”, and increases “scalability for multiprocessing.”
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`EX1001, 2:26-38; EX1002, ¶88.
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`Therefore, consistent with the AAPA Memo, the patentee’s admissions both
`
`support a motivation to combine particular disclosures and demonstrates the
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`knowledge of the ordinarily-skilled artisan at the time of the invention. EX1006,
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`4. Thus, Petitioner’s reliance on AAPA is proper. EX1002, ¶89.
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`Moreover, the following discussion includes examples that show that,
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`consistent with AAPA, the benefits of having multiple processors on a single di