Author:
`
`Issue To:
`
`
`ORIGINATE DATE
`
`7 May, 2001
` Laurent Lefebvre
`
`
`
`EDIT DATE
`
`4 September, 2015
`
`DOCUMENT-REV. NUM.
`
`GEN-CXXXXX-REVA
`
`PAGE
`
`1 of 9
`
`Copy No:
`
`
`R400 Sequencer Specification
`
`SEQ
`
`Version 0.1
`
`
`Overview: This is an architectural specification for the R400 Sequencer block (SEQ). It provides an overview of the
`required capabilities and expected uses of the block. It also describes the block interfaces, internal sub-
`blocks, and provides internal state diagrams.
`
`
`
`
`
`
`
`AUTOMATICALLY UPDATED FIELDS:
`Document Location:
`D:\Perforce\r400\arch\doc\gfx\MC\R400 MemCtl.doc
`Current Intranet Search Title:
`R400 Memory Controller Architectural Specification
`APPROVALS
`
`Name/Dept
`
`
`
`
`
`
`
`Remarks:
`
`
`Signature/Date
`
`
`
`
`
`
`
`THIS DOCUMENT CONTAINS CONFIDENTIAL INFORMATION THAT COULD BE
`SUBSTANTIALLY DETRIMENTAL TO THE INTEREST OF ATI TECHNOLOGIES
`INC. THROUGH UNAUTHORIZED USE OR DISCLOSURE.
`
`
`
`“Copyright 2001, ATI Technologies Inc. All rights reserved. The material in this document constitutes an unpublished
`work created in 2001. The use of this copyright notice is intended to provide notice that ATI owns a copyright in this
`unpublished work. The copyright notice is not an admission that publication has occurred. This work contains
`confidential, proprietary information and trade secrets of ATI. No part of this document may be used, reproduced, or
`transmitted in any form or by any means without the prior written permission of ATI Technologies Inc.”
`
`
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`ATI 2007
`LG v. ATI
`IPR2015-00326
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 1 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`EDIT DATE
`
`4 September, 2015
`
`
`
`
`R400 Memory Controller
`Architectural Specification
`
`PAGE
`
`2 of 9
`
`
`
`Table Of Contents
`
`1. OVERVIEW ......................................... 3
`1.1 Top Level Block Diagram .................... 4
`TEXTURE ARBITRATION .................. 7
`2.
`ALU ARBITRATION ........................... 8
`3.
`INPUT INTERFACE ............................ 8
`4.
`4.1 Rasterizer to Register File (interpolated
`data) 8
`4.2 Texture Unit to Register File (texture
`return) .......................................................... 8
`
`
`Revision Changes:
`
`Rev 0.1 (Laurent Lefebvre)
`Date: May 7, 2001
`
`
`
`4.3 ALU Unit to Register File (ALU op
`result) ........................................................... 8
`4.4 Scalar Unit to Register File (Scalar op
`result) ........................................................... 8
`5. OUTPUT INTERFACE ........................ 8
`5.1 Sequencer to Shader Engine Bus ....... 8
`5.2 Shader Engine to Texture Unit Bus ..... 9
`6. OPEN ISSUES .................................... 9
`
`
`
`
`
`First draft.
`
`
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 2 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`EDIT DATE
`
`4 September, 2015
`
`DOCUMENT-REV. NUM.
`
`GEN-CXXXXX-REVA
`
`PAGE
`
`3 of 9
`
`
`
`
`1. Overview
`The sequencer first arbitrates between vectors of 16 vertices that arrive directly from primitive assembly and vectors
`of 8 quads (32 pixels) that are generated in the raster engine.
`
`The vertex or pixel program specifies how many GPR’s it needs to execute. The sequencer will not start the next
`vector until the needed space is available.
`
`The sequencer is based on the R300 design. It chooses an ALU clause and a texture clause to execute, and execute
`all of the instructions in a clause before looking for a new clause of the same type. Each vector will have eight texture
`and eight alu clauses, but clauses do not need to contain instructions. A vector of pixels or vertices ping-pongs along
`the sequencer FIFO, bouncing from texture reservation station to alu reservation station. A FIFO exists between each
`reservation stage, holding up vectors until the vector currently occupying a reservation station has left. A vector at a
`reservation station can be chosen to execute. The sequencer looks at all eight alu reservation stations to choose an
`alu clause to execute and all eight texture stations to choose a texture clause to execute. The arbitrator will give
`priority to clauses/reservation stations closer to the top of the pipeline. It will not execute an alu clause until the
`texture fetches initiated by the previous texture clause have completed.
`
`To support the shader pipe the raster engine also contains the shader instruction cache and constant store.
`
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 3 of 1898
`
`

`

`EDIT DATE
`ORIGINATE DATE
`
`
`4 September, 2015
`7 May, 2001
`
`1.1 Top Level Block Diagram
`
`
`R400 Memory Controller
`Architectural Specification
`
`PAGE
`
`4 of 9
`
`texture arbitrator
`
`vertex/pixel vector arbitrator
`
`Possible delay for available GPR’s
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`FIFO
`
`Texture clause 0
`reservation station
`
`Texture clause 1
`reservation station
`
`Texture clause 2
`reservation station
`
`Texture clause 3
`reservation station
`
`Texture clause 4
`reservation station
`
`Texture clause 5
`reservation station
`
`Texture clause 6
`reservation station
`
`Texture clause 7
`reservation station
`
`ALU clause 0
`reservation station
`
`ALU clause 1
`reservation station
`
`ALU clause 2
`reservation station
`
`ALU clause 3
`reservation station
`
`ALU clause 4
`reservation station
`
`ALU clause 5
`reservation station
`
`ALU clause 6
`reservation station
`
`ALU clause 7
`reservation station
`
`texture arbitrator
`
`
`
`
`The rasterizer always checks the vertices FIFO first and if allowed by the sequencer sends the data to the shader. If
`the vertex FIFO is empty then, the rasterizer takes the first entry of the pixel FIFO (a vector of 32 pixels) and sends it
`to the interpolators. Then the sequencer takes control of the packet.
`
`On receipt of a packet, the input state machine (not pictured but just before the first FIFO) allocated enough space in
`the registers to store the interpolatoted values and temporaries. Following this, the input state machine stacks the
`packet in the first FIFO.
`
`On receipt of a command, the level 0 texture machine issues a texure request and corresponding register address for
`the texture address (ta). A small command (tcmd) is passed to the texture system identifying the current level number
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 4 of 1898
`
`

`

`PAGE
`DOCUMENT-REV. NUM.
`EDIT DATE
`ORIGINATE DATE
`
`
`
`
`5 of 9
`GEN-CXXXXX-REVA
`4 September, 2015
`7 May, 2001
`
`(0) as well as the register set being used. One texture request is sent every 4 clocks causing the texturing of four
`2x2s worth of data.
`
`Uppon recept of the return data (identified by the tcmd containing the level number 0), the level 0 texture machine
`issues a register address for the return value (td). Then, it puts the finished packet in FIFO 1.
`
`On receipt of a command, the level 0 ALU machine issues a complete set of level 0 shader instructions. For each
`instruction, the state machine generates 3 source addresses, one destination address (2 cycles later) and an
`instruction id wich is used to index into the instruction store. Once the last instruction as been issued, the packet is
`put into FIFO 2. Note that in the case of a pixel packet, the two vectors of 16 pixels are interleaved in order to hide the
`latency of the ALUs (8 cycles).
`
`All other level process in the same way until the packet finally reaches the last ALU machine (8). On completion of the
`level 8 ALU clause, a valid bit is sent to the Render Backend wich picks up the color data. This requires that the last
`instruction writes to the output register – a condition that is almost always true. If the packet was a vertex packet,
`instead of sending the valid bit to the RB, it is sent to the PA, which picks up the data a puts it into the vertex store.
`
`Only one ALU state machine may have access to the SRAM address bus or the instruction decode bus at one time.
`Similarly, only one texture state machine may have access to the SRAM address bus at one time. Arbitration is
`performed by two arbitrer blocks (one for the ALU state machines and one for the texture state machines). The
`arbitrers always favor the higher number state machines, preventing a bunch of half finished jobs from clogging up
`the SRAMS.
`
`Each state machine maintains an address pointer specifying where the 16 (or 32) entries vector is located in the
`SRAM (the texture machine has two pointers one for the read address and one for the write). Upon completion of its
`job, the address pointer is incremented by a predefined amount equal to the total number of registers required by the
`shading code. A comparison of the address pointer for the first state machine in the chain (the input state machine),
`and the last machine in the chain (the level 8 ALU machine), gives an indication of how much unallocated SRAM
`memory is available. When this number falls below a preset watermark, the input state machine will stall the rasterizer
`preventing new data from entering the chain.
`
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 5 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`data returned from texture fetch
`
`interpolated data from RE
`
`EDIT DATE
`
`4 September, 2015
`
`
`R400 Memory Controller
`Architectural Specification
`
`PAGE
`
`6 of 9
`
`Register File
`512x128 (built as 4 128x128 or 16 128x32
`
`control from RE
`
`Address to texure
`or vertex parameter data to RE through texture block
`or pixel data to RB through texture block
`
`4x32
`128 bit data
`
`constants from RE
`
`Operand mux
`
`4 32 bit MAC units
`
`128 bit scalar/vector
`ALU
`
`control from RE
`
`
`
`
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 6 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`EDIT DATE
`
`4 September, 2015
`
`DOCUMENT-REV. NUM.
`
`GEN-CXXXXX-REVA
`
`PAGE
`
`7 of 9
`
`
`
`pipeline stage
`
`Register File
`
`instruction
`
`MAC
`
`data from RE
`texture fetch return
`
`address to texture
`
`constants from RE
`
`Register File
`
`data from RE
`texture fetch return
`
`MAC
`
`address to texture
`
`constants from RE
`
`Register File
`
`MAC
`
`Register File
`
`MAC
`
`data from RE
`texture fetch return
`
`address to texture
`
`constants from RE
`
`data from RE
`texture fetch return
`
`address to texture
`
`constants from RE
`
`instruction
`
`instruction
`
`instruction
`
`instruction
`
`instruction
`
`pipeline stage
`
`instruction
`
`pipeline stage
`
`pipeline stage
`
`scalar operand input/ scalar result output
`
`Scalar Unit
`
`2. Texture Arbitration
`The texture arbitration logic chooses one of the 8 potentially pending texture clauses to be executed. The choice is
`made by looking at the fifos from 8 to 0 and picking the first one ready to execute. Once chosen, the clause state
`machine will send one 2x2 texture fetch per 4 clocks until all the texture fetch instructions of the clause are sent. This
`means that there cannot be any dependencies between two texture fetches of the same clause.
`
`
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 7 of 1898
`
`

`

`EDIT DATE
`
`4 September, 2015
`
`
`R400 Memory Controller
`Architectural Specification
`
`PAGE
`
`8 of 9
`
`ORIGINATE DATE
`
`7 May, 2001
`
`3. ALU Arbitration
`ALU arbitration proceeds in almost the same way than texture arbitration. The ALU arbitration logic chooses one of
`the 8 potentially pending ALU clauses to be executed. The choice is made by looking at the fifos from 8 to 0 and
`picking the first one ready to execute. If the packet chosen is a packet of vertices, the state machine issues one
`instruction every 4 clocks until the clause is finished. This means that the compiler has to insert nops between two
`dependent successive instructions. If the packet is a pixel packet it is made out of two sub-vectors of 16. Thus the
`state machine issues the first instruction for the first sub-vector and then, 4 clocks later, the first instruction of the
`second sub-vector and so on until the clause is finished. Proceeding this way hides the latency of 8 clocks of the
`ALUs.
`4. Input Interface
`4.1 Rasterizer to Register File (interpolated data)
`Name
`Direction
`bits
`Description
`SND
`SEQSP
`1
`High when sending data
`Interpolated data
`SEQSP
`512
`512 bits transferred every 4 cycles
`
`4.2 Texture Unit to Register File (texture return)
`Name
`Direction
`bits
`Description
`SND
`SEQTU
`1
`High when sending data
`Texture colors
`TUSP
`512
`512 bits transferred every 4 cycles
`
`4.3 ALU Unit to Register File (ALU op result)
`Name
`Direction
`bits
`Description
`SND
`SEQSP
`1
`High when sending data
`Blend result ALU
`SPSP
`512
`512 bits transferred every 4 cycles
`Write Mask
`SPSP
`16
`The four write masks
`
`4.4 Scalar Unit to Register File (Scalar op result)
`Name
`Direction
`bits
`Description
`SND
`SEQSP
`1
`High when sending data
`Scalar result
`SPSP
`512
`512 bits transferred every 4 cycles
`Write Mask
`SPSP
`16
`The four write masks
`
`5. Output Interface
`5.1 Sequencer to Shader Engine Bus
`This is a bus that sends the instruction and constant data to all 4 Sub-Engines of the Shader. Because a new
`instruction is needed only every 4 clocks, the width of the bus is divided by 4 and both constants and instruction
`are sent over those 4 clocks.
`
`Name
`Instruction Start
`Constant 0
`Constant 1
`Instruction
`
`Bits Description
`1
`High on first cycle of transfer
`32
`128 bits transferred over 4 cycles, alpha first…blue last
`32
`128 bits transferred over 4 cycles, alpha first…blue last
`40
`160 bits transferred over 4 cycles
`
`Direction
`SEQ-> SP
`SEQ-> SP
`SEQ-> SP
`SEQ-> SP
`
`
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 8 of 1898
`
`

`

`512
`8
`
`4 Texture Addresses read from the Register File
`Index into Register file for write of returned Texture
`Data
`
`EDIT DATE
`ORIGINATE DATE
`
`
`4 September, 2015
`7 May, 2001
`
`5.2 Shader Engine to Texture Unit Bus
`One quad’s worth of addresses is transferred to Texture Unit every clock. These are sourced fro a different pixel
`within each of the sub-engines repeating every 4 clocks. The register file index to read must precede the data by
`2 clocks. The Read address associated with Quad 0 must be sent 1 clock after the Instruction Start signal is sent,
`so that data is read 3 clocks after the Instruction Start.
`
`One Quad’s worth of Texture Data may be written to the Register File every clock. These are directed to a
`different pixel of the sub-engines repeating every 4 clocks. The register file index to write must accompany the
`data. Data and Index associated with the Quad 0 must be sent 3 clocks after the Instruction Start signal is sent.
`
`
`
`Name
`Tex_Read_Register_Inde
`x
`SP->TEX
`Tex_RegFile_Read_Data
`Tex_Write_Register_Index SEQ->SP
`
`Bits Description
`8
`Index into Register Files for reading Texture Address
`
`DOCUMENT-REV. NUM.
`
`GEN-CXXXXX-REVA
`
`PAGE
`
`9 of 9
`
`Direction
`SEQ->SP
`
`
`6. Open issues
`There is currently an issue with constants. If the constants are not the same for the whole vector of vertices, we don’t
`have the bandwith from the texture store to feed the ALUs. Two solutions exists for this problem:
`1) Let the compiler handle the case and put those instructions in a texture clause so we can use the
`bandwith there to operate. This requires a significant amount of temporary storeage in the register store.
`2) Waterfall down the pipe allowing only at a given time the vertices having the same constants to operate in
`parralel. This might in the worst case slow us down by a factor of 16.
`
`
`
`Exhibit 2007.doc (cid:31)(cid:31) 9252 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  ***09/04/15 04:03 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 9 of 1898
`
`

`

`Author:
`
`Issue To:
`
`
`ORIGINATE DATE
`
`7 May, 2001
` Laurent Lefebvre
`
`
`
`EDIT DATE
`
`8 September, 20153
`September 201513
`
`DOCUMENT-REV. NUM.
`
`GEN-CXXXXX-REVA
`
`PAGE
`
`1 of 16
`
`
`
`Copy No:
`
`
`R400 Sequencer Specification
`
`SEQ
`
`Version 0.32
`
`
`Overview: This is an architectural specification for the R400 Sequencer block (SEQ). It provides an overview of the
`required capabilities and expected uses of the block. It also describes the block interfaces, internal sub-
`blocks, and provides internal state diagrams.
`
`
`
`
`
`
`
`AUTOMATICALLY UPDATED FIELDS:
`Document Location:
`C:\perforce\r400\arch\doc\gfx\RE\R400_Sequencer.doc
`Current Intranet Search Title:
`R400 Sequencer Specification
`APPROVALS
`
`Name/Dept
`
`
`
`
`
`
`
`Remarks:
`
`
`Signature/Date
`
`
`
`
`
`
`
`THIS DOCUMENT CONTAINS CONFIDENTIAL INFORMATION THAT COULD BE
`SUBSTANTIALLY DETRIMENTAL TO THE INTEREST OF ATI TECHNOLOGIES
`INC. THROUGH UNAUTHORIZED USE OR DISCLOSURE.
`
`
`
`“Copyright 2001, ATI Technologies Inc. All rights reserved. The material in this document constitutes an unpublished
`work created in 2001. The use of this copyright notice is intended to provide notice that ATI owns a copyright in this
`unpublished work. The copyright notice is not an admission that publication has occurred. This work contains
`confidential, proprietary information and trade secrets of ATI. No part of this document may be used, reproduced, or
`transmitted in any form or by any means without the prior written permission of ATI Technologies Inc.”
`
`
`
`Exhibit 2009.docR400_Sequencer.doc (cid:31)(cid:31) 16178 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  *** 09/08/15 01:03
`
`PM08/13/01 03:17 PM07/13/01 02:10 PM
`
`ATI 2009
`LG v. ATI
`IPR2015-00326
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 10 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`
`
`EDIT DATE
`
`8 September, 20153
`September 201513
`
`R400 Sequencer Specification
`
`
`
`PAGE
`
`2 of 16
`
`
`
`Table Of Contents
`
`1. OVERVIEW ......................................... 3
`1.1 Top Level Block Diagram .................... 4
`1.2 Data Flow graph ................................ 87
`1.3 Control Graph ................................ 1110
`INTERPOLATED DATA BUS ....... 1110
`2.
`INSTRUCTION STORE ................ 1110
`3.
`CONSTANT STORE ..................... 1211
`4.
`LOOPING AND BRANCHES ........ 1211
`5.
`REGISTER FILE ALLOCATION ... 1211
`6.
`TEXTURE ARBITRATION ............ 1312
`7.
`ALU ARBITRATION ..................... 1312
`8.
`HANDLING STALLS .................... 1413
`9.
`10. CONTENT OF THE RESERVATION
`STATION FIFOS .................................... 1413
`11. THE OUTPUT FILE (RB FIFO AND
`PARAMETER CACHE) .......................... 1413
`INTERFACES ......................... 1413
`12.
`12.1 External Interfaces ............. 1413
`12.1.1 Sequencer to Shader
`Engine Bus ........................................ 1413
`12.1.2 Shader Engine to Output
`File
`1413
`12.1.3 Shader Engine to Texture
`Unit Bus (Fast Bus) ......................... 1514
`12.1.4
`Sequencer to Texture Unit bus
`(Slow Bus) 1514
`
`
`
`Revision Changes:
`
`Rev 0.1 (Laurent Lefebvre)
`Date: May 7, 2001
`
`Rev 0.2 (Laurent Lefebvre)
`Date : July 9, 2001
`Rev 0.3 (Laurent Lefebvre)
`Date : August 6, 2001
`
`12.1.5
`Shader Engine to RE/PA Bus
`1514
`
`12.1.6
`PA to sequencer ................ 1514
`13. OPEN ISSUES .............................. 1614
`1. OVERVIEW ......................................... 3
`1.1 Top Level Block Diagram .................... 4
`TEXTURE ARBITRATION .................. 9
`2.
`ALU ARBITRATION ........................... 9
`3.
`HANDLING STALLS ........................ 10
`4.
`CONTENT OF THE RESERVATION
`5.
`STATION FIFOS ........................................ 10
`INTERFACES ............................. 10
`6.
`6.1 External Interfaces .................... 10
`6.1.1 Sequencer to Shader Engine
`Bus
`10
`6.1.2 Shader Engine to Output File
`
`10
`6.1.3 Shader Engine to Texture Unit
`Bus (Fast Bus) ...................................... 10
`6.1.4 Sequencer to Texture Unit bus
`(Slow Bus) ............................................... 11
`6.1.5 Shader Engine to RE/PA Bus ... 11
`7. OPEN ISSUES .................................. 11
`
`
`
`
`
`
`
`First draft.
`
`Changed the interfaces to reflect the changes in the
`SP. Added some details in the arbitration section.
`Reviewed the Sequencer spec after the meeting on
`August 3, 2001.
`
`Exhibit 2009.docR400_Sequencer.doc (cid:31)(cid:31) 16178 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  *** 09/08/15 01:03
`PM08/13/01 03:17 PM07/13/01 02:10 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 11 of 1898
`
`

`

`EDIT DATE
`
`8 September, 20153
`September 201513
`
`DOCUMENT-REV. NUM.
`
`GEN-CXXXXX-REVA
`
`PAGE
`
`3 of 16
`
`ORIGINATE DATE
`
`7 May, 2001
`
`
`
`
`1. Overview
`The sequencer first arbitrates between vectors of 16 (maybe 32) vertices that arrive directly from primitive assembly
`and vectors of 84 quads (16 pixels) (32 pixels) that are generated in the raster engine.
`
`The vertex or pixel program specifies how many GPR’s it needs to execute. The sequencer will not start the next
`vector until the needed space is available.
`
`The sequencer is based on the R300 design. It chooses an two ALU clauses and a texture clause to execute, and
`executes all of the instructions in aa clause before looking for a new clause of the same type. Two ALU clauses are
`executed interleaved to hide the ALU latency. Each vector will have eight texture and eight ALU clauses, but clauses
`do not need to contain instructions. A vector of pixels or vertices ping-pongs along the sequencer FIFO, bouncing
`from texture reservation station to alu reservation station. A FIFO exists between each reservation stage, holding up
`vectors until the vector currently occupying a reservation station has left. A vector at a reservation station can be
`chosen to execute. The sequencer looks at all eight alu reservation stations to choose an alu clause to execute and
`all eight texture stations to choose a texture clause to execute. The arbitrator will give priority to clauses/reservation
`stations closer to the top bottom of the pipeline. It will not execute an alu clause until the texture fetches initiated by
`the previous texture clause have completed. There are two separate sets of reservation stations, one for pixel vectors
`and one for vertices vectors. This way a pixel can pass a vertex and a vertex can pass a pixel.
`
`To support the shader pipe the raster engine also contains the shader instruction cache and constant store. There
`are only one constant store for the whole chip and one instruction store. These will be shared among the four shader
`pipes.
`
`
`Exhibit 2009.docR400_Sequencer.doc (cid:31)(cid:31) 16178 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  *** 09/08/15 01:03
`
`PM08/13/01 03:17 PM07/13/01 02:10 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 12 of 1898
`
`

`

`ORIGINATE DATE
`EDIT DATE
`
`
`8 September, 20153
`7 May, 2001
`
`September 201513
`1.1 Top Level Block Diagram
`
`R400 Sequencer Specification
`
`
`
`PAGE
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`4 of 16
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`texture arbitrator
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`vertex/pixel vector arbitrator
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`Possible delay for available GPR’s
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`FIFO
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`Texture clause 0
`reservation station
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`Texture clause 1
`reservation station
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`Texture clause 2
`reservation station
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`Texture clause 3
`reservation station
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`Texture clause 4
`reservation station
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`Texture clause 5
`reservation station
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`Texture clause 6
`reservation station
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`Texture clause 7
`reservation station
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`ALU clause 0
`reservation station
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`ALU clause 1
`reservation station
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`ALU clause 2
`reservation station
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`ALU clause 3
`reservation station
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`ALU clause 4
`reservation station
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`ALU clause 5
`reservation station
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`ALU clause 6
`reservation station
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`ALU clause 7
`reservation station
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`texture arbitrator
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`There are two sets of the above figure, one for vertices and one for pixels.
`
`The rasterizer always checks the vertices FIFO first and if allowed by the sequencer sends the data to the shader. If
`the vertex FIFO is empty then, the rasterizer takes the first entry of the pixel FIFO (a vector of 32 16 pixels) and
`sends it to the interpolators. Then the sequencer takes control of the packet. The packet consists of 3 bits of state, 6-
`7 bits for the base address of the Shader program and some information on the coverage to determine texture LOD.
`All other information (2x2 adresses) is put in a FIFO (one for the pixels and one for the vertices) and retrieved when
`the packet finishes its last clause.
`
`
`
`
`Exhibit 2009.docR400_Sequencer.doc (cid:31)(cid:31) 16178 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  *** 09/08/15 01:03
`PM08/13/01 03:17 PM07/13/01 02:10 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 13 of 1898
`
`

`

`DOCUMENT-REV. NUM.
`ORIGINATE DATE
`PAGE
`EDIT DATE
`
`
`
`
`5 of 16
`GEN-CXXXXX-REVA
`8 September, 20153
`7 May, 2001
`
`September 201513
`On receipt of a packet, the input state machine (not pictured but just before the first FIFO) allocated enough space in
`the registers to store the interpolated values and temporaries. Following this, the input state machine stacks the
`packet in the first FIFO.
`
`On receipt of a command, the level 0 texture machine issues a texure request and corresponding register address for
`the texture address (ta). A small command (tcmd) is passed to the texture system identifying the current level number
`(0) as well as the register set being usedwrite address for the texture return data. One texture request is sent every 4
`clocks causing the texturing of four 2x2s worth of data (or 16 vertices). Once all the requests are sent the packet is
`put in FIFO 1.
`
`Upon recept of the return data (identified by the tcmd containing the level number 0), the level 0 texture machine
`issues a register address for the return value (td). Then, it increments the counter of FIFO one 1 to signify to the ALU
`1 that the data is ready to be processed.
`
`On receipt of a command, the level 0 ALU machine first decrements the input FIFO counter and then issues a
`complete set of level 0 shader instructions. For each instruction, the state machine generates 3 source addresses,
`one destination address (2 3 cycles later) and an instruction id wich is used to index into the instruction store. Once
`the last instruction as been issued, the packet is put into FIFO 2. Note that in the case of a pixel packet, the two
`vectors of 16 pixels are consecutive in order to hide the latency of the ALUs (8 cycles).
`
`There will always be two active ALU clauses at any given time (and two arbitrers) In this case, the instructions of a
`vector are interleaved with the instructions of the other vector. One arbitrer will arbitrate over the odd clock cycles and
`the other one will arbitrate over the even clock cycles. The only constraints between the two arbitrers is that they are
`not allowed to pick the same clause number as they other one is currently working on if the packet os of the same
`type.
`
`If the packet is a vertex packet, upon reaching ALU clause 4, it can export the position if the position is ready. So the
`arbitrer must prevent ALU clause 4 to be selected if the positional buffer is full (or can’t be accessed). Along with the
`positional data, the location where the vertex data is to be put is also sent (parameter data pointers).
`
`All other level process in the same way until the packet finally reaches the last ALU machine (8). On completion of the
`level 8 ALU clause, a valid bit is sent to the Render Backend which picks up the color data. This requires that the last
`instruction writes to the output register – a condition that is almost always true. If the packet was a vertex packet,
`instead of sending the valid bit to the RB, it is sent to the PA, which picks up the data and puts it into the vertex store
`so it can know that the data present in the parameter store is valid.
`
`Only one two ALU state machine may have access to the SRAMregister file address bus or the instruction decode
`bus at one time. Similarly, only one texture state machine may have access to the SRAMregister file address bus at
`one time. Arbitration is performed by two three arbitrer blocks (one two for the ALU state machines and one for the
`texture state machines). The arbitrers always favor the higher number state machines, preventing a bunch of half
`finished jobs from clogging up the SRAMregister Sfiles.
`
`Each state machine maintains an address pointer specifying where the 16 (or 32) entries vector is located in the
`SRAMregister file (the texture machine has two pointers one for the read address and one for the write). Upon
`completion of its job, the address pointer is incremented by a predefined amount equal to the total number of
`registers required by the shading code. A comparison of the address pointer for the first state machine in the chain
`(the input state machine), and the last machine in the chain (the level 8 ALU machine), gives an indication of how
`much unallocated SRAMregister file memory is available
`
`Exhibit 2009.docR400_Sequencer.doc (cid:31)(cid:31) 16178 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  *** 09/08/15 01:03
`
`PM08/13/01 03:17 PM07/13/01 02:10 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 14 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`data returned from texture fetch
`
`EDIT DATE
`
`8 September, 20153
`September 201513
`interpolated data from RE
`
`R400 Sequencer Specification
`
`
`
`PAGE
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`6 of 16
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`Register File
`512x128 (built as 4 128x128 or 16 128x32
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`control from RE
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`Address to texure
`or vertex parameter data to RE through texture block
`or pixel data to RB through texture block
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`4x32
`128 bit data
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`constants from RE
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`Operand mux
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`4 32 bit MAC units
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`128 bit scalar/vector
`ALU
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`control from RE
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`
`
`Exhibit 2009.docR400_Sequencer.doc (cid:31)(cid:31) 16178 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  *** 09/08/15 01:03
`PM08/13/01 03:17 PM07/13/01 02:10 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 15 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`EDIT DATE
`
`8 September, 20153
`September 201513
`
`DOCUMENT-REV. NUM.
`
`GEN-CXXXXX-REVA
`
`PAGE
`
`7 of 16
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`Register File
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`constants from RE
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`instruction
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`scalar input/output
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`MAC
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`pipeline stage
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`texture request
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` texture data/primitive data from RE into the register files
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`texture request
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`texture request
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`texture request
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`Mux
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`texture address
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`Mux
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`primitive data
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`from RE
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`texture data
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`Register File
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`MAC
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`Register File
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`MAC
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`Register File
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`MAC
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`instruction
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`scalar input/output
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`pipeline stage
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`scalar input/output
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`scalar input/output
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`Scalar Unit
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`instruction
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`pipeline stage
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`constants from RE
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`instruction
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`to Primitive Assembly Unit or RenderBackend
`
`
`Exhibit 2009.docR400_Sequencer.doc (cid:31)(cid:31) 16178 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  *** 09/08/15 01:03
`
`PM08/13/01 03:17 PM07/13/01 02:10 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 16 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`1.2 Data Flow graph
`
`EDIT DATE
`
`8 September, 20153
`September 201513
`
`R400 Sequencer Specification
`
`
`
`PAGE
`
`8 of 16
`
`Exhibit 2009.docR400_Sequencer.doc (cid:31)(cid:31) 16178 Bytes***  ATI Confidential. Reference Copyright Notice on Cover Page  *** 09/08/15 01:03
`PM08/13/01 03:17 PM07/13/01 02:10 PM
`
`PROTECTIVE ORDER MATERIAL
`
`ATI Ex. 2119
`IPR2023-00922
`Page 17 of 1898
`
`

`

`ORIGINATE DATE
`
`7 May, 2001
`
`EDIT DATE
`
`8 September, 20153
`September 201513
`
`DOCUMENT-REV. NUM.
`
`GEN-CXXXXX-REVA
`
`PAGE
`
`9 of 16
`
`Register File
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`constants from R