LINITED STATES PATENT AND TRADEMARK OFFICE
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE TFIE PATENT TRIAL AND APPEAL BOARD
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`LG ELECTRONICS, [NTC.,
`LG ELECTRONICS, INC.,
`Petitioner,
`Petitioner,
`
`v.
`V
`
`ATI TECHNOLOGIES ULC,
`ATI TECHNOLOGIES ULC,
`Patent Owner.
`Patent Owner.
`
`Case IPR2015-00326
`Case IPR2015-00326
`Patent 6,897,871
`Patent 6,897,871
`
`DECLARATION OF' II¡'VENTOR LAURENT LEFEBVRE
`DECLARATION OF INVENTOR LAURENT LEFEBVRE
`REGARDTNG THE INVENTTON DATE OF U.S. PATENT NO. 6,897,871.
`REGARDING THE INVENTION DATE OF U.S. PATENT NO. 6,897,871
`
`Maíl Stop "Patent Board"
`Mail Stop "Patent Board"
`Patent Trial and Appeal Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`U.S. Patent and Trademark Office
`P.O. Box 1450
`P.O. Box 1450
`Alexandria, VA 223 13 -1450
`Alexandria, VA 22313-1450
`
`$ (cid:9)
`
`EXHIBIT
`
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`
`ATI2006
`ATI 2006
`LG v. ATI
`LG v. ATI
`IPR2015-00326
`rPR2015-00326
`
`LG Ex. 1037
`LG v. ATI
`IPR2015­00330
`
`LG Ex. 1037, pg 1
`
`ATI Ex. 2118
`
`IPR2023-00922
`Page 1 of 66
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`

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`
`
`Table of Contents
`Table of Contents
`
`I.
`BACKGROUND
`I. BACKGROUND (cid:9)
`II. CONCEPTION
`II. CONCEPTION (cid:9)
`A.
`A. R400 Architecture Proposal (cid:9)
`R400 Architecture Proposal
`
`B.
`B.
`
`R400 Top Level Specification (cid:9)
`R400 Top Level Specification.
`R400 Shader Processor
`C. R400 Shader Processor (cid:9)
`C.
`D. R400 Sequencer Specification (cid:9)
`D.
`R400 Sequencer Specification
`
`1
`1
`
`aJ
`3
`
`4
`
`5
`5
`
`7
`..........7
`
`7
`7
`
`2.
`2
`
`R400 Sequencer Specification (Version 0.4): August
`1. R400 Sequencer Specification (Version 0.4): August
`I
`24,200r....,;...........
`24, 2001 (cid:9)
`R400 Sequencer Specification (Version 2.0): April 19,
`R400 Sequencer Specification (Version 2.0): April 19,
`2002
`2002 (cid:9)
`18
`...........18
`ru. DILIGENCE
`III. DILIGENCE (cid:9)
`I Periodically Updated the R400 Sequencer Specification .................21
`A.
`21
`I Periodically Updated the R400 Sequencer Specification (cid:9)
`A.
`
`8
`.......8
`
`21
`2T
`
`My Colleagues and I Continuously Developed and
`B. My Colleagues and I Continuously Developed and
`B.
`Debugged Emulation Code and RTL Code for the R400
`Debugged Emulation Code and RTL Code for the R400 (cid:9)
`IV. TESTING SHOWED THAT TI{E RTL IMPLEMENTATION
`IV. (cid:9)
`TESTING SHOWED THAT THE RTL IMPLEMENTATION
`WORKED FOR ITS INTENDED PURPOSE..
`WORKED FOR ITS INTENDED PURPOSE (cid:9)
`V. DILIGENCE CALENDAR
`V. (cid:9)
`DILIGENCE CALENDAR (cid:9)
`VI. EXHIBITS
`VI. EXHIBITS (cid:9)
`
`22
`22
`
`28
`28
`
`aa
`33
`JJ
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`61
`6T
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`LG Ex. 1037, pg 2
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`ATI Ex. 2118
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`IPR2023-00922
`Page 2 of 66
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`I, Laurent Lefebvre, declare as follows:
`I, Laurent Lefebvre, declare as follows:
`
`I. BACKGROT]ND
`I. BACKGROUND
`1.
`I am a computer-graphics hardware architect at AMD Inc. I have been
`I am a computer-graphics hardware architect at AMD Inc. I have been
`1.
`
`designing computer-graphics processors for the past fifteen years. I specialize in
`designing computer-graphics processors for the past fifteen years. I specialize in
`
`sequencers, shaders, 3 D-computer graphics, and integrated-circuit design
`sequencers, shaders, 3D-computer graphics, and integrated-circuit design.
`
`2. From September 2000 to November 2006,I worked as an engineer
`From September 2000 to November 2006, I worked as an engineer
`2.
`
`and hardware architect for ATI Technologies Inc. ("ATI"). It is my understanding
`and hardware architect for ATI Technologies Inc. ("ATI"). It is my understanding
`
`that ATI hired me to develop technologies for the R400, which is a graphics
`that ATI hired me to develop technologies for the R400, which is a graphics
`
`processor. Information relating to ATI's development of the R400 is confidential
`processor. Information relating to ATI's development of the R400 is confidential
`
`and proprietary.If this information became public, it would put ATI/AMD at a
`and proprietary. If this information became public, it would put ATI/AMD at a
`
`competitive disadvantage because it would give ATI/AMD's competitors access to
`competitive disadvantage because it would give ATI/AMD's competitors access to
`
`proprietary algorithms, implementation details, and development schedules for the
`proprietary algorithms, implementation details, and development schedules for the
`
`R400 design.
`R400 design.
`
`3.
`Ilnlike conventional graphics processors at the time, the R400 used a
`3. Unlike conventional graphics processors at the time, the R400 used a
`
`unified shader for both pixel commands and vertex commands-two types of
`unified shader for both pixel commands and vertex commands—two types of
`
`commands required to produce an image. Conventional graphics processors had
`commands required to produce an image. Conventional graphics processors had
`
`separate shaders for pixel commands and vertex commands. But a unified shader,
`separate shaders for pixel commands and vertex commands. But a unified shader,
`
`like the R400's unified shader, enhances functionality and efficiency by allowing
`like the R400's unified shader, enhances functionality and efficiency by allowing
`
`the same shader complex to be used for both pixel commands and vertex
`the same shader complex to be used for both pixel commands and vertex
`
`I
`1
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`LG Ex. 1037, pg 3
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`commands. The R400's unified-shader architecture was later included in a chip
`
`called the Xenos chip. The Xenos chip was in the Microsoft® Xbox 360®.
`called the Xenos chip. The Xenos chip was in the Microsoft@ Xbox 360@
`
`4. The R400 includes many different functional blocks (e.g., the
`The R400 includes many different functional blocks (e.g., the
`4. (cid:9)
`
`sequencer, shader pipe, primitive assembly, texture cache, texture Pipe, raster
`sequencer, shader pipe, primitive assembly, texture cache, texture pipe, raster
`
`engine, display, etc.). See, e.g.,Ðx.2053, p. 6. The PowerPoint slide titled Block
`engine, display, etc.). See, e.g., Ex. 2053, p. 6. The PowerPoint slide titled Block
`
`Responsibility (reproduced below) shows tne ÁTI office responsible for designing
`Responsibility (reproduced below) shows the ATI office responsible for designing
`
`each block.
`each block.
`
`Block Responsibility
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`5. For the R400 project, I was responsible for the sequencer block,
`5.
`For the R400 project, I was responsible for the sequencer block,
`
`which is the block thatmanages the execution of pixel commands and vertex
`which is the block that manages the execution of pixel commands and vertex
`
`commands for the unified shader. In particular, I drafted the high-level
`commands for the unified shader. In particular, I drafted the high-level
`
`specification that describes the sequencer block's functionality, and I wrote
`specification that describes the sequencer block's functionality, and I wrote
`
`emulator code for the sequencer block. In addition, I was also co-responsible for
`emulator code for the sequencer block. In addition, I was also co-responsible for
`
`emulating the shader pipe block and the export block.
`emulating the shader pipe block and the export block.
`
`6.
`6.
`
`I am one of the named inventors of U.S. Patent No. 6,897,871 ("the
`I am one of the named inventors of U.S. Patent No. 6,897,871 ("the
`
`'871 patent"). The other named inventors are Steve Morein, Andy Gruber, and
`'871 patent"). The other named inventors are Steve Morein, Andy Gruber, and
`
`Andi Skende. W.e collectively conceived of the graphics-processing system
`Andi Skende. We collectively conceived of the graphics-processing system
`
`claimed in the '87I patent no later than early 2002, while working on the R400
`claimed in the '871 patent no later than early 2002, while working on the R400.
`
`See infra Part II. A team of my colleagues and I, which totaled about one hundred
`See infra Part II. A team of my colleagues and I, which totaled about one hundred
`
`engineers, worked on the R400 nearly every business day from no later than early
`engineers, worked on the R400 nearly every business day from no later than early
`
`2002 to November 20,2003. See infra Parts III, V. No later than the third quarter
`2002 to November 20, 2003. See infra Parts III, V. No later than the third quarter
`
`of 2002, we made a GPU in register-transfer-language ("RTL") code that worked
`of 2002, we made a GPU in register-transfer-language ("RTL") code that worked
`
`to process a first triangle. See infra Part IV.
`to process a first triangle. See infra Part IV.
`
`II. CONCEPTION
`II. CONCEPTION
`7 . No later than early 2002, Steve Morein, Andy Gruber, Andi Skende,
`7. No later than early 2002, Steve Morein, Andy Gruber, Andi Skende,
`
`and I collectively conceived of the graphics-processing system in the '87I patent.
`and I collectively conceived of the graphics-processing system in the '871 patent.
`
`We each contributed different aspects to this system. Steve Morein came up with
`We each contributed different aspects to this system. Steve Morein came up with
`
`the idea for a unified shader. This is shown, for example, in documents titled
`the idea for a unified shader. This is shown, for example, in documents titled
`
`-3-
`- 3 -
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`"R400 Architecture Propos al" and "R400 Top Level Specification." Ex. 2040, p. l;
`"R400 Architecture Proposal" and "R400 Top Level Specification." Ex. 2040, p. 1;
`
`8x.2041, p. 1. Andy Gruber was the lead architect for the shader pipe. Andy
`Ex. 2041, p. 1. Andy Gruber was the lead architect for the shader pipe. Andy
`
`Gruber worked with Andi Skende to come up with ideas for implementing the
`Gruber worked with Andi Skende to come up with ideas for implementing the
`
`shader pipe and author the shader processor specification. This is shown, for
`shader pipe and author the shader processor specification. This is shown, for
`
`example, in a document titled "Shader Processor." Ex. 2042, p. 1. And I was the
`example, in a document titled "Shader Processor." Ex. 2042, p. 1. And I was the
`
`lead for the sequencer block. This is shown, for example, in a document titled
`lead for the sequencer block. This is shown, for example, in a document titled
`
`"R400 Sequencer Specification." 8.g., 8x.2007, p. l. I explain each of these
`"R400 Sequencer Specification." E.g., Ex. 2007, p. 1. I explain each of these
`
`documents in turn below
`documents in turn below.
`
`A. R400 Architecture Proposal
`A. R400 Architecture Proposal
`8. Steve Morein authored the "R400 Architecture Proposal." Ex. 2040,
`8. (cid:9)
`Steve Morein authored the "R400 Architecture Proposal." Ex. 2040,
`
`p. 1. In this proposal, the R400 includes a unified shader that performs both pixel
`p. 1. In this proposal, the R400 includes a unified shader that performs both pixel
`
`operations and vertex operations. See id. at 9. The R400 also includes a unified
`operations and vertex operations. See id. at 9. The R400 also includes a unified
`
`processing pipe (i.e., a single programmable pipeline for 2D video, 3D vertex, and
`processing pipe (i.e., a single programmable pipeline for 2D video,3D vertex, and
`
`3D pixel operations). ,See id. at 6 ("The most ambitious feature in this design is the
`3D pixel operations). See id. at 6 ("The most ambitious feature in this design is the
`
`'truly unified pipe': a single programmable pipeline."). V/ith a single pipeline for
``truly unified pipe': a single programmable pipeline."). With a single pipeline for
`
`both pixel commands and vertex commands, the graphics processor had higher
`both pixel commands and vertex commands, the graphics processor had higher
`
`color precision and the ability to support more registers, compared with a
`color precision and the ability to support more registers, compared with a
`
`conventional graphics pipeline. See id.
`conventional graphics pipeline. See id.
`
`-4-
`4
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`B. R400 Top Level Specifïcation
`B. R400 Top Level Specification
`9. Steve Morein also authored the "R400 Top Level Specification,"
`9.
`Steve Morein also authored the "R400 Top Level Specification,"
`
`which sets forth the high-level architecture for the R400. Ex. 2047, p. 1. As shown
`which sets forth the high-level architecture for the R400. Ex. 2041, p. 1. As shown
`
`in this document, the R400 Top Level Specification includes a sequencer. See e.g.,
`in this document, the R400 Top Level Specification includes a sequencer. See e.9.,
`
`id. at27-28,30. The sequencer manages the instructions for the unified shader. ,See
`id. at 27-28, 30. The sequencer manages the instructions for the unified shader. See
`
`id. at 11 ("Before starting the processing . . . the rasterizer (which includes the
`id. at 11 ("Before starting the processing . . . the rasterizer (which includes the
`
`sequencer for the shader pipeline) checks to make sure that there are enough free
`sequencer for the shader pipeline) checks to make sure that there are enough free
`
`registers in the shader pipeline for the pixel shader program."),27 ("The raster
`registers in the shader pipeline for the pixel shader program."), 27 ("The raster
`
`engine . . . contains the sequencer for the shader pipe.")
`engine . . . contains the sequencer for the shader pipe.").
`
`10. The R400 Top Level Specification includes a block diagram of the
`10. The R400 Top Level Specification includes a block diagram of the
`
`sequencer's control flow (reproduced below for reference)
`sequencer's control flow (reproduced below for reference).
`
`5
`5
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`LG Ex. 1037, pg 7
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`Id. at30.
`Id. at 30.
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`-6-
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`LG Ex. 1037, pg 8
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`(cid:9)
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`11. This block diagram includes three arbitratorst: (1) a "vertex/pixel
`11. (cid:9)
`This block diagram includes three arbitrators': (1) a "vertex/pixel
`
`vector arbitrator" atthe top of the diagram; (2) a"texture arbitrator" on the left side
`vector arbitrator" at the top of the diagram; (2) a "texture arbitrator" on the left side
`
`of the diagram; and (3) a "texture arbitrator" on the right side of the diagram. See
`of the diagram; and (3) a "texture arbitrator" on the right side of the diagram. See
`
`id. The "texture arbitrator" on the left side is mislabeled. This arbitrator should be
`id. The "texture arbitrator" on the left side is mislabeled. This arbitrator should be
`
`labeled "ALIJ arbitrator" to correspond to the ALU reservation stations. I describe
`labeled "ALU arbitrator" to correspond to the ALU reservation stations. I describe
`
`the control flow for this block diagram in Part II.D.1 of this declaration.
`the control flow for this block diagram in Part II.D.1 of this declaration.
`
`C. R400 Shader Processor
`C. R400 Shader Processor
`12. Andy Gruber and Andi Skende authored the "Shader Processor,"
`12. (cid:9) Andy Gruber and Andi Skende authored the "Shader Processor,"
`
`which describes the shader architecture, interfaces, partitioning, and timing of the
`which describes the shader architecture, interfaces, partitioning, and timing of the
`
`shader. 8x.2042, p. 1. The shader processor had four identical Shader pipelines in
`shader. Ex. 2042, p. 1. The shader processor had four identical Shader pipelines in
`
`the R400 architecture, each pipe capable of operating on ALU instructions for
`the R400 architecture, each pipe capable of operating on ALU instructions for
`
`vertex parameters and pixel values. See id. at 5
`vertex parameters and pixel values. See id. at 5
`
`D. R400 Sequencer Specification
`D. R400 Sequencer Specification
`13. I authored the "R400 Sequencer Specificatioî," which is the
`I authored the "R400 Sequencer Specification," which is the
`13. (cid:9)
`
`architectural specification for the R400 sequencer block. Ex. 2007, p. 1. There are
`architectural specification for the R400 sequencer block. Ex. 2007, p. 1. There are
`
`1 The term"arbitratot" is interchangeable with the term "arbiter." See, e.g.,
`'The term "arbitrator" is interchangeable with the term "arbiter." See, e.g.,
`
`Ex.2023, pp. 9-10 (identi$'ing the control flow diagram as: "Figure 2: Reservation
`Ex. 2023, pp. 9-10 (identifying the control flow diagram as: "Figure 2: Reservation
`
`stations and arbiters").
`stations and arbiters")
`
`-7 -
`7
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`LG Ex. 1037, pg 9
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`(cid:9)
`(cid:9)
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`at least thirty three revisions of this specification. SeeEx.2039, pp. 4-5;8xs.2007-
`at least thirty three revisions of this specification. See Ex. 2039, pp. 4-5; Exs. 2007-
`
`38. Each revision updates the specification.
`38. Each revision updates the specification.
`
`14. I developed two versions of the sequencer's control flow. SeeEx.
`14. 1 developed two versions of the sequencer's control flow. See Ex.
`2010;8x.2028. 'When I filed the patent application that led to the '871 pafent,I
`2010; Ex. 2028. When I filed the patent application that led to the '871 patent, I
`
`intended this patent application to cover both versions of the sequencer's control
`intended this patent application to cover both versions of the sequencer's control
`
`flow
`flow.
`
`15. The first version, described in Version 0.4 of the R400 Sequencer
`15. The first version, described in Version 0.4 of the R400 Sequencer
`
`Specification, was designed for sixteen vertex clauses and sixteen pixel clauses.
`Specification, was designed for sixteen vertex clauses and sixteen pixel clauses.
`
`SeeEx.2010, pp. 5, 14-15. ATI presented this version to Microsoft to see whether
`See Ex. 2010, pp. 5, 14-15. ATI presented this version to Microsoft to see whether
`
`the R400 was compatible with the application-programming interface ("API") that
`the R400 was compatible with the application-programming interface ("API") that
`
`Microsoft was developing, called DXl0. Microsoft rejected this version because
`Microsoft was developing, called DX10. Microsoft rejected this version because
`
`Microsoft's API required a sequencer that could process an unlimited number of
`Microsoft's API required a sequencer that could process an unlimited number of
`
`clauses. To be compatible with this requirement, I developed a second version of
`clauses. To be compatible with this requirement, I developed a second version of
`
`the sequencer control flow. This second version is described in Version 2.0 of the
`the sequencer control flow. This second version is described in Version 2.0 of the
`
`R400 Sequencer Specification. SeeEx.2028.I explain these versions in turn
`R400 Sequencer Specification. See Ex. 2028. I explain these versions in turn
`
`below.
`below
`
`1. R400 Sequencer Specfficøtion (Versíon 0.4): August 24, 2001
`1. R400 Sequencer Specification (Version 0.4): August 24, 2001
`16. Version 0.4 of the R400 Sequencer Specification is dated August24,
`16. Version 0.4 of the R400 Sequencer Specification is dated August 24,
`
`2001. See Ex. 2010, p. 3; see also Ex. 2043 (for the log entry on August 24, 2001)
`2001. See Ex. 2010, p. 3; see also Ex. 2043 (for the log entry on August 24, 2001).
`
`-8-
`-8
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`This version includes the same sequencer-block diagram as the sequencer-block
`This version includes the same sequencer-block diagram as the sequencer-block
`
`diagram in the R400 Top Level Specification (reproduced again below for
`diagram in the R400 Top Level Specification (reproduced again below for
`
`convenience). CompareEx.2010, p. 5 withEx.2047, p. 30. Version 0.4 also
`convenience). Compare Ex. 2010, p. 5 with Ex. 2041, p. 30. Version 0.4 also
`
`includes an example of the flow of pixels and vertices through the system. SeeEx.
`includes an example of the flow of pixels and vertices through the system. See Ex.
`
`2070, pp.3, l7-19.
`2010, pp. 3, 17-19.
`
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`-9-
`9
`
`LG Ex. 1037, pg 11
`
`(cid:9)
`ATI Ex. 2118
`
`IPR2023-00922
`Page 11 of 66
`
`

`

`
`
`17. The sequencer has two sets of reservation stations, one for pixels d
`The sequencer has two sets of reservation stations, one for pixels and
`17. (cid:9)
`
`one for vertices. Id. at 4-5. A representation of the two sets of reservation stations
`one for vertices. Id at 4-5. A representation of the two sets of reservation stations
`
`is shown below. Each set has eight ALU reservation stations and eight texture
`is shown below. Each set has eight ALU reservation stations and eight texture
`
`reservation stations . Id. Each reservation station stores clauses. Id. These clauses
`reservation stations. Id. Each reservation station stores clauses. Id. These clauses
`
`contain a sequence of instructions. Id. at4 ("fthe sequencer] . . . executes all of the
`contain a sequence of instructions. Id. at 4 ("[the sequencer] . . . executes all of the
`
`instructions in a clause"); see alsoEx.2042, p. 7 ("instructions in a clause will be
`instructions in a clause"); see also Ex. 2042, p. 7 ("instructions in a clause will be
`
`executed sequentially").
`executed sequentially")
`
`Pixel Reservation Stations
`Pixel Reservation Stations
`
`Vertex Reservation Stations
`Vertex Reservation Stations
`
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`18. Clauses flow down each set of reservation stations. See Ex. 2010, pp.
`Clauses flow down each set of reservation stations. See Ex. 2010, pp.
`18. (cid:9)
`
`4-5. Pixel clauses flow down the set of pixel reservation stations, and vertex
`4-5. Pixel clauses flow down the set of pixel reservation stations, and vertex
`
`clauses flow down the vertex reservation stations. See id. Reservation stations
`clauses flow down the vertex reservation stations. See id. Reservation stations
`
`touch the arbiter, so the ALU arbiters and the texture arbiters can select clauses
`touch the arbiter, so the ALU arbiters and the texture arbiters can select clauses
`
`traveling down the reservation stations. See id. at 17 ("the control packet continues
`traveling down the reservation stations. See id. at 17 ("the control packet continues
`
`-10-
`- 10 -
`
`LG Ex. 1037, pg 12
`
`(cid:9)
`ATI Ex. 2118
`
`IPR2023-00922
`Page 12 of 66
`
`

`

`
`
`to travel down the path of reservation stations until all clauses have been
`
`executed").
`executed").
`
`19. The arbiterlarbitration logic has two levels of arbitration, collectively
`The arbiter/arbitration logic has two levels of arbitration, collectively
`19. (cid:9)
`
`shown in red on the figure below.
`shown in red on the figure below.
`
`Vertex Clauses
`Vertex Clauses
`
`Pixel Clauses
`Pixel Clauses
`
`0
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`"SEQ arbitrates between the Pixel FIFO and the Vertex FIFO"
`"SEQ arbitrates between the Pixel FIFO and the Vertex FIFO"
`
`20. The first level of arbitration is between ALU clauses and texture
`The first level of arbitration is between ALU clauses and texture
`20. (cid:9)
`
`clauses for both the vertex set of reservation stations and the pixel set of
`clauses for both the vertex set of reservation stations and the pixel set of
`
`reservation stations. This first level of arbitration is represented by the ALU
`reservation stations. This first level of arbitration is represented by the ALU
`
`arbitrators and texture arbitrators labeled in the figure above. ALU arbitration logic
`arbitrators and texture arbitrators labeled in the figure above. ALU arbitration logic
`
`- 11-
`
`LG Ex. 1037, pg 13
`
`(cid:9)
`ATI Ex. 2118
`
`IPR2023-00922
`Page 13 of 66
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`

`

`
`
`chooses one of the eight potentially pending ALU clauses stored within the ALU
`chooses one of the eight potentially pending ALU clauses stored within the ALU
`
`reservation stations. See id. at 14-15. Texture arbitration logic chooses one of the
`reservation stations. See id. at 74-15. Texture arbitration logic chooses one of the
`
`eight potentially pending texture clauses stored within the texture reservation
`eight potentially pending texture clauses stored within the texture reservation
`
`stations. See id. at 14.
`stations. See id. at 14
`
`2I. For the second level of arbitration, the arbitration logic selects
`21. For the second level of arbitration, the arbitration logic selects
`
`between the pixel and the vertex. See id. at 17 (2) ("SEQ arbitrates between the
`between the pixel and the vertex. See id. at 17 (2) ("SEQ arbitrates between the
`
`Pixel FIFO and the Vertex FIFO"), 18 (4) ("SEQ arbitrates between Pixel FIFO
`Pixel FIFO and the Vertex FIFO"), 18 (4) ("SEQ arbitrates between Pixel FIFO
`
`and Vertex FIFO"). So, not only does the arbiter select which clauses to execute,
`and Vertex FIFO"). So, not only does the arbiter select which clauses to execute,
`
`the arbiter also selects which order to execute pixels and vertices. See id. at 4 ("a
`the arbiter also selects which order to execute pixels and vertices. See id. at 4 ("a
`
`pixel can pass a vertex and a vertex can pass a pixel").
`pixel can pass a vertex and a vertex can pass a pixel").
`
`22. The ALU arbitration and the texture arbitration give priority to
`22. The ALU arbitration and the texture arbitration give priority to
`
`reservation stations/clauses closer to the bottom of the pipeline. See id. After this
`reservation stations/clauses closer to the bottom of the pipeline. See id. After this
`
`arbitration selects winning pixel and vertex clauses, the pixel/vertex arbitration
`arbitration selects winning pixel and vertex clauses, the pixel/vertex arbitration
`
`logic selects between the pixel and the vertex. Id. at 17 (2),18 (4). Vertices
`logic selects between the pixel and the vertex. Id. at 17 (2), 18 (4). Vertices
`
`generally have priority. Id at 77 (2). When a vertex is not pending or the register
`generally have priority. Id. at 17 (2). When a vertex is not pending or the register
`
`files do not have open space for a vertex, the arbiter selects a pixel. Id. at l8 (4)
`files do not have open space for a vertex, the arbiter selects a pixel. Id. at 18 (4).
`
`23. Once arbitration logic selects the pixel/vertex clauses, the sequencer's
`23. Once arbitration logic selects the pixel/vertex clauses, the sequencer's
`
`arbitration logic provides the clauses to a register file in the shader pipe. See id. at
`arbitration logic provides the clauses to a register file in the shader pipe. See id. at
`
`pp. 17 (5) ("SEQ constructs a control packet for the vector and sends it to the first
`pp. 17 (5) ("SEQ constructs a control packet for the vector and sends it to the first
`
`-12-
`- 12 -
`
`LG Ex. 1037, pg 14
`
`ATI Ex. 2118
`
`IPR2023-00922
`Page 14 of 66
`
`

`

`
`
`reservation station (the FIFO in front of texture state machine 0, or TSMO FIFO)
`reservation station (the FIFO in front of texture state machine 0, or TSMO FIFO)
`
`the control packet contains the state pointer, the tag to the position cache and a
`the control packet contains the state pointer, the tag to the position cache and a
`
`register file base pointer."),17 (9) ("ASM0 accepts the control packet (after being
`register file base pointer."), 17 (9) ("ASMO accepts the control packet (after being
`
`selected by the ASM arbiter) and gets the instructions for ALU clause 0 from the
`selected by the ASM arbiter) and gets the instructions for ALU clause 0 from the
`
`global instruction store")
`global instruction store").
`
`24. The shader pipe, as of Version 0.4 of the R400 Sequencer
`24. (cid:9)
`The shader pipe, as of Version 0.4 of the R400 Sequencer
`
`Specification (reproduced below for reference), has four physical register file
`Specification (reproduced below for reference), has four physical register file
`
`memories per shader pipeline.Id. at 10.
`memories per shader pipeline. Id. at 10.
`
`-t3-
`- 13 -
`
`LG Ex. 1037, pg 15
`
`ATI Ex. 2118
`
`IPR2023-00922
`Page 15 of 66
`
`

`

`
`
`it
`
`Register RI!
`RËgide¡Fil!
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`25. Each register file is coupled to a bank of ALUs. See id. at 11. The
`Each register file is coupled to a bank of ALUs. See id. at 11. The
`25. (cid:9)
`
`gray area of the Figure reproduced below shows the logical view of the four
`gray area of the Figure reproduced below shows the logical view of the four
`
`register files within the shader pipe as software would see it. Id. The Figure also
`register files within the shader pipe as software would see it. Id. The Figure also
`
`-14-
`- 14 -
`
`LG Ex. 1037, pg 16
`
`ATI Ex. 2118
`
`IPR2023-00922
`Page 16 of 66
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`

`

`shows an ALU bank, a texture unit, an instruction store/cache, and a constant store.
`shows an ALU bank, a texture unit, an instruction store/cache, and a constant store.
`
`
`
`See id.
`See id.
`
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`26. In the Figure reproduced above, the sequencer block comprises the
`In the Figure reproduced above, the sequencer block comprises the
`26. (cid:9)
`
`instruction store and the constant store. In a different representation, reproduced
`instruction store and the constant store. In a different representation, reproduced
`
`below, the instruction store and the constant store are within the sequencer block.
`below, the instruction store and the constant store are within the sequencer block.
`
`-15-
`- 15 -
`
`LG Ex. 1037, pg 17
`
`ATI Ex. 2118
`
`IPR2023-00922
`Page 17 of 66
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`

`

`
`
`c
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`
`27. Later versions of the R400 Sequencer Specification show the
`Later versions of the R400 Sequencer Specification show the
`27. (cid:9)
`
`sequencer and the shader pipe within the R400 architecture. See, e.g.,Bx.2012, pp.
`sequencer and the shader pipe within the R400 architecture. See, e.g., Ex. 2012, pp.
`
`3, 5. Th