UNITED STATES PATENT AND TRADEMARKOFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`LG ELECTRONICS, INC.,
`Petitioner,
`
`V.
`
`ATI TECHNOLOGIES ULC,
`Patent Owner.
`
`
`
`Case IPR2015-00326
`Patent 6,897,871 Bl
`
`
`DECLARATION OF ANDREWWOLFE
`REGARDINGU.S. PATENT NO.6,897,871
`
`Mail Stop “Patent Board”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`ATT 2003
`
`LGvy. ATI
`IPR2015-00326
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`Case IPR2015-00326 of
`U.S. Patent No. 6,897,871
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`Table of Contents
`
`I.
`
`TE.
`
`INTRODUCTION ooooicccccccccccccccccccscecseceeseesceeeeseeeseeeseeessecssecssecssecssessestaeenees 1
`
`BACKGROUND ooo ccccccccccsecesecesecesecsecsecssecssesesessscssessssssssestetsseesaeenes 2
`
`TH.=EXHIBITS ooo cccccccccccscccseccseccsecssecssecseessecssecssecssessessssscssseeseesseenes 7
`
`IV. OVERVIEW OF THE LAW USED FOR THIS DECLARATION............. 10
`
`A.
`
`Burden of Proof... cccccccccessceesseceseeeeseeesessescectseecsessetenieeess 11
`
`B.—Level of skillin the art 0000.00 ccee ccc ects teettetneteneeens 11
`
`C.
`
`Reduction to Practice... ccc ccccccccceseceeseccneceseceeeecsscssseecsseeeeeenaes 12
`
`1.
`
`2.
`
`Actual Reduction to Practice 00.00.0000 cec cece cette eeeeeees 13
`
`Constructive Reduction to Practice... ccc cccceceeetetenees 13
`
`NOVENY coon ccc cccccne cece cece se sees esceseseeseseeseneesenesectsesecssstteeneeees 14
`
`ODVIOUSIESS 00.0... cccecceecceccecseeeseceeseecsseceseeecsseeseceeseeecssscteeetseenateaees 14
`
`ObviOUSNESS tO COMDING 0... ccc cece cece ceseceeseeessestseeetsseessesetseeesenenies 16
`
`D.
`
`E.
`
`F,
`
`G.-CConstruction ooo. cc cece ceeccccececenecenseeenseersetecsesenseeetsteenseeneees 17
`
`VV.
`
`INSTITUTED GROUNDS 1... ccc ccc ccscceecenseeneeeeenssecsesssesseststenees 17
`
`VE
`
`TECHNOLOGYooooooccoccccccccccccece cece cee ceeeceee see sees etc eeseeteesecettetitetiteneeneens 18
`
`A,
`
`B.
`
`C.
`
`D.
`
`Terminologies... cc cccccccccccsscccesseeeseseeecesssesecssescesseeccsteeeseeenaes 18
`
`General OVerview ooo... ccc cece cece cee ceneceene et ee tet ectstecettuntteteeens 19
`
`Conventional graphics systems used separate shaders for vertex
`calculations and pixel calculations .......0000000c cece cecctececeeeeeeneteeees 21
`
`Drawbacks of graphics systems using separate vertex and pixel
`SHAMCTS ooo cece ccccecsseeescecsseeeseeecseecsseceeseeesseseeseecesesssessiseensseeitenseees 22
`
`VIL. U.S. PATENT NO. 6,897,871 ooo. ccccccccscceteccecnsecnsecssecssscssscssessestieseees 27
`
`Vl. BACKGROUND ON CHIP DESIGN AND ATTS CHIP DESIGN........... 28
`
`IX.
`
`THE CODE FOR ATI’S R400 CHIP ooo. cccccccccccecsecctetetectesseeeaees 31
`
`AL
`
`Cham icc cece cece cee eects e cee eeeeeeseetesstesesstsetesttstteteeees DD
`
`lL.
`
`2.
`
`3,
`
`The Preamble oo... ccc cccccccccsseceeseeeseseseeessesceseecssesstseessanenaes 35
`
`The Arbiter Circuit ......00000000ccccc cece ccc cceecectesceeeseneeseceeeesneeees 35
`
`The shader coupled to the arbiter circuit ....000.0 eee 45
`
`-i-
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`a.
`
`b.
`
`C.
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`Case IPR2015-00326 of
`USS. Patent No. 6,897,871
`The shader is operative to process the selected one
`of the plurality of inputs .0..0.00 ccc ccceeeeeseeeeeneaes48
`
`The shader including means for performing vertex
`operations and pixel operations ........00..cc cee ecceeeeeenees 50
`
`The shader also includes means for performing one
`of the vertex operations or pixel operations based
`on the selected one of the plurality of inputs.......000.0..... 58
`
`d.
`
`And the shader provides a appearance attribute. ............ 58
`
`CDA2c cccccceccceesteccseeecssecsseceecsseceeeeeseeestseecsseesseecsssstiteseeeeeeeess 73
`
`C13 ccc cccccccccsecsteeessceessecsseceecsseceeeeeseeeseseecseesseenssetitereeeeeeeess 75
`
`1.
`
`2.
`
`The vertex storage block further includes a parameter
`COCK. cccccccceccsccssecssecsseccnsecsecssecseescsesssesssessescasssaseseeeseeeaes 76
`
`The vertex storage block and a position cache...........0.....0.6 83
`
`CDat Soe ccc cccnteceececeeseeeetecseececseeeceseeessssseccsssseecsatestsaeeeeaeeses 88
`
`1.
`
`2,
`
`The appearanceattribute is position 200.0... 00 eeceee erences 88
`
`The position attribute is associated with a corresponding
`VETEOX ccc cece cccnsececneeeeseesseceesseeessseecessceessseeeccssterseeeneieeees 92
`
`C16 ccc cccccccccsecsteecsececssecsseceecsseceseeeeseeestseesssessiseecsssetiteseeseteeeess 93
`
`1.
`
`2,
`
`The appearanceattribute is Color 0.20.00 cccceccceeeeceeeseeeees93
`
`The color attribute is associated with a corresponding
`PIX] cc ccc ccceccecsnececsecssecceseecenseseeccsstsecsutescsateesseeeesaeeees96
`
`1A8 ccc ccccccccecseccsececseeesseceecsseceeeeeseeessseessseessseecissstitesseeseteeeess 97
`
`CDA9 ccc ccc cccectteceseceeseeeseceeeseseseeeeseeestsesssseesseessssenitereeeeeeeegs 98
`
`1.
`
`2.
`
`3.
`
`The selection Circuit 0.0.0 ccccccccccccesesecseecseesteeetseesatesseeeseeees 99
`
`The control signal.....0...000 cece cece cccec cece ce ceseceeececeuteesseeesiees 102
`
`The arbiter is coupled to the multiplexer... 103
`
`Chaim 10 icc cece cc cece eens cece teens teteeeetetecietittteceieeteesteteteees 103
`
`lL.
`
`2.
`
`3.
`
`The vertex position data... ccccccccccccccccccssecsescetstecsteesseeesees 104
`
`The primitive assembly block coupled to the shader.............. 105
`
`The primitive assembly block is operative to generate
`PTUMELDVESocc eect eee ce eee cene cee te tobe teceeetteeneeeeteees 107
`
`-ii-
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`Case IPR2015-00326 of
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`Charm D1 occ ccc cccececccsececseecseeeecsseesseeeeseeeseseessesseestsesetieeseesseeees 109
`
`I,
`
`1.
`
`2.
`
`The Raster Engine oo... coccccccceccceececceecececeenteeteteesteeseertes 110
`
`
`Generating the pixel parameter... ccc cccceeceseceeneees 112
`
`J.
`
`C)atm 13 icc cc ce ccecete cece ee ceneteteeeebeeecietiestecttetestiteeeseeed 113
`
`lL.
`
`2.
`
`3,
`
`The register DIOCK..0000 coc ccceccccccscccessececesssssecsuececateessseeeesaees 114
`
`The computation clement .........000 ccc ccc ccc cccecceecenteceees 119
`
`The Sequencer 0.0... 0.0 cccccccccscccccssccccsseeecesssssccsuececateesaeeeesaees 124
`
`Ke
`
`Chat 15 ccc cccccceceseceesseecesseecseeeeeecceesssesesseststersesssseeesees 132
`
`1.
`
`2.
`
`3.
`
`A general purpose register DBlOCK oo... ccc ccceeeetseceeteees 133
`
`The ProcesSOr UNIt oo. c cc ccecccccccccccessececesssesccsuececuteesaeeeesaees 135
`
`The S@quencer .........00. ccc cccecce cece cece ceevceseseveetsecuteetteeessaees 135
`
`a.
`
`b.
`
`Coupled to the general purpose register... 135
`
`The sequencer maintains instructions.....0000000000000000. 138
`
`L.
`
`1am 17 ccc ccecccseceeseeeseceeeseeesseeeeseeeseseccsecseestsseeatenseeeeseees 139
`
`M., Chat 18 occ cece cecnne cee ceeeesesettesecrsetetattesttteetteeeseeees 142
`
`N.C)atm 20 cc ccccccccccccseceeeecseeeeeseecnseeesseeccseesssssessesttstetsesesseensees 142
`
`THE CLAIMS OF THE °871 PATENT ARE SUPPORTED BY THE
`PRIORITY DOCUMENT0... cccccccccccccccsccescccsceeeeecssecssecssecsestsestseeneeeeeens 143
`
`Xi.
`
`CONCEPTION0000000 ccc cece secs cece eee bene su secu ee tu sesueseetestiteieteeeseeeets 175
`
`Xl.
`
`OVERVIEW OF THE APPLIED REFERENCES FOR GROUNDS
`Dad eee cece ce eeee attest eeeeeeeeeeteeceeeeesseseeeetecestsettcttcetscitesteteeneees 236
`
`AL RICK ccc ccc ccccssceeccseseseeesseecseeeseecseeestecsescssssssscsescesteeneeieeess 236
`
`Bo Raptrance cece cece ccece cece sens tecbesccssesssttstitecteseseenees 240
`
`All,
`
`GROUNDS6 AND 9: OBVIOUSNESS GROUND BASED ON
`RICH AND KURIHARA 0oooooooccccccccccccec cece ccc ce ccc ee ce tbbetbeetbceteteteneeeneeees 242
`
`A.
`
` APOSA would not have modified Rich in the way that LG and
`Dr. Bagherzadeh propose. ..........cccccccccccccsccceteecenesetttssesstsesenteeee DAD
`
`B.—Kurihara does not teach or suggest a “processor unit”that
`“executes vertex calculations while the pixel calculations are
`still in progress,” as in Claim 20. 0000.0... ccce ce cccceectseeeenseeees256
`
`C.
`
`Objective indicia Of NON-ODVIOUSNESS.....0...cc ccc cece cccceeeesseeeeaees261
`
`- ili -
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`XIV. CONCLUSION 2c cccccceeencecsesnsececeseeeveseveeeverevnresateneeccestestrsteversate 265
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`Case IPR2015-00326 of
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`Case IPR2015-00326 of
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`I, Andrew Wolfe, declare as follows:
`
`1.
`
`INTRODUCTION
`
`1.
`
`I have been retained bythe patent owner, ATT Technologies ULC
`
`(“ATT”), to evaluate several technical issues relating to U.S. Patent No. 6,897,871
`
`(“the ’871 patent”).
`
`2.
`
`First, | have been asked to evaluate source code related to the
`
`development of the “R400”projectat its state of development on August 5, 2002,
`
`and to provide my opinion regarding whether the functionality of this source code
`
`for the R400 chip and the structure it describes corresponds to each and every
`
`element as set forth in claims 1, 2, 3, 5, 6, 8,9, 10, 11, 13, 15, 17, 18, and 20 ofthe
`
`°871 patent. As set forth below,it is my opinion that this source code includes
`
`everylimitation of these claims.
`
`3.
`
`Second, | have been asked to review U.S. Patent Application No.
`
`10/718,318 (‘the °318 application”), filed November 20, 2003, to which the ’871
`
`patent claims priority, and to provide my opinion regarding whetherclaims 1, 2, 3,
`
`5, 6, 8,9, 10, 11, 13, 15, 17, 18, and 20 are supported bythe 318 application. As
`
`set forth below,it is my opinion that the °318 application provides support for
`
`every limitation of these claims.
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`Lhird, | have been asked to review ATI’s internal documents relating
`
`4,
`
`to the R400 project to provide my opinion regarding whether the inventors of the
`
`°871 patent conceived claims 1, 2, 3,5, 6, 8,9, 10, 11, 13, 15, 17, 18, and 20. As
`
`set forth below,it is my opinion that these internal documents showthat the °871
`
`patent inventors conceived of every limitation of these claims.
`
`5.
`
`Fourth, | have been asked to review Rich and Kurihara and to provide
`
`myopinion regarding whether these references render obvious claims 15 and 20.
`
`Asset forth below,it is my opinion that claims 15 and 20 are patentable over these
`
`references.
`
`1.
`
`BACKGROUND
`
`6.
`
`I have more than 30 years of experience as a computerarchitect,
`
`computer system designer, personal computer graphics designer, educator, and
`
`executive in the electronics industry. A curriculum vitae is attached as Exhibit
`
`2003 to this report and is summarized below.
`
`7.
`
`In 1985, I earned a B.S.E.E. in Electrical Engineering and Computer
`
`Science from The Johns Hopkins University. In 1987, | received an M.S. degree in
`
`Electrical and Computer Engineering from Carnegie Mellon University. In 1992, I
`
`received a Ph.D. in Computer Engineering from Carnegie Mellon University. My
`
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`doctoral dissertation pertained to a newapproachfor the architecture of a computer
`
`processor.
`
`8.
`
`In 1983, I began designing touch sensors, microprocessor-based
`
`computer systems, and I/O (input/output) cards for personal computers as a senior
`
`design engineer for Touch Technology, Inc. During the course of my design
`
`projects with Touch Technology, I designed I/O cards for PC-compatible computer
`
`systems, including the IBM PC-AT, to interface with interactive touch-based
`
`computer terminals that I designed for use in public information systems. I
`
`continued designing and developing related technology as a consultant to the
`
`Carroll Touch division of AMP, Inc., where in 1986, I designed one ofthe first
`
`custom touch screen integrated circuits.
`
`9.
`
`While I studied at Carnegie Mellon University for my master’s
`
`degree, from 1986 and through 1987, I designed and built a high-performance
`
`computer system. From 1986 through early 1988, I also developed the curriculum,
`
`and supervised the teaching laboratory, for processor design courses.
`
`10.
`
`In the latter part of 1989, I worked as a senior design engineer for
`
`ESL-TRW Advanced Technology Division. While at ESL-TRW,I designed and
`
`built a bus interface and memory controller for a workstation-based computer
`
`system, and also worked on the design of a multiprocessor system.
`
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`ll. Atthe end of 1989, | (along with mypartners) reacquired the rights to
`
`the technologyI had developed at Touch Technology and at AMP, and founded
`
`The Graphics Technology Company. Over the next seven years, as an officer and a
`
`consultant for The Graphics Technology Company, I managed the company’s
`
`engineering developmentactivities and personally developed dozens of touch
`
`screen sensors, controllers, and interactive touch-based computer systems.
`
`12.
`
`Ihave consulted, formally and informally, for a numberof fabless
`
`semiconductor companies. In particular, I have served on the technical advisory
`
`boards for two processor design companies: BOPS, Inc., where I chaired the board,
`
`and Siroyan Ltd., where I served in a similar role for three networking chip
`
`companies—Intellon, Inc., Comsilica, Inc., and Entridia, Inc—and one 3D game
`
`accelerator company, Ageia, Inc.
`
`13.
`
`[have also served as a technology advisor to Motorola and to several
`
`venture capital funds in the United States and Europe. Currently, | am a director of
`
`Turtle Beach Corporation, providing guidance in its development of premium
`
`audio peripheral devices for a variety of commercial electronic products.
`
`14.
`
`From 1991 through 1997, I served on the Faculty of Princeton
`
`University as an Assistant Professor of Electrical Engineering. At Princeton,I
`
`taught undergraduate and graduate-level courses in Computer Architecture,
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`Advanced Computer Architecture, Display Technology, and Microprocessor
`
`Systems, and conducted sponsored research in the area of computer systems and
`
`related topics. I was also a principal investigator for Department of Defense
`
`(“DOD”) research in video technology and a principal investigator for the New
`
`Jersey Center for Multimedia Research. From 1999 through 2002, I taught the
`
`Computer Architecture course to both undergraduate and graduate students at
`
`Stanford University multiple times as a Consulting Professor. At Princeton, I
`
`received several teaching awards, both from students and from the School of
`
`Engineering. | have also taught advanced microprocessor architecture to industry
`
`professionals in IEEE and ACM sponsored seminars. I am currently a lecturerat
`
`Santa Clara University teaching graduate courses on Computer Organization and
`
`Architecture and undergraduate courses on electronics and embedded computing.
`
`15.
`
`From 1997 through 2002, I held a variety of executive positionsat a
`
`publicly-held fabless semiconductor companyoriginally called S3, Inc. and later
`
`called SonicBlue Inc. I held the positions of Chief Technology Officer, Vice
`
`President of Systems Integration Products, Senior Vice President of Business
`
`Development, and Director of Technology, among others. At the time I joined S3,
`
`the companysupplied graphics accelerators for more than 50% of the PCs sold in
`
`the United States.
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`16. While at S3/SonicBlue I developed technology for and participated in
`
`the development of products for digital music and digital video including HDTVs,
`
`DVD players and recorders, DVRs, portable video devices, PDAs, andtablets. I
`
`also supervised the video research and development team.
`
`17.
`
`Thave published more than 50 peer-reviewed papers in computer
`
`architecture and computer systemsand IC design.
`
`18.
`
`T also have chaired IEEE and ACM conferences in microarchitecture
`
`and integrated circuit design and served as an associate editor for IEEE and ACM
`
`journals.
`
`19.
`
`Jam anamedinventoron at least 43 U.S. patents and 27 foreign
`
`patents.
`
`20.
`
`In 2002, I was the invited keynote speaker at the ACM/TEEE
`
`International Symposium on Microarchitecture and at the International Conference
`
`on Multimedia. From 1990 through 2005, I was also an invited speaker on various
`
`aspects of technology and the PC industry at numerous industry events including
`
`the Intel Developer’s Forum, Microsoft Windows Hardware Engineering
`
`Conference, Microprocessor Forum, Embedded Systems Conference, Comdex, and
`
`Consumer Electronics Show, as well as at the Harvard Business School and the
`
`University of Illinois LawSchool. I have been interviewed on subjects related to
`
`-6-
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`computer graphics and video technology and the electronics industry by
`
`publications such as the Wall Street Journal, New York Times, Los Angeles
`
`Times, Time, Newsweek, Forbes, and Fortune as well as CNN, NPR, and the BBC.
`
`I have also spoken at dozens of universities including MIT, Stanford, University of
`
`Texas, Carnegie Mellon, UCLA, University of Michigan, Rice, and Duke.
`
`21.
`
`Tam being compensated for my time working on this case at my
`
`customaryrate of $450 per hour for work performed on the case. My compensation
`
`is not in any way related to the outcomeofthe case.
`
`Il. EXHIBITS
`
`22.
`
`In this Declaration, I cite to the following Exhibits.
`
`
`
`
`
`United States Patent No. 6,897,871 to Morein ef al.
`
`
`
`
`
`
`1002
`Prosecution History of U.S. Patent No. 6,897,871
`
`
`1003
`Declaration of Dr. Nader Bagherzadeh
`
`
`1004
`U.S. Patent 7,015,913 to Lindholm ef al.
`
`
`1005
`USS. Patent No. 5,808,690 to Rich
`
`
`1006
`US. Patent No. 7,376,811 B2 to Kizhepat
`
`
`1007
`
`US. Patent No. 5,500,939 to Kunhara
`
`1008
`
`Mark Segal and Kurt Akeley, The OpenGL® Graphics System:
`A Specification (Version 1.4) (Chris Frazier and Jon Leech eds.,
`Silicon Graphics, Inc. 2002)
`1009|CurriculumVitaeofDr.NaderBagherzadeh
`
`-7-
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`Case IPR2015-00326 of
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`2004
`Curriculum Vitae of Dr. Andrew Wolfe
`
`
`2010
`R400 Sequencer Specification (Version 0.4)
`
`
`
`
`
`
`2028
`R400 Sequencer Specification (Version 2.0)
`
`2041
`R400 Top Level Specification (Version 0.2)
`2042
`R400 Shader Processor (Version1.2)
`
`
`
`
`
`
`Deposition Transcript of Nader Bagherzadeh, Ph.D., taken
`Sept. 15, 2015
`Deposition Transcript of Nader Bagherzadeh, Ph.D. for
`
`IPR2015-00325, taken Aug. 14, 2015
`Uniram Technology, Inc. v. Taiwan Semiconductor
`Manufacturing Co., Ltd., et al., 3:04-cv-01268-VRW,Findings
`of Facts and Conclusions of Law, Dkt. No. 627, April 14, 2008
`United States Patent Application No. 10/718,318 to Morein et
`2076
`al.
`
`
`
`2077
`
`2078
`
`Graham Singer, History of the Modern Graphics Processor,
`
`Part 3, TechSpot (Apr. 10, 2013)
`David Luebke & Greg Humphreys, How GPUs Work, IEE!
` (Tl
`
`Computer, 96-100 (2007)
`Microsoft and ATI Technologies Announce Technology
`2079
`
`Development Agreement, Microsoft (Aug. 14, 2003)
`
`2080
`
`2081
`
`2082
`
`2083
`
`2084
`
` Anton Shilov, ATI and NVIDIA Proclaim Different Graphics
`
`Processors Architecture Goals: ATI Says Unified Rendering
`Engine — the Way to Go, NVIDIA Disagrees, Xbit (Dec. 23,
`
`2004, 7:55 AM)
`Anton Shilov, NVIDIA Chief Architect: Unified Pixel and
`Vertex Pipelines — The Way to Go. NVIDIA SaysIt Would
`Make a Chip with Unified Pipes ““When it Makes Sense,” Xbit
`
`(July 11, 2005, 11:07 PM)
`Yoo et al., Mobile 3D Graphics SoC: From Algorithm to Chip
`(2010)
`Luna, Introduction to 3D Game Programming with DirectX
`9.0, Figures 4.2, 5.7, pp. 94-97, 107-109 (2003)
`Ahmedef a/., OpenGL - Lighting, Material, Shading and
`
`Texture Mapping (August 28, 2009)
`
`-8-
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`2087
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`
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`
`
`2090
`
`2092
`
`
`
`
`
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`Case IPR2015-00326 of
`U.S. Patent No. 6,897,871
`
`2085
`MICROSOFT COMPUTER DICTIONARY (Sth Ed. 2002)
`2086
`Foley et al., Fundamentals of Interactive Computer Graphics
`
`(1984)
`S3 Graphics, DirectX 10 Architecture for Chrome 400 Series
`Discrete Graphics Processors, A $3 Graphics White Paper (July
`
`21, 2007)
`
`2088
`COLLIN, DICTIONARY OF COMPUTING(4th ed., 2002)
`2089
`Woo, J.H. et al., A 195/152-mW mobile multimedia SoC with
`fully programmable 3D graphics and MPEG4/H.264/JPEG.
`IEEFE J. Solid-St. Cire., 43 (9), 2047-2056 (2008)
`Technical Brief, NVIDIA GeForce® GTX 200 GPU
`
`Architectural Overview (May,2008)
`2091
`Intel® Processor Graphics DirectX Developer’s Guide (2008-
`
`2010)
`The Rise of Mobile Gaming on Android: Qualcomm®
`Snapdragon™Technology Leadership (2014)
`RTL CodeFile: sq.v
`2093
`RTL Code File: sq_ais_output.v
`2094
`2095
`RTL Code File: sq_alu_instr_queue.v
`
`2096|RTL Code File: sqaluinstrseq.v
`2097
`RTL CodeFile: sq_thread_arb.v
`2098
`RTL CodeFile: sq_input_arb.v
`
`RTL Code File: sq_instruction_store.v
`2099
`
`2100
`RTL Code File: sq_defs.v
`2101
`RTL Code File: sq_thread_buff.v
`2102
`RTL Code File: sq_target_fetch.v
`2103
`RTL Code File: sq export alloc.v
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`2104
`RTL CodeFile: vector.v
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`2105
`RTL Code File: macc_gpr.v
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`2106
`RTL Code File: export_control.v
`2107
`RTL Code File: macc.v
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`
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`2108
`RTL Code File: macc32.mc
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`
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`2109 RTL Code File: sx.v
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`
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`2110
`2111
`2112
`
`RTL Code File: parameter_caches.v
`RTLCode File: paramcache_ctl.v
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`RTL Code File: sp.v
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`RTL Code File: export_buffers.v
`2114|RTL Code File: pa.v
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`2115
`RTL Code File: pa_ag.v
`RTL CodeFile: pa_sxifecg.v
`RTL Code File: pa ccgsxifsm.v
`2117
`
`2118
`RTLCode File: se.v
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`2119
`Takahashi, The XBOX 360 Uncloaked (2006)
`
`2120 Microsoft Corporation Annual Report (2006)
`
`23.
`
`Exhibits 2077-2092 and 2119 are true and accurate copies of what
`
`they purportto be.
`
`24.
`
`This declaration represents only the opinions I have formed to date.I
`
`may consider additional documents as they becomeavailable or other documents
`
`that are necessary to form my opinions.I reserve the right to revise, supplement, or
`
`amend my opinions based on newinformation and on mycontinuing analysis.
`
`IV. OVERVIEW OF THE LAW USED FOR THIS DECLARATION
`
`25. When considering the °871 patent and stating my opinions, I am
`
`relying on legal principles that have been explained to me by counsel.
`
`-10-
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`
`A.
`
`Burden ofProof
`
`26.
`
`Iunderstand that for a claim to be found patentable, the claims must
`
`be, among other requirements, novel and nonobvious from what was knownat the
`
`time ofthe invention.
`
`27.
`
` Tunderstand that the information that 1s used to evaluate whether a
`
`claim is novel and nonobviousis referred to as priorart.
`
`28.
`
`Iunderstand that in this proceeding, LG has the burden of proving that
`
`each element of the challenged claims is rendered obvious by the alleged prior art
`
`references.
`
`B.
`
`Level ofskill in the art
`
`29.
`
` Thave been asked to considerthe level of ordinary skill in the art that
`
`someone would have had from August 2001 to November 2003. With over 30
`
`years of experience as a computer architect, computer system designer, personal
`
`computer graphics designer, educator, and executive in the electronics industry, I
`
`am well informed of the level of ordinary skill in the art. I understand that
`
`determining the level ordinary skill in the art takes into consideration:
`
`e Levels of education and experience of persons working in the field;
`
`e Types of problems encountered in the field; and
`
`-|l]-
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`e Sophistication of the technology.
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`Case IPR2015-00326 of
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`
`30.
`
`Based on the technologies disclosed in the ’871 patent and the
`
`considerations listed above, a person having ordinary skill in the art (‘POSA”)
`
`would haveat least a bachelor’s degree in electrical or computer engineering or
`
`computer science plus five years of experience in the computer graphics hardware
`
`industry, or a master’s degree in electrical or computer engineering or computer
`
`science plus two years of experience in that industry, or an equivalent combination
`
`of education and experience.
`
`31.
`
`Throughout my declaration, even if I discuss my analysis in the
`
`present tense, | am always making my determinations based on what a POSA
`
`would have knownat the time of the invention. Additionally, throughout my
`
`declaration, even if I discuss something stating “I,” I am referring to a POSA’s
`
`understanding.
`
`C.
`
`Reduction to Practice
`
`32.
`
`lunderstand there are two types of reduction to practice—actual
`
`reduction to practice and constructive reduction to practice. My understanding of
`
`each, I describe below.
`
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`T,
`
`Actual Reduction to Practice
`
`33.
`
`lunderstand that actual reduction to practice requires proof of either
`
`(i) an embodiment of a claimed invention or (11) performance of a processthat
`
`includes all limitations ofthe clarmed invention.
`
`34. Here, I have examined the R400 RTL code foran early version of the
`
`R400 written in Verilog. Verilog RTL codeis a structural and functional
`
`embodimentof a design that in the development of 3D graphics chips is generally
`
`used to model, define, and instantiate a hardware design. Below,I identify the
`
`specific files, objects, input/output interfaces, and functions that describe cach
`
`element of claims 1, 2,3, 5, 6, 8,9, 10, 11, 13, 15, 17, 18, and 20 of the ’871
`
`patent.
`
`2.
`
`Constructive Reduction to Practice
`
`35.
`
` Tunderstand that constructive reduction to practice occurs when the
`
`patent application discussing the subject matter of the claims is filed. In this case,
`
`the constructive reduction to practice occurred on November20, 2003, with the
`
`filing of the °318 Application. Below, I include a claim chart where I identify
`
`support for each element of claims 1, 2, 3,5, 6, 8, 9, 10, 11, 13, 15, 17, 18, and 20
`
`of the °318 Application.
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`
`D.
`
`Novelty
`
`36.
`
`lunderstand that a claim is unpatentable for being anticipated
`
`(sometimes called lack of novelty) if a prior art reference disclosed, at the time of
`
`the invention, each claim element as arranged in the claim. I also understand that if
`
`a prior art reference fails to expressly disclose one or more claim elements, the
`
`claim may be anticipated if the missing element(s) are inherently disclosed. I
`
`understand that to establish inherency, the evidence must make clearthat the
`
`missing claim element is necessarily present in the prior art reference. I understand
`
`that anticipation requires a high threshold because each and every claim element
`
`must be unambiguouslytaught by a single reference, either explicitly or inherently.
`
`EF.
`
`Obviousness
`
`37.
`
`Tunderstand that a patent claim is invalid if the claims would have
`
`been obvious to a POSAat the time of the invention. I understand that the
`
`obviousness inquiry should not be done in hindsight, but from the perspective of a
`
`POSAasof the time of invention of the patent claim.
`
`38.
`
`lunderstandthat to obtain a patent, the claims must have,as of the
`
`time of the invention, been nonobvious in viewof the priorart.
`
`-|4-
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`lunderstand that a claimis obvious whenthe differences between the
`
`39.
`
`subject matter sought to be patented and the prior art are such that the subject
`
`matter as a whole would have been obvious to a POSAatthe time the invention.
`
`40.
`
`lunderstandthat to prove that prior art reference or a combination of
`
`priorart references renders a patent obvious, it is necessary to: (1) identify the
`
`particular references that, singly or in combination, make the patent obvious;
`
`(2) specifically identify which elements of the patent claim appearin each of the
`
`asserted references; and (3) explain how a POSA could have combined thepriorart
`
`references to create the claimed invention.
`
`41.
`
`lunderstand that to support a conclusion that a prior art reference or a
`
`combination of prior art references renders a patent obvious, there must be some
`
`documentary evidence. Mere statements about whatis basic knowledgeor
`
`commonsense, /.e., common knowledgeas a replacement for documentary
`
`evidence, is insufficient to support a conclusion of obviousness.
`
`42.
`
`| understand that certain objective indicia can be important evidence
`
`regarding whether a patent is obvious. Such indicia include: industry acceptance,
`
`commercial success of products covered bythe patent claims; long-felt need for
`
`the invention; failed attempts by others to make the invention; copying of the
`
`invention by others in the field; unexpected results achieved by the invention as
`
`-1[5-
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`compared to the closest prior art; praise of the invention by the infringer or others
`
`in the field; taking of licenses under the patent by others; expressions of surprise or
`
`skepticism by experts and those skilled in the art at the making of the invention;
`
`and the patentee proceeded contrary to the accepted wisdom ofthepriorart.
`
`E.
`
`Obviousness to combine
`
`43.
`
`Junderstand that obviousness can be established by combining
`
`multiple prior art references to meet each and every claim element, but I also
`
`understand that a proposed combination of references can be susceptible to
`
`hindsightbias.
`
`44.
`
`| understand that references are more likely to be combinable if the
`
`nature of the problem to be solved is the same.
`
`45.
`
`lunderstand that if the combination of references results in the
`
`references being unsatisfactory for their intended purposes or the combination
`
`changes the references’ principle of operation, a POSA would not have a
`
`motivation to combine the references.
`
`46.
`
`Junderstand that teaching away, e.g., discouragement,is strong
`
`evidence that the references are not combinable. I also understand that a disclosure
`
`of more than one alternative does not necessarily constitute a teaching away. I
`
`understand that the combination does not needto result in the most desirable
`
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`embodiment, but if the proposed combination does not have a reasonable
`
`expectation of successat the time of the invention, a POSA would not have a
`
`teaching, suggestion, or motivation to combine the references.
`
`G.
`
`Claim construction
`
`47.
`
` lunderstand that in this /nter Partes Reviewproceeding the claims
`
`must be given their broadest reasonable interpretation consistent with the
`
`specification. In this declaration, I have used this broadest-reasonable-
`
`interpretation standard when interpreting the claim terms.
`
`48.
`
`lunderstand that the Board construed the term “means for performing
`
`vertex operations and pixel operations and performing one of the vertex operations
`
`or pixel operations based on the selected one of the plurality of inputs” to include a
`
`register, an instruction sequencer capable ofproviding instructionsfor performing
`
`vertex operations and pixel operations, and a processor capable offloating point,
`
`arithmetic, and logical operations on a selected input. For the purposesofthis
`
`proceeding, I apply that construction to my analysis below.
`
`Vv.
`
`INSTITUTED GROUNDS
`
`49.
`
`J understand that LG proposed nine groundsfor inter partes review
`
`based on two primary references: Lindholmand Rich. I understand that the Board
`
`denied LG’s Grounds5, 7, and 8 in their entirety, and denied Ground 6 with
`
`-|7-
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