//depot/r400/devel/partslib/src/gfix/pa/pa.v
`#148 change 91060 edit on 2003/03/19 by
`
`delifton@dclifton_r400 (ktext)
`
`Reverted width of IOPAscan and PA_IOscan
`
`back to 15 bits.
`
`#147 change 91033 edit on 2003/03/19 by
`
`delifton@dcelifton_r400 (ktext)
`
`Changed number of IOPAscan and PA_IOscan
`
`pins to 14 each.
`
`#146 change 90895 edit on 2003/03/19 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`add test signals
`
`#145 change 90862 edit on 2003/03/19 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`add commondft test ports
`
`#144 change 85882 edit on 2003/02/21 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`add blockbusyextender module to pa.v
`
`#143 change 76202 edit on 2003/01/13 by
`
`scamlin@scamlin_crayola_win (ktext)
`
`update memory order of patch chain
`
`#142 change 72728 edit on 2002/12/20 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`1. use sclk_ag to clock clipper registers that get reset when writes are done to
`pa cl enhance register to ensure register is clocked.
`
`2. add some test logic for soft reset
`
`(for test only; commented out).
`
`3.
`
`removed reset from pa cl enhance register
`
`#141 change 72494 edit on 2002/12/19 by
`
`delifton@dclifton_r400 (ktext)
`
`Fixed makefile to compile cot gate netlist.
`
`Added flush for writes to clenhance reg.
`Added daisy chain reads.
`
`Put state variable poiinter logic in pa_ag on hard reset.
`Put perfmon on hard reset.
`
`#140 change 71769 edit on 2002/12/17 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`1. update some non state-based perf signals
`
`to more closely match csim.
`
`2.
`
`remove some commented lines.
`
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`#148 change 91060 edit on 2003/03/19 by
`
`delifton@dclifton_r400 (ktext)
`
`Reverted width of IOPAscan and PA_IOscan
`
`back to 15 bits.
`
`#147 change 91033 edit on 2003/03/19 by
`
`delifton@dcelifton_r400 (ktext)
`
`Changed number of IOPAscan and PA_IOscan
`
`pins to 14 each.
`
`#146 change 90895 edit on 2003/03/19 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`add test signals
`
`#145 change 90862 edit on 2003/03/19 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`add commondft test ports
`
`#144 change 85882 edit on 2003/02/21 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`add blockbusyextender module to pa.v
`
`#143 change 76202 edit on 2003/01/13 by
`
`scamlin@scamlin_crayola_win (ktext)
`
`update memory order of patch chain
`
`#142 change 72728 edit on 2002/12/20 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`1. use sclk_ag to clock clipper registers that get reset when writes are done to
`pa cl enhance register to ensure register is clocked.
`
`2. add some test logic for soft reset
`
`(for test only; commented out).
`
`3.
`
`removed reset from pa cl enhance register
`
`#141 change 72494 edit on 2002/12/19 by
`
`delifton@dclifton_r400 (ktext)
`
`Fixed makefile to compile cot gate netlist.
`
`Added flush for writes to clenhance reg.
`Added daisy chain reads.
`
`Put state variable poiinter logic in pa_ag on hard reset.
`Put perfmon on hard reset.
`
`#140 change 71769 edit on 2002/12/17 by
`
`bhankins@fl_bhankins_r400_win (ktext)
`
`1. update some non state-based perf signals
`
`to more closely match csim.
`
`2.
`
`remove some commented lines.
`
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`#139 change 69259 edit on 2002/12/06 by dcelifton@dclifton_r400 (ktext)
`
`Eliminated ground nets in setupdebug buses.
`
`#138 change 69136 edit on 2002/12/06 by dclifton@dclifton_r400 (ktext)
`
`attached registered reset to pa_perfmon
`
`#137 change 69079 edit on 2002/12/06 by bhankins@fl_bhankins_r400_win (ktext)
`
`uncomment u0/1_pa_sx_wake_up_call signals
`
`#136 change 68717 edit on 2002/12/05 by bhankins@flbhankins r400win (ktext)
`
`add logic for pa to sx wake up call.
`
`commented out in pa.v
`
`#135 change 68177 edit on 2002/12/03 by scamlin@scamlin_crayola_unixorl (ktext)
`
`updated memory sizes
`
`#134 change 68127 edit on 2002/12/03 by bhankins@fl_bhankins r400_win (ktext)
`
`1. add vertex reordering bits from cliper to su
`
`2. add clipped_prim_seq_stall logic and bit to clip enhance reg
`
`3. add some non-state perf counter signals
`
`#133 change 67858 edit on 2002/12/02 by dclifton@dclifton_r400 (ktext)
`
`added clip_su_reordervtx input and expanded fifo to hold it. Changed provoking vertex
`logic in pa_su_geomprep block
`
`#132 change 67786 edit on 2002/12/02 by delifton@dclifton_r400 (ktext)
`
`Added temp fuse box for rams.
`
`#131 change 66979 edit on 2002/11/26 by viviana@viviana_crayola_unixorl (ktext)
`
`Added the delay block and IO connections.
`
`#130 change 66777 edit on 2002/11/25 by delifton@dclifton_r400 (ktext)
`
`Reducing clip_su_pt_size to 25 bits.
`
`#129 change 66692 edit on 2002/11/25 by bhankins@fl_bhankins +400win (ktext)
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`Reduced the width of the clipper's pointsize memory to 25 bits, as well as the
`pointsize datapath within the clipper.
`
`#128 change 66598 edit on 2002/11/25 by bhankins@fl_bhankins_r400_win (ktext)
`
`add a clipper debug bus
`
`#127 change 66573 edit on 2002/11/25 by bhankins@fl_bhankins_r400_win (ktext)
`
`rearrange clipper debug bus
`
`#126 change 66269 edit on 2002/11/22 by delifton@dcliftonr400 (ktext)
`
`Connected up additional debug buses.
`
`Fixed debugdata mux select in pa_rbiu.
`
`#125 change 66199 edit on 2002/11/22 by bhankins@fl_bhankins r400win (ktext)
`
`change state reg in pa_sxifecg so as not
`
`to support readback
`
`#124 change 65917 edit on 2002/11/21 by viviana@viviana_crayola_unixorl (ktext)
`
`Connected PA_rf_recen to STAR_testbus_rf[1].
`
`#123 change 65549 edit on 2002/11/20 by bhankins@fl_bhankins r400win (ktext)
`
`added clipper-oriented performance monitoring signals
`
`#122 change 65541 edit on 2002/11/20 by viviana@viviana_crayolaunixorl (ktext)
`
`Changed the reset going to the memories to hard reset.
`
`#121 change 65488 edit on 2002/11/20 by bhankins@flbhankins r400win (ktext)
`
`increase pa_clipper perf counter multicount values to 5 bits.
`
`#120 change 65272 edit on 2002/11/19 by bhankins@fl_bhankins +400win (ktext)
`
`add signals to debug busses
`
`#119 change 65233 edit on 2002/11/19 by viviana@viviana_crayolaunixorl (ktext)
`
`Added a port connection to the pa_rf_stp.v that was missing inside the pa.v
`
`#118 change 65200 edit on 2002/11/19 by viviana@viviana_crayolaunixorl (ktext)
`
`Added the pa_rf_stp (Virage processor),
`Scan IO and new Virage memories.
`
`the Test Controller and
`
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`#117 change 64457 edit on 2002/11/15 by bhankins@fl_bhankins_r400win (ktext)
`
`add more and fix some existing non-state based performance monitoring signals to
`
`pa_clipper.v
`
`#116 change 64397 edit on 2002/11/15 by bhankins@fl_bhankins r400_win (ktext)
`
`1. add non-state based performance monitoring signals to pa_cl_clipsm.
`
`2.
`
`fix some leda warnings in pa_cl_vert_storel.v
`
`#115 change 64364 edit on 2002/11/15 by bhankins@flbhankins r400win (ktext)
`
`add more to non-state based performance monitoring,
`
`including counter enable.
`
`#114 change 64055 edit on 2002/11/14 by bhankins@fl_bhankins r400win (ktext)
`
`1. start to add clprim non-state based performance monitoring signals.
`
`not complete.
`
`2. change assignment
`
`to non-blocking in register proc in pa_clvertstore3.v
`
`#113 change 64031 edit on 2002/11/14 by bhankins@fl_bhankins +400win (ktext)
`
`add non-state based performance monitoring signals to pa_sxifccg
`
`#112 change 63921 edit on 2002/11/14 by bhankins@fl_bhankins +400win (ktext)
`
`misc performance monitor bug fixes
`
`#111 change 63672 edit on 2002/11/13 by bhankins@fl_bhankins 1400win (ktext)
`
`add more performance monitoring
`
`#110 change 63528 edit on 2002/11/12 by dclifton@dclifton_r400 (ktext)
`
`Added performance counters
`
`#109 change 63365 edit on 2002/11/12 by bhankins@fl_bhankins_r400win (ktext)
`
`add pa_clipper and pa_sxifsm performance counter signals, and bring up to pa.v level
`for now.
`
`#108 change 63330 edit on 2002/11/12 by bhankins@fl_bhankins +400win (ktext)
`
`add debug bus to pa_sxifccg (clipperdebug3)
`
`#107 change 62865 edit on 2002/11/08 by viviana@viviana_crayola_unixorl (ktext)
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`Changed the STAR test buses for the pa_ag to get rid of the extra
`instantiations for the memories that should have been bit write memories.
`
`#106 change 62724 edit on 2002/11/08 by bhankins@fl_bhankins_r400_win (ktext)
`
`removed debug bus signal for synthesis (for now)
`
`#105 change 62708 edit on 2002/11/08 by bhankins@fl_bhankins_r400_win (ktext)
`
`removed debug bus from sxifceg for now for a quick synthesis
`
`#104 change 62684 edit on 2002/11/08 by bhankins@flbhankins r400win (ktext)
`
`register ROMspndisablevtx inputs
`
`#103 change 62673 edit on 2002/11/08 by bhankins@fl_bhankins r400win (ktext)
`
`add debug bus for pa_sxifecg block
`
`#102 change 62352 edit on 2002/11/07 by bhankins@fl_bhankins r400win (ktext)
`
`replace pa_cl_clip_to_outsm_fifo.v with an rtl version without latency.
`
`#101 change 62087 edit on 2002/11/06 by delifton@dcliftonr400 (ktext)
`
`Connected up debug busses, added cl_enhance reg to su,
`fixed typo in counters.
`
`removed reference to SU_ENHANCE,
`
`#100 change 61915 edit on 2002/11/06 by viviana@viviana_crayola_unix_orl
`
`(ktext)
`
`Added another set of STARpatch signals for the pntsz memory for the clipper.
`
`#99 change 61844 edit on 2002/11/05 by dclifton@dcliftonr400 (ktext)
`
`Added performance counter outputs to pa_su
`
`#98 change 61217 edit on 2002/11/02 by viviana@viviana_crayola_unixorl (ktext)
`
`Changed the instance names for the ati master clock instances and the rbbm interface.
`
`#97 change 61081 edit on 2002/11/01 by viviana@viviana_crayola_unixorl (ktext)
`
`Added the STAR test bus signals and wired up the hierarchy.
`
`#96 change 61080 edit on 2002/11/01 by dclifton@dclifton_r400 (ktext)
`
`Fixed problem with init_point_prim.
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`Added decode for debug and enhance registers
`
`#95 change 61041 edit on 2002/11/01 by bhankins@flbhankins r400win (ktext)
`
`infer pa_cl_enhance register and the connections to it.
`
`#94 change 60980 edit on 2002/11/01 by bhankins@fl_bhankins r400win (ktext)
`
`1. add clip_to_ga_ps_expand out of pa_clipper
`
`2. add initial code for clipper vertex reordering (hard-wired disabled).
`
`#93 change 60278 edit on 2002/10/30 by dclifton@dcliftonr400 (ktext)
`
`Changed name of ROMdisable bits to ROMdisablevtx. Connected to sxifecg block
`
`#92 change 60238 edit on 2002/10/30 by bhankins@fl_bhankins r400win (ktext)
`
`update for 4x clipper
`
`#91 change 60077 edit on 2002/10/29 by dclifton@dcliftonr400 (ktext)
`
`CHanges for clock speed-up and a few STAR bus additions or fixes.
`
`#90 change 60033 edit on 2002/10/29 by viviana@viviana_crayola_unixorl (ktext)
`
`Added the STAR test bus signals.
`
`#89 change 59670 edit on 2002/10/28 by dclifton@dclifton_r400 (ktext)
`
`first cut as distributing resets
`
`#88 change 58336 edit on 2002/10/21 by bhankins@fl_bhankins r400win (ktext)
`
`stop clipperbusy from turning off too soon
`
`#87 change 57230 edit on 2002/10/15 by delifton@dclifton+400 (ktext)
`
`Moved st_indx and primtype from ram fifo into register fifo so early version could be
`used by polymode circuit. Created special controller to drive both ram and register
`based fifo. Routed early version of st_indx into regs block and routed back early
`versions of cull, polymode, and init state variables to update in syne with other prim
`data.
`Increased prim_fifo controller to use 8 deep ram since it's available.
`Lowered
`state variable input delay on geom_prep block.
`
`#86 change 56587 edit on 2002/10/11 by dclifton@dclifton_r400 (ktext)
`
`Routed sclk_reg and sclk_ag into pa_ag.
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`#85 change 56421 edit on 2002/10/10 by delifton@delifton_r400 (ktext)
`
`Routed sclkreg into pa_clipper and pa_sxifecg for state storage blocks.
`
`#84 change 56410 edit on 2002/10/10 by delifton@dclifton_r400 (ktext)
`
`Routed sclkreg to pa_su_regs block
`
`#83 change 56393 edit on 2002/10/10 by dcelifton@dclifton_r400 (ktext)
`
`Routed sclkreg into pa_vteregs
`
`#82 change 56076 edit on 2002/10/09 by dclifton@dclifton_r400 (ktext)
`
`Connected registered pa_srst to internal blocks instead of srst input.
`
`#81 change 56066 edit on 2002/10/09 by dclifton@dclifton_r400 (ktext)
`
`Added VGTPAwakeupcall and PASCwakeupcall clock enable signals
`
`#80 change 55645 edit on 2002/10/07 by dclifton@dclifton_r400 (ktext)
`
`Changed name of power management signal
`
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`//depot/r400/devel/partslib/src/gfx/tp/tp.tree
`#51 change 95000 edit on 2003/04/10 by tien@tien_r400devel_marlboro (ktext)
`
`Some LEDA cleanup
`Fix for unnormed coords
`
`Got FMT_32 3232 32 FLOAT working for one test :-)
`
`#50 change 91104 edit on 2003/03/19 by tien@tienr400develmarlboro (ktext)
`
`Fixed cmask for hicolor fast floats
`
`Added test ports
`
`#49 change 87694 edit on 2003/02/28 by nkociuk@nkociuk1400linuxmarl
`
`(ktext)
`
`change to allow sclktpperf to br forced off (except during register read/write
`activity)
`
`#48 change 87102 edit on 2003/02/26 by tien@tien_r400_devel_marlboro (ktext)
`
`Width mismatch
`
`#47 change 87093 edit on 2003/02/26 by tien@tien_r400_devel_marlboro (ktext)
`
`Fixed a port issue in tp
`Added max clamp in sptp_norm32
`Fixed max/min clamp in sp_tp_norm32
`Fixed sens list issue in sp_tp_norm32
`
`#46 change 85630 edit on 2003/02/20
`
`by
`
`smburu@smburu_r400linuxmarlboro (ktext)
`
`Some STAR_cmdscout hook-up changes.
`
`#45 change $4996 edit on 2003/02/18
`
`by
`
`smburu@smburu_r400sunmarlboro (ktext)
`
`Hook-ed up clrerr as should be.
`
`#44 change 84979 edit on 2003/02/18
`
`by
`
`smburu@smburu_r400sunmarlboro (ktext)
`
`Some changes to STAR_emdscout hook-up.
`
`#43 change 82833 edit on 2003/02/07
`
`by
`
`nkociuk@nkociuk+400linuxmarl
`
`(ktext)
`
`bring in rts to perfmon_wrapper
`
`#42 change 82175 edit on 2003/02/05
`
`by
`
`tien@tienr400develmarlboro (ktext)
`
`Fixed recen
`Removed fusebux
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`#41
`
`change 81887 edit on 2003/02/04 by nkociuk@nkociuk_r400_linux_marl
`
`(ktext)
`
`updated
`
`tpregisters, and matching tp.tree
`tp_cg,
`also connects up tp_perfmon_wrapper
`
`#40 change 80382 edit on 2003/01/29 by nkociuk@nkociuk_r400_linuxmarl
`
`(ktext)
`
`renamming tp_reg.v to tp_registers.v
`
`#39 change 70840 edit on 2002/12/12 by tien@tien_r400devel_marlboro (text)
`
`Added RBB_* readback ports to TP top level
`
`#38 change 69795 edit on 2002/12/09 by tien@tien_r400develmarlboro (text)
`
`Fixed bit widths in tpc_fifos
`Fixed logs in anise to add sign bit where needed
`
`#37 change 69099 edit on 2002/12/06 by tien@tienr400develmarlboro (text)
`
`Added STAR proc and fusebox
`
`#36 change 65627 edit on 2002/11/20 by tien@tienr400develmarlboro (text)
`
`Fixed LOD logic to match algorithm in spec
`
`change 64485 edit on 2002/11/15 by tien@tien_r400devel_marlboro (text)
`
`tp_tc_ fifo and tpc_state_fifo
`up control between tpc_aligner and TP_TC interface
`
`change 62504 edit on 2002/11/07 by desiree@desiree1400sunmarlboro (text)
`
` change 62169 edit on 2002/11/06 by tien@tien_r400devel_marlboro (text)
`
`#35
`
`Removed
`Cleaned
`
`#34
`
`Convert
`Initial
`
`#33
`
`to STAR
`RAMs
`checkin of STAR ctme and v files
`TP Makefile
`
`Updated
`STAR signals tied off and tp level to avoid new ports and chip.tree
`
`Candidate fix for border
`
`Candidate fix for tpc_rr_fifo overflow
`
`#32 change 55685 edit on 2002/10/07 by tien@tienr400develmarlboro (text)
`
`Fixes for clamping/mipmapping
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`//depot/r400/devel/partslib/src/gfix/pa/pa_ag.v
`#42 change 85363 edit on 2003/02/19 by delifton@delifton_r400 (ktext)
`
`Controlled writes to CIDO to prevent real time streams from corrupting non-real time
`state by writing state without initial cpy.
`
`#41 change 72494 edit on 2002/12/19 by delifton@dclifton_r400 (ktext)
`
`Fixed makefile to compile cot gate netlist.
`Added flush for writes to cl_enhance reg.
`Added daisy chain reads.
`Put state variable poiinter logic in pa_ag on hard reset.
`Put perfmon on hard reset.
`
`#40 change 70338 edit on 2002/12/11 by bhankins@fl_bhankins r400win (ktext)
`
`init function variable to remove synopsys warning
`
`#39 change 66692 edit on 2002/11/25 by bhankins@fl_bhankins_ r400win (ktext)
`
`Reduced the width of the clipper's pointsize memory to 25 bits, as well as the
`pointsize datapath within the clipper.
`
`#38 change 65236 edit on 2002/11/19 by delifton@decliftonr400 (ktext)
`
`added include “header.v"
`
`#37 change 65200 edit on 2002/11/19 by viviana@viviana_crayola_unix_orl
`
`(ktext)
`
`Added the pa_rf_stp (Virage processor),
`Scan IO and new Virage memories.
`
`the Test Controller and
`
`#36 change 62865 edit on 2002/11/08 by viviana@viviana_crayola_unixorl (ktext)
`
`Changed the STAR test buses for the pa_ag to get rid of the extra
`instantiations for the memories that should have been bit write memories.
`
`#35 change 62858 edit on 2002/11/08 by dclifton@dcliftonr400 (ktext)
`
`Changed stve and veoc_back rams to bit-enable write variety
`
`#34 change 61915 edit on 2002/11/06 by viviana@viviana_crayola_unixorl (ktext)
`
`Added another set of STAR_patch signals for the pntsz memory for the clipper.
`
`#33 change 61081 edit on 2002/11/01 by viviana@viviana_crayola_unixorl (ktext)
`
`Added the STAR test bus signals and wired up the hierarchy.
`
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`#32 change 60239 edit on 2002/10/30 by bhankins@fl_bhankins_ r400win (ktext)
`
`update for 4x clipper
`
`#31 change 56587 edit on 2002/10/11 by delifton@dclifton_r400
`
`(ktext)
`
`Routed sclkreg and sclk_ag into pa_ag.
`
`#30 change 55261 edit on 2002/10/04 by dcelifton@dclifton_1r400
`
`(ktext)
`
`Fixed a small
`
`leda error
`
`#29 change 54996 edit on 2002/10/03 by dclifton@dclifton_r400
`
`(ktext)
`
`Added register stage on rbiu inputs to eliminate timing violation.
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`//depot/r400/devel/partslib/src/gfx/pa/pa_ccgsxifsm.v
`#38 change 74916 edit on 2003/01/07 by bhankins@fl_bhankins r400_win (ktext)
`
`Increased sxrequestindx to seven bits to fix a bug that could occur when both even or
`both odd pipelines were disabled.
`
`#37 change 74660 edit on 2003/01/06 by bhankins@fl_bhankins r400_win
`
`Fix bug in sxifsm request side that shows up when disable_sp is non-zero.
`
`#36 change 72728 edit on 2002/12/20 by bhankins@fl_bhankins r400_win
`
`(ktext)
`
`(ktext)
`
`1. use sclk_ag to clock clipper registers that get reset when writes are done to
`pa_cl enhance register to ensure register is clocked.
`
`2, add some test logic for soft reset
`
`(for test only; commented out).
`
`3.
`
`removed reset from pa_cl enhance register
`
`#35 change 71769 edit on 2002/12/17 by bhankins@flbhankins r400win
`
`(ktext)
`
`1. update some non state-based perf signals to more closely match csim.
`
`2.
`
`remove some commented lines.
`
`#34 change 69061 edit on 2002/12/06 by bhankins@fl_bhankins r400_win
`
`(ktext)
`
`change wake up to use pasx_req_cnt
`
`#33 change 68842 edit on 2002/12/05 by bhankins@fl_bhankins r400_win
`
`(ktext)
`
`include write of sxpendingfifo
`
`#32 change 68717 edit on 2002/12/05 by bhankins@fl_bhankins r400win
`
`(ktext)
`
`add logic for pa to sx wake up call.
`
`commented out in pa.v
`
`#31 change 66586 edit on 2002/11/25 by bhankins@fl_bhankins r400_win
`
`rearrange pa_sxifecg debug bus
`
`#30 change 65467 edit on 2002/11/20 by bhankins@fl_bhankins r400_win
`
`leda warning fix
`
`#29 change 65466 edit on 2002/11/20 by bhankins@fl_bhankins r400_win
`
`(ktext)
`
`(ktext)
`
`(ktext)
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`bug fix for performance counter
`
`#28 change 65273 edit on 2002/11/19 by bhankins@fl_bhankins r400win (ktext)
`
`1. bug fix in nan kill flag
`
`2. add signals to debug busses
`
`#27 change 64364 edit on 2002/11/15 by bhankins@fl_bhankins r400win (ktext)
`
`add more to non-state based performance monitoring,
`
`including counter enable.
`
`#26 change 64031 edit on 2002/11/14 by bhankins@fl_bhankins r400_win (ktext)
`
`add non-state based performance monitoring signals to pa_sxifceg
`
`#25 change 63944 edit on 2002/11/14 by bhankins@fl_bhankins r400_win (ktext)
`
`mods to try and improve on timing.
`
`no functional changes.
`
`#24 change 63365 edit on 2002/11/12 by bhankins@fl_bhankins r400win (ktext)
`
`add pa_clipper and pa_sxifsm performance counter signals, and bring up to pa.v level
`for now.
`
`#23 change 63330 edit on 2002/11/12 by bhankins@fl_bhankins r400win (ktext)
`
`add debug bus to pa_sxifccg (clipperdebug3)
`
`#22 change 62982 edit on 2002/11/09 by bhankins@fl_bhankins r400_win (ktext)
`
`add a register to the output of the vgt_toccgenfifo to try to improve on timing.
`
`#21 change 62708 edit on 2002/11/08 by bhankins@fl_bhankins r400_win (ktext)
`
`removed debug bus from sxifcceg for now for a quick synthesis
`
`#20 change 62673 edit on 2002/11/08 by bhankins@fl_bhankins_ r400win (ktext)
`
`add debug bus for pa_sxifceg block
`
`#19 change 55858 edit on 2002/10/08 by dclifton@dclifton_r400 (ktext)
`
`LEDA errors fixed
`
`#18 change 55550 edit on 2002/10/07 by bhankins@fl_bhankins r400_win (ktext)
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`fixed some leda warnings
`
`#17 change 55536 edit on 2002/10/07 by delifton@deliftonr400 (ktext)
`
`Fixed sens. list in proc 610.
`
`Fixed a few more LHS, RHS width mismatches.
`
`#16 change 55426 edit on 2002/10/04 by delifton@dclifton_r400 (ktext)
`
`Fixed blocking transition errors in proc 600, 300, 480
`
`#15 change 55397 edit on 2002/10/04 by delifton@dclifton_r400 (ktext)
`
`Fixed leda errors associated with LHS and RHS bit sizes.
`
`#14 change 54783 edit on 2002/10/02 by bhankins@fl_bhankins r400win (ktext)
`
`try to improve on timing.
`
`no functional change.
`
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`//depot/r400/devel/partslib/src/gfx/pa/pa_sxifccg.v
`#38 change 74916 edit on 2003/01/07 by bhankins@fl_bhankins_ r400win (ktext)
`
`Increased sxrequestindx to seven bits to fix a bug that could occur when both even or
`both odd pipelines were disabled.
`
`#37 change 71769 edit on 2002/12/17 by bhankins@fl_bhankins r400win (ktext)
`
`1. update some non state-based perf signals to more closely match csim.
`
`2,
`
`remove some commented lines.
`
`#36 change 68717 edit on 2002/12/05 by bhankins@fl_bhankins r400win (ktext)
`
`add logic for pa to sx wake up call.
`
`commented out in pa.v
`
`#35 change 66591 edit on 2002/11/25 by bhankins@fl_bhankins_ r400win (ktext)
`
`debug bus fix
`
`#34 change 66586 edit on 2002/11/25 by bhankins@fl_bhankins r400_win (ktext)
`
`rearrange pa_sxifccg debug bus
`
`#33 change 66199 edit on 2002/11/22 by bhankins@fl_bhankins r400win (ktext)
`
`change state reg in pa_sxifccg so as not
`
`to support readback
`
`#32 change 65272 edit on 2002/11/19 by bhankins@fl_bhankins r400win (ktext)
`
`add signals to debug busses
`
`#31 change 65200 edit on 2002/11/19 by viviana@viviana_crayola_unix_orl
`
`(ktext)
`
`Added the pa_rfstp (Virage processor),
`Scan IO and new Virage memories.
`
`the Test Controller and
`
`#30 change 64639 edit on 2002/11/16 by bhankins@fl_bhankins r400_win (ktext)
`
`fix syntax error
`
`#29 change 64364 edit on 2002/11/15 by bhankins@fl_bhankins r400win (ktext)
`
`add more to non-state based performance monitoring,
`
`including counter enable.
`
`#28 change 64031 edit on 2002/11/14 by bhankins@fl_bhankins r400win (ktext)
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`add non-state based performance monitoring signals to pa_sxifecg
`
`#27 change 63365 edit on 2002/11/12 by bhankins@fl_bhankins r400win (ktext)
`
`add pa_clipper and pa_sxifsm performance counter signals, and bring up to pa.v level
`for now.
`
`#26 change 63330 edit on 2002/11/12 by bhankins@fl_bhankins r400_win (ktext)
`
`add debug bus to pa_sxifecg (clipper_debug3)
`
`#25 change 62724 edit on 2002/11/08 by bhankins@fl_bhankins r400win (ktext)
`
`removed debug bus signal for synthesis (for now)
`
`#24 change 62708 edit on 2002/11/08 by bhankins@fl_bhankins r400win (ktext)
`
`removed debug bus from sxifceg for now for a quick synthesis
`
`#23 change 62673 edit on 2002/11/08 by bhankins@fl_bhankins r400win (ktext)
`
`add debug bus for pa_sxifccg block
`
`#22 change 61081 edit on 2002/11/01 by viviana@viviana_crayola_unixorl (ktext)
`
`Added the STAR test bus signals and wired up the hierarchy.
`
`#21 change 56421 edit on 2002/10/10 by dclifton@dclifton_r400 (ktext)
`
`Routed sclk_reg into pa_clipper and pa_sxifecg for state storage blocks.
`
`#20 change 55340 edit on 2002/10/04 by bhankins@FLBHANKINSP4 (ktext)
`
`fix vertex fifo size definition
`
`#19 change 55305 edit on 2002/10/04 by bhankins@flbhankins r400win (ktext)
`
`put fifo dimensions in pa_clippkg.v
`
`#18 change 55244 edit on 2002/10/04 by bhankins@fl_bhankins r400win (ktext)
`
`replace ram-based fifos with register-based
`
`#17 change 55091 edit on 2002/10/03 by bhankins@flbhankins r400win (ktext)
`
`back out registered-fifo replacements due to simulation errors.
`
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`#16 change 55066 edit on 2002/10/03 by bhankins@fl_bhankins r400win (ktext)
`
`replace ram-based fifo with register-based fifo.
`
`no functional change.
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`//depot/r400/devel/partslib/src/gfix/sc/sc.v
`#143 change 91177 edit on 2003/03/20 by donaldl@fl_donaldl_p4 (ktext)
`
`Removed IOSC and IOSC_B partition scan input/output signals.
`
`#142 change 90807 edit on 2003/03/18 by donaldl@fl_donaldl_p4 (ktext)
`
`Added common test ports.
`
`#141 change 88830 edit on 2003/03/06 by donaldl@fl_donaldl_p4 (ktext)
`
`(ie. w_addr[2:0],
`Delayed by 1 clk some of RBIU inputs/outputs to state storage modules
`we, sel, cp, wdata[31:0], r_addr[2:0], re, r_data[31:0]).
`Done to reduce large fanout
`in post layout netlist.
`
`#140 change 87944 edit on 2003/03/02 by donaldl@fl_donaldl_p4 (ktext)
`
`Fanout of state variable indices to help post layout timing.
`
`#139 change 84488 edit on 2003/02/14 by rramsey@rramseycrayolalinuxorl (ktext)
`
`Add pixel-per-quad perfcounters to SC RTL
`
`#138 change 78237 edit on 2003/01/21 by kmeekins@kmeekins r400win (ktext)
`
`Cleaned up fifo interface.
`Removed unused signal.
`
`sc_qdpr_proc.v
`
`Changed waitforrl logic.
`
`#137 change 73878 edit on 2002/12/31 by donaldl@fl_donaldl_p4 (ktext)
`
`Make same sciter change of nxt_spinterfacefull to sc_biter. Need to also add
`interface signal sc_beopv from sc to sc_b.
`
`#136 change 73050 edit on 2002/12/21 by scamlin@scamlin_crayola_unixorl (ktext)
`
`updated sc_intercmdfifo depth to 28
`
`#135 change 71840 edit on 2002/12/17 by rramsey@RRAMSEYP4 r400win (ktext)
`
`Add PA_SC_FIFOSIZE to rbiu decode, state block
`Change sc_primfifo and sc_tilefifo to progdepth fifos
`
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`#134 change 69647 edit on 2002/12/09 by mmantor@FLmmantorLTr400win (ktext)
`
`added replicated qd0 and qdl hit signals to
`
`sc packer
`
`#133 change 69632 edit on 2002/12/09 by
`
`rramsey@RRAMSEYP4_r400_win (ktext)
`
`SC timing fixes
`
`Change sc_rbiu srst input to a registered version
`Split hier_masksum into two clks in sc_perf_cntl
`Register samplemask outputs in se_qdpr_proc
`Make g0/1hit output from qdprproc 5 bits to help with fanout
`
`#132 change 68882 edit on 2002/12/05 by donaldl@fl_donaldl_p4 (ktext)
`
`Reassigned primdata and quad data widths/definitions so lsbs line up sequentially with
`data going to sc_b.v.
`
`Change scbiterphase[2:0]
`
`to sebiterphase1lsb since only bit 0 is need in sc_b.v.
`
`#131 change 68725 edit on 2002/12/05 by
`
`mmantor@FLmmantorLT_r400_win (ktext)
`
`removed sc rc wake up since re is not using
`
`#130 change 68700 edit on 2002/12/05 by
`
`rramsey@RRAMSEYP4_r400_win (ktext)
`
`Fix some lint warnings for se rtl
`Cover iclk hole in busy cnt decrements from
`
`qdprproc
`
`#129 change 68079 edit on 2002/12/03 by
`
`scamlin@scamlin_crayola_unixorl (ktext)
`
`change itercmdfifo memory from 22 to 24 deep
`
`#128 change 67640 edit on 2002/11/29 by
`
`mmantor@FLmmantorLT_r400_win (ktext)
`
`moved “define USESC_B to header file so it
`
`is defined for every one
`
`#127 change 67412 edit on 2002/11/27 by
`
`grayc@chipregress orl (ktext)
`
`added define for scb
`
`#126 change 67351 edit on 2002/11/27 by
`
`donaldl@fl_donaldl_p4 (ktext)
`
`Added wake-up output signals going to SX's,
`
`SP's, SQ, and RC external blocks.
`
`#125 change 67284 edit on 2002/11/27 by
`
`donaldl@fl_donaldl_p4 (ktext)
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`Added delay chain and scan I/O to scb.v.
`
`Added fusebox to sc.v.
`
`#124 change 66994 edit on 2002/11/26 by viviana@viviana_crayola_linux_orl
`
`(ktext)
`
`Added the ati_delay block and two IO pins to the se and tbh_se.v.
`
`#123 change 66978 edit on 2002/11/26 by donaldl@fl_donaldl_p4 (ktext)
`
`Send sc_clk_en from sc.v to se_b.v for clock gating in sc_b.
`
`#122 change 66791 edit on 2002/11/25 by donaldl@fl_donaldlp4 (ktext)
`
`Initial split of sc into two blocks: sc.v and scb.v.
`
`The sc_b contains the sc_baryc blocks and any supporting logic.
`
`#121 change 66725 edit on 2002/11/25 by kmeekins@kmeekins r400_win (ktext)
`
`- Propigated the scpipeout_cntx0 signal to the output of the
`sc_iter (renamed it iterator_SP_cntx0).
`- Registered iteratorSP_cntx0 in the sc_interface_regs.
`
`#120 change 66519 edit on 2002/11/24 by grayc@graycr400win (ktext)
`
`changed top level signal name to PA_SC_wake_up_call
`
`#119 change 66087 edit on 2002/11/21 by kmeekins@kmeekins r400win (ktext)
`
`-connected new module I/O ports for use with trackers.
`
`sc_detailmask_accum.v
`
`- Created two new outputs to indicate when context
`1 thru 7 are in use. Used in the trackers.
`
`0 or context
`
`- Added a new SC to SX port indicating context
`
`0 usage for trackers.
`
`sc_interface_regs.v
`
`- Created two new registers for the new tracker ports to keep
`control signals alligned with their data.
`
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`#118 change 65916 edit on 2002/11/21 by viviana@viviana_crayola_unixorl (ktext)
`
`Connected SCrfrecen that was previously unconnected.
`
`#117 change 65685 edit on 2002/11/20 by viviana@viviana_crayola_unixorl (ktext)
`
`Connected the Virage memories reset to the sc_hard_srst.
`
`#116 change 65259 edit on 2002/11/19 by viviana@viviana_crayola_unixorl (ktext)
`
`Added more Test
`
`IO for the register file memories.
`
`#115 change 64540 edit on 2002/11/15 by viviana@viviana_crayola_unixorl (ktext)
`
`Added the Star Processor to the sc.v and all the Test Controller busses.
`
`#114 change 64321 edit on 2002/11/15 by mmantor@mmantorr400win (ktext)
`
`added debug port from the packer
`
`#113 change 64188 edit on 2002/11/14 by rramsey@RRAMSEYP4 r400win (ktext)
`
`Change comment for RTS bbfract default from Oxf to 0x0
`Hook scperfcntl to permanent sclk instead of sclk_sce
`Add iter freeze signal to scperf_cntl to filter out packer send rows during freeze
`Fix rbbm address decodes in sc_perfmon
`
`#112 change 63461 edit on 2002/11/12 by donaldl@fl_donaldl_p4 (ktext)
`
`Added debug bus for sc_qdpr_proc and sc_z_interp
`
`#111 change 63372 edit on 2002/11/12 by rramsey@RRAMSEYP4 r400win (ktext)
`
`Add debug connections for qpp (two selects)
`Change rts bbhfract default to 0x0 from Oxf
`Add three new perfmon selects
`
`#110 change 62922 edit on 2002/11/08 by donaldl@fl_donaldl_p4 (ktext)
`
`Added initial debug bus.
`
`#109 change 62852 edit on 2002/11/08 by viviana@viviana_crayola_unixorl (ktext)
`
`Corrected the size of the STAR_testbus going to the primfifo.
`
`#108 change 62779 edit on 2002/11/08 by viviana@viviana_crayolaunixorl (ktext)
`
`Changed the memories in the primfifo to 3 84x96 and one 84x80 due to the
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`
`new compiler's limitations. Added a STARpatch bus for the additional fifo.
`
`#107 change 61587 edit on 2002/11/05 by rramsey@RRAMSEYP4 r400win (ktext)
`
`Add sc_one_quad_per_clock logic to quad pair processor
`half rate)
`
`(allows us to detail-sample at
`
`RTL- adds a bit to se_hiz_cull_rslt_fifo
`
`#106 change 61436 edit on 2002/11/04 by mmantor@mmantorr400_win (ktext)
`
`added packer optimization with register hookup
`added sc bad pipe logic
`
`#105 change 61216 edit on 2002/11/02 by viviana@viviana_crayola_unixorl (ktext)
`
`Changed the instance names for the master clock instances and the rbbm interface
`instance.
`
`#104 change 61088 edit on 2002/11/01 by kmeekins@kmeekins r400_win (ktext)
`
`Added a second register level for reset.
`Created new reset signals for the usc instances requiring reset.
`
`#103 change 60665 edit on 2002/10/31 by rramsey@RRAMSEYP4 r400win (ktext)
`
`correct connection of eventid msb in sc and tb sc
`
`clean up ports in se_perf_cntl.v
`
`#102 change 60275 edit on 2002/10/30 by rramsey@RRAMSEYP4 r400win (ktext)
`
`Add pix suffix to the ROM pipe disable signals for the sc
`
`#101 change 60080 edit on 2002/10/29 by kmeekins@kmeekins r400win (ktext)
`
`Piped rt_valid through to the 3C_RC interface for dump file compare
`purposes only.
`
`#100 change 59915 edit on 2002/10/29 by rramsey@RRAMSEYP4 r400win (ktext)
`
`Add another
`
`(and hopefully the last) signal to the se performance monitor logic
`
`#99 change 59805 edit on 2002/10/28 by kmeekins@kmeekinsr400win (ktext)
`
`Makefile
`
`Fixed sc_perfmon target
`
`sCc.V
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`ATI Ex. 2098
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