2 Bow |
`orp ® Fe,
`.@ &@ FE Se,
`.#ae © Boe,
`
`se BBs aaa
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`"Sag
`on gy
`
`VirtuaLogic 3.5
`User Guide
`
`IKOS Technical Publications
`
`Part Number 6000290-0001
`
`Last Revision 25-Apr-2001
`
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`Important Notice
`
`This document 1s for informational and instructional purpeses. IKOS Systems,Inc. reserves the right to
`make changes in the specifications and other information contamed in this publication without prior notice.
`and the reader should, in all cases, consult IKOS Svstems, Inc. to determine whether anv changes have
`been made.
`
`The terms and conditions governing the sale and licensing of IKOS Systems. Inc. products are set forth in
`the written contracts between IKOS Systems, Inc. and its customers. No representation or other affirmation
`of fact containedin this publication shall be deemed to be a warrant orgive rise to anv liability to IKOS
`Systems, Inc. whatsoever.
`
`IKOS Systems. Inc. MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL,
`INCLUDING, BUT NOT LIMITED TO. THE IMPLIED WARRANTIES OF MERCHANTABILITY
`AND FITNESS FOR A PARTICULAR PURPOSE.
`
`IKOS Systems, Inc. SHALL NOT BE LIABLE FOR ERRORS CONTAINED HEREIN OR FROM
`INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER
`(INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS
`PUBLICATION OR THE INFORMATION CONTAINEDIN IT, EVEN IF [KOS Systems, Inc. HAS
`BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
`
`This document contains proprictary information. In addition, the software programs and hardware
`described in this document are confidential and proprictarypreducts of IKOS Systems, Inc. and its
`licensors. NO PART OF THIS DOCUMENT MAY BE REPRODUCED, STORED IN A RETRIEVAL
`SYSTEM OR TRANSMITTED IN ANY FORM OR BY ANY MEANS, ELECTRONIC,
`MECHANICAL, PHOTOCOPY, RECORDING OR OTHERWISE WITHOUT THE PRIOR WRITTEN
`CONSENT OF IKOS Svstems. Inc. Each licensed user is allowed to print up to [0 copies of this material
`for intracompanyuse only without infringing this copyright. Please contact IKOS Systems, Inc., for
`permission to print additional copies.
`
`IKOS"is a registered trademark of IKOS Swstems, Inc.
`VHDLAccelerator™ is a registered trademark of IKOS Systems, Inc.
`Virsim™ is a registered trademark of Summit Systems. Inc.
`VirtuaLogic™ is a trademark of IKOS Systems, Inc.
`VLE-3M©isatrademark of IKOS Systems, Inc.
`Rt
`VStation-3M is a trademark of [KOS Swstems,Ine.
`¥Station-12M"”
`is a trademark of IKOS Systems, Inc
`
`SimMatrix” is a registered trademark of Preeedence, Inc.
`Verilog-XL~ is a registered trademark of Cadence Design Systems. Inc,
`Sun * is a registered trademark of Sun Microsystems.
`
`All other brands or products are trademarksof their respective companies and should be treated as such.
`
`Copyright © 2001 by IKOS Systems, Inc.
`
`All rights reserved.
`
`Written inthe U.S.A
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`

`reaeB eo ay
`28 Fhe.
`~89R0 ®GRaa
`son OBacas
`
`"1KOS
`
`Table of Contents
`
`
`
`Table of Contents . 2... 00.0. ee ee ee 3
`
`List of Figures 2. 0 ee ee ee ew eee ee we 2d
`
`Listof Tables... 2... 2 ee es 25
`
`Introduction 2... ee ee ee 27
`
`Overview22
`
`|we 8
`VirtuaLogic’s technology advantages 6
`RTL for VStation.
`2
`2
`2 2) ee BB
`
`Transaction Interface Portal
`
`=
`
`2
`
`2
`
`22 88
`
`VStaton Components... 2...) BI
`
`Hardware...2 BI
`
`IDS and HP Logic Analwzer,
`
`2|
`
`Targetinterfaces
`
`2 0.) eB
`
`Targctsysttem 2 2.) ee. BB
`
`Software
`
`20ee 88
`
`RTL Compiler
`
`2
`
`7
`
`22 84
`
`2 2) Bt
`VirtiaLogic Compiler.
`Timing resynihesis 2. kw ee 8
`Interconnect resynthesis.
`2. 2... Lo.
`Coe ee ee.
`BA
`
`Backend Place and Route manager
`
`7 ww ee BS
`
`Virtual probe analysis tools .
`
`Diagnostics
`
`Last Revision 25-Apr-2001
`
`VirtuaLagic 3.5 User Guide
`
`35
`
`35
`
`3
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`Table of Contents
`
`Using the Graphical User Interface (GUI... ........4.
`
`tee ee 37
`
`Overview.
`
`Environment setup .
`VLEsetup.
`
`RTLC setup .
`
`Invoking the VirtuaLogicsoftware .
`
`Configurations .
`Config_name
`
`Starting evl on a pre-existing configuration .
`
`Building a single-ASIC configuration .
`Software executables.
`
`Starting the graphical compiler interface .
`Problems
`
`Disk space requirements.
`
`CPU requirements
`
`Navigating the GVL interface
`
`GVL windowlavout.
`Screen clements.
`
`Drag and Drop .
`
`Multiple selection.
`
`Scrolling text windows.
`
`Directory and file browsers .
`“ buttons,
`
`Optional textfields
`
`Commonparts of the interface .
`Buttonbar .
`
`Tab bar .
`
`Drop down menu .
`VirtualBrowser .
`Path .
`Modules
`Nets .
`
`37
`
`37
`
`37
`
`38
`
`38
`
`39
`39
`
`39
`
`40
`
`40
`
`Al
`
`42
`
`42
`
`43
`
`Laao>oS
`
`Last Revision 25-Apr-2001
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`Table of Contents
`
`Terminals .
`Find .
`Search |
`
`Showpath
`Additional (catures
`
`Regular expression syntax.
`Ambiguity
`Loe
`Reguiar expression cxample
`
`Clipboard .
`Clear
`Insert file.
`Write file.
`
`Append file
`Dismiss
`
`Reload
`
`Undo.
`
`Quit
`Errors window .
`OK
`
`Visil(next)
`Help .
`ShowLog .
`Save Errors
`
`File Browser .
`Path .
`Dircetorics
`Files .
`OK
`Filter
`Cancel.
`
`Optional text ficlds
`
`UAununuaununununaaarawwawaweeOOHROOee
`
`62
`62
`62
`62
`
`Design Import... 1. ee ee es
`
`rr 65
`
`Overview .
`
`RTL Verilog flow
`Verilog RTL user Mow
`
`RTL VHDL flow .
`
`Last Revision 25-Apr-2001
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`VirtuaLagic 3.5 User Guide
`
`6ta
`
`65
`
`67
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`67
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`Table of Contents
`
`VHDL RTLuser flow
`
`Design import
`
`.
`
`Netlist import
`Nethists .
`
`Entering pathnamics
`Netlists requirements .
`Netlist defines
`
`Inputnetlist type
`Root module .
`
`Technology mapping .
`
`Technology
`Bonded out cores .
`
`Instance removal example .
`
`Technolog»files
`
`Memoryspecification .
`Memory parameters .
`Memory name
`Contents file.
`
`Le
`
`Instance-Specific contents file
`Write enable sense
`
`Memorics .
`Showmemorics
`
`toe
`
`Defining memerics with uctlist prototypes.
`Defining memorics without netlist prototypes.
`
`MemoryI/O terminals .
`Ports .
`Vectors .
`Scalar
`
`.
`
`Output enable scnse
`
`Add memory .
`
`Delete memory.
`
`Import memorfile.
`Memoryfiles
`
`Check memory.
`
`Memorycxample .
`Adding the memory .
`
`Last Revision 25-Apr-2001
`
`VirtuaLagic 3.5 User Guide
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`Table of Contents
`
`Adding thc porlinformation ©. ee ee 8G
`Adding the memory parameters information . 2... 2... eB
`
`Timing specification © 6... ee BB
`Clockdomain 2... BY
`
`Building the waveforms ©ee OD
`Multiple domams
`©
`0 2 ee GT
`
`Datasignals ©2 ee OD
`Rising2 9B
`Rising edge synchronous inputs.
`2 2... ee
`Falling edge synchronous inpulg. 2... ee
`Bothedgc svnchronousimpulgs. 6 eG
`Rising edge synchronous outputs |. ee
`Falling edge synchronous cuiputs ©. ee ee OB
`Bothedge synchronous outputs. | ee
`
`Asynchronous inputs. 2...) ee LOG
`Asynchronous preset and reset signals oss.
`Loe
`woe ee eee. LOO
`Asynchronous dalasignals
`2 0 ee LOT
`
`Unconnected inputs and outputs. 2.2 OT
`Output clocks on the targelsyslem . ee LOR
`Inputs derived fromoutputs
`2 6. ee LOR
`Feedthrough signals
`2
`2 2) 2. ee ee. 103
`Feedthroughs and verify simulation 5 ee LS
`Bidireclional signals 2. eee ee ee. L0G
`
`2 0) ee LOE
`2.
`2
`2
`2.
`Design /Oterminals.
`Instuctions6 ee. LOE
`
`Adddomam 2...) 2 ee OF
`
`Addeclockk 2
`
`22 e107
`
`Add clocked datasignal
`
`2
`
`0
`
`22 «107
`
`Add asynchronous datasienal.. 2. 2. ee LF
`
`Tmperttiming 6 eee EOF
`Clock files
`2
`20 LOB
`
`Gate counting
`
`2we ey LOR
`
`Siomalsoe ee ee ee ee LOY
`
`Overview.
`
`2
`
`00 to Coe ee ee. LOD
`
`Signal windows pane. 6ee eee LT
`
`Auto-compiled/not compiled. ©.
`
`2 2. 0 ee HD
`
`Last Revision 25-Apr-2001
`
`VirtuaLagic 3.5 User Guide
`
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`Table of Contents
`
`Delete
`
`Add
`
`Write virsim configuration
`
`Signal groups pane .
`
`Group types.
`Add
`
`Delcte
`
`Cheek
`
`Import probes
`
`Signals pane.
`
`Compiler .......
`
`Overview .
`
`RTL Compile
`
`RTL Compiler flow .
`Input
`.
`Output
`Log...
`Messages -
`Incomplete sensitivity lists .
`Undefined function/task outputs
`Multiple drivers
`Four-siate reads -
`
`Gate strengths and delavs .
`Clock variable data.
`
`Function retum null.
`
`Report Files
`
`Primary options.
`Optimization level.
`RTLsource debug .
`
`Simulation errors (Allow).
`
`Module specific options
`RTLC additional options .
`
`RTLC troubleshooting .
`RTL messages
`.
`
`VLE/VSYN Compile .
`
`. 112
`
`. 112
`
`J 112
`
`_ 113
`
`14
`
`_ 11?
`
`_ 118
`
`119
`119
`_ 120
`126
`122
`127
`_ 129
`_ 136
`131
`
`_ 132
`
`133
`
`133
`134
`
`tl
`142
`12
`
`143
`
`143
`
`. 144
`
`ua
`145
`
`. 146
`
`Last Revision 25-Apr-2001
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`Table of Contents
`
`Target hardware pane we LAG
`Emulation plafferm 2. 2) 2. ee. L4G
`Emulaterboards
`2 2.) 2) 2 ee L4G
`
`Slorage ee LAG
`
`2 ee ee LAP
`2
`Compiler configuration pane
`100% Visibility.
`20 LAP
`
`100% Visibility cable
`
`2
`
`0 2. ee TAB
`
`100% Visibility benefits 2. ee ee TAB
`
`100% Visibility costs2 LAD
`
`oo. Se LAD
`2 2 oo.
`100% Visibility restrictions =
`Conditional capturewe ee FG
`
`Partition filepane ) | 2) ESO
`
`Placement filepane 2
`
`2 2)2 LSD
`
`2 0. AST
`2.
`Terminal constraintfile pane
`Compileroptions pane... ee ST
`
`Improved emulation performance.
`
`©
`
`2 2.
`
`2 ee ee «LB
`
`No-Flowsformodeling,
`
`2 0. 2 ee
`
`No-Flowstocompileadesigen.
`
`2. 2.) BP
`
`2 2. |. a
`No-flows to improve emulation speed.
`Special na-fow semantics for bidirectional top-levelWOs
`Visibility for bidirectional [/Os with no-flows .
`
`183
`. | id
`134
`
`2 0.)De ee ESS
`Using No-Flows
`No-Flows on Buses.
`2| ey LG
`
`No-Fiows in Combinational Loops... 0. 2 ee 1G
`No-Flow atoutputoflaiches ©
`2
`2 2... 1G
`Nettie-offs
`2 2 ee ee LG
`
`Designs with multiple asvnchronous clocks.
`
`. _ oo. ASF
`
`Script driven activities © 2) ee. LS?
`Scrip driven generation of virlualized model 2) «EP
`Seripldrivendesigncompilation
`2. 2. 2... eee LB
`Script driven PlaccandRowte 2. 2 ee LSB
`viecommands
`2 0) LSB
`
`VRO oo.
`
`oo. ee
`
`2) De ee LEY
`2 6)
`vie. browse_constants.
`Incorrect net valuc inthe circuit | ee LY
`
`Design removal during second dead logic elimination .
`
`.
`
`2.
`
`.
`
`2. 2... LSD
`
`Running repeat configurations.
`
`©
`
`2 2... ee LEO
`
`Last Revision 25-Apr-2001
`
`VirtuaLagic 3.5 User Guide
`
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`Table of Contents
`
`Vprobe batch-mode
`VRUN baich-mode
`
`Creating a new configuration database
`Sugpestions for repeat configurations.
`Configuration input files
`Runtimestate read/init/force.
`
`Wavs to improve compile time .
`Front End Compile(vlc .compile)
`Place and Route (vie .vtask)
`VLE messages
`.
`
`FPGA Compile.
`Machines
`.
`Remote machine resources .
`
`All known hosts
`
`Niceness
`
`Lo
`
`FPGA compile tasks.
`Resct host list Ce
`
`Stopping FPGA compile during compilation
`
`Run FPGA compilation from the command line .
`
`Task management.
`vtask commands
`
`Hungjobs .
`vtask commiand.
`
`FPGA messages
`
`Control
`
`.
`
`Reports .
`
`Generate VSM.
`
`Virtualized Simulation Medel
`
`VSMlimitations
`
`Preserving design hicrarchy .
`
`Generating a VSM
`
`.
`Simulating a VSM.
`Step |: Simulate the input netlist
`.
`Step 2: Prepare the lesibench -
`Step 3: Resimulate the modified Testbench .
`Step 4: Simulate the VSM _.
`
`Last Revision 25-Apr-2001
`
`VirtuaLagic 3.5 User Guide
`
`. 60
`. 16]
`. 162
`. 163
`. 163
`
`. 164
`
`. 166
`. 166
`. 166
`. 167
`
`. 167
`
`. 168
`. 169
`_ 170
`
`J Ld
`
`_ 17
`
`. 172
`_ 172
`
`_ 173
`
`_ 173
`
`_ 173
`
`_ 173
`
`. 174
`_ 174
`
`_ 175
`
`LF?
`
`177
`
`_ LF?
`
`_ 178
`
`_ 178
`
`_ U7
`
`_ 78
`_ 179
`179
`. 180
`. 180
`
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`Table of Contents
`
`Resolving simulation scenarios.
`
`.
`
`2 2. 2) ee. ERO
`
`2ee BO
`Initializing the design
`Timeseale issues ee ABT
`
`Inputtiming issues ow eee EBT
`
`Clock ordering and period issues... eee LB
`Veclorcaptrre |we 1B
`Example 2.0. 2 ee ee. 183
`
`VSMsummarm. 2). ee LBA
`
`Incremental probe compile 2. ee ee LBA
`FPGA compile = = oo.
`oo. Se BA
`
`Statcompile.
`
`2 2.)2 ee LBS
`
`Interrupt.
`
`©
`
`22 ee EBS
`
`LOG pane. 2) ee EBS
`
`Multi Module Compile (MMC1) . 0.0... 0.0 ee te ee ee ee ee BF
`
`Overview.
`
`20ee RF
`
`Userinput.
`
`2
`
`22 188
`
`File structure.
`
`©
`
`2
`
`22 LBD
`
`Overview of MMC phasesandflows 2...) 8D
`
`Manual box partitioning 2 2. 2. ee LOG
`
`02 ee ESO
`2
`MMC phases.
`Toplevelanalysis .
`2
`2
`2 2 ee 19D
`Localamalysis
`22 ee OT
`Global resource allocation © 2 eee. TT
`
`6 0. ee ee AGT
`2
`Localcompile
`MMC flows 2 0 7 7 oo.
`oo. So 192
`
`How toinvokethe MMC compiler.
`
`22.)
`
`.. 2... 2... ee. EF
`MMC targetcommands
`Initiaicompile 2.) EF
`Incremental compile 2
`2 2, Loe
`woe ee eee LS
`
`Procedure for compiling mixed architecture multi-box configuration.
`
`©
`
`.
`
`2 2... . 196
`
`New vsyn parameters used by the mmc driver
`(forthe advanced user)
`2 ww). 198
`
`Required vsyn arguments (forthe advanced user).
`
`2
`
`0
`
`2 2. 0.2
`
`Last Revision 25-Apr-2001
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`Table of Contents
`
`Fileformats.
`
`2 2. 2.
`
`22 198
`
`virnw.resourees file2 188
`
`vmw.changes file.
`
`2 2) 200
`
`Visibility 22. 200
`
`© 2.7 OT
`MMC restrictions.
`MMC circuttrestrictions:.
`2
`2
`2 0 ee 201
`
`MMC sub-module topology restrictions:
`
`.
`
`2.
`
`2. 2... ee 2
`
`Triggers... ee ee ee ee ee et we ee ee 2S
`
`Overview 2
`
`60 208
`
`Compiled signal windows pane.
`
`© 2.) ee 204
`
`Compiled signal groups pane. ©.) 20S
`
`22 ee 205
`Trigger pane.
`Openfile oo.
`oo. Se 2S
`Wrtefile.
`22 Lo. ee ee ee LOG
`Showerrors.,
`20. 1 ee. 206
`Addstae.,
`20. 20
`Adddomain=. 208
`Addalldomain..
`© 2.
`2
`2 2 ee. 2OR
`Commer. ee. 208
`Timers ee 2NG
`Location
`2 0.ee 210
`
`Trigger diagram pane... ee ee BT
`
`Triggering capabilities
`
`2
`
`0 2. eB
`
`Steps toassembling ausefultriggser.
`
`2 0 Bd
`
`Anatomyofthe triggersvstom| aT?
`“Triggerable Signals” we) ee 2TD
`Logicreduction.
`© 6). 212
`Programmable state machine = | oo.
`oo. Se 2B
`Coumlersandtimers
`2.
`2 2. 2. ee. Lo
`Soe eee ee 21d
`
`Trigger description. ee BTS
`
`Anatomy ofatngecrdescription. 2. 2... BS
`Timerdeclarations 2... ee BIS
`
`(Gencral-purpese) Counter declarations
`
`2
`
`2 |.
`
`Lol.
`
`Soe ee ee ee 2G
`
`Last Revision 25-Apr-2001
`
`VirtuaLagic 3.5 User Guide
`
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`

`Table of Contents
`
`Domain declarations.
`Slate declarations.
`
`Location assignment
`
`.
`
`Tngger compilation .
`Termcollapsing
`Termsharing
`Trigger expressionslimitations
`
`Useful recommendations
`
`Summary of thgger concepts and overall syntax
`
`Understanding expression evaluation with respect to domains and clock cdges .
`Basics
`Default domains and clocks
`
`Explicit domains
`Explicit clock edges
`Cross-demain evaluation
`
`Understanding overall syntax
`
`Examples .
`- Matching a given value
`Example |
`Example 2 - Matching a condition N times (Not necessarily N contiguous times)
`Example 3 - Matching a condition N contiguous times .
`Example 4 - Wailing for N clock ticks
`Example 3 - Tnggering statement occurring normally .
`Example 6 - Controlling storage ina trigger
`Example 7 - Controlling storage withina statc according to the valuc of an cxpression
`Example 8 - Repeating a paltern N times ,
`Example 9 - Specif¥ing an inilial state other than the first slate .
`Example 10 - Triggering after a given period ofno progress .
`Example 11 - Matching an expression exactly N contiguous times
`Example 12 (Advanced) - Iilustraling various triggcring [catures
`Example 13 (Advanced) - Illustrating use of various counters
`
` -
`
`. 216
`.217
`L219
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`. 220
`. 220
`. 220
`. 221
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`. 221
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`. 222
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`_ 222
`. 222
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`. 223
`_ 223
`
`. 224
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`. 225
`. 225
`. 225
`. 225
`. 226
`. 226
`. 226
`. 226
`_ 227
`. 227
`. 228
`. 228
`. 230
`
`Emulation, .. 0.0 eee ee te tt te ee ee te ete te ee ee eed
`
`Overview .
`
`Emulator control pane.
`
`Sctup.
`Emulater
`
`.
`
`Logic analyzer
`
`.
`
`Last Revision 25-Apr-2001
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`VirtuaLagic 3.5 User Guide
`
`helad laa
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`cer)
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`hebefutoOtn
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`Table of Contents
`
`Virsim/¥re
`
`Conncct.
`
`Load design .
`Enable 1/Os
`
`Emulation speed
`Functional test
`
`.
`
`-
`
`Functional test purpose.
`Vectors .
`
`Reload memory.
`
`Poke memon
`
`Upload memory.
`
`Interrupt.
`User bits
`
`Conncct analyzer
`Window
`
`.
`
`Load tigger .
`
`Upload waveform.
`
`100% Visibility.
`Emulation status
`
`Clock relationships
`
`Multiple domain designs as a single domain
`Design emulation speed cxample .
`
`Resetting the emulator target system
`
`Trigger
`
`Waveform traces .
`
`Emulator log.
`
`Virsim control window .
`
`Virsim hicrarchy
`Virsim waveform .
`
`Virsim register .
`Virsim source
`
`Virsim logic .
`
`236
`
`. 236
`
`. 237
`237
`
`238
`238
`
`239
`239
`
`. 240
`
`. 240
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`241
`
`241
`. 24]
`
`. 242
`. 242
`
`_ 242
`
`243
`
`. 243
`. 244
`
`. 245
`
`. 246
`246
`
`. 248
`
`_ 248
`
`. 248
`
`249
`
`. 249
`
`. 249
`. 249
`
`. 249
`. 230
`
`. 250
`
`Compiler Options Reference Guide... ..........-....-.-- 251
`
`Last Revision 25-Apr-2001
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`Table of Contents
`
`Overview .
`
`RTLC Additional Opiions .
`
`Design input switches.
`
`Vonlog .
`VHBL
`
`Languawe recognition switches.
`
`Venlog .
`-sy nth_prefix
`-chable_case_pragmas
`-compile_celldefines .
`VHBL
`
`-max_recur_limit
`-preservc_namc_case .
`
`-compile-vhdl-inits
`
`-gndhangingterminals
`
`Outputfile switches.
`-out_dir
`-out_file
`-loefile
`-report_file
`carcarepfile
`
`2 2...
`
`Directorics NM/, NET/. INCR/.
`
`Message control switches -
`
`Disable/limit messages .
`“suppress.
`-mMax_crror_counl
`-max_loop_cnt.
`.
`-max_mesgcount .
`Allow/Disallow Sim Errors
`
`.
`
`-allow_4ST
`-allow_4ST_for_mod
`-allowGSD .
`-allow_GSD_for_mod
`-allow_ISL
`-allow_ISL_for_mod .
`-allowMDR
`-allow_MDR_for_mod .
`
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`. 259
`. 239
`. 260
`. 260
`
`. 260
`. 260
`_ 26]
`. 26]
`. 261
`. 261
`_ 262
`. 262
`. 262
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`Table of Contents
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`-allow_UFO .
`-allow_UFO_for_mod
`-disallow_4ST_for_mod
`-disallowyGSDformod
`-disallow_ISL_for_mod .
`-disallow_MDR_for_mod .
`.
`.
`-disallow UFO_formod 2...
`-cnableBHV_messages (RTL errors) .
`
`Selective compilation switches.
`-import
`.
`-noblack_box
`-force_module
`-foree_all
`.
`-ignorenonnlgen.
`
`Debug and preserve switches.
`-debug .
`-debug_module .
`-dont_debugmodule .
`“preserve.
`-preserve_moduic .
`-dont_preserve_medule .
`
`Optimization switches.
`~lut_map
`-optlevel .
`-opt_limcoutlimit
`-res_share .
`
`Compiler Directives
`
`Disable compilation of regions-
`
`VHBL Built-in Pragmas
`
`VLE Compiler Options .
`
`Capacity control arguments .
`-Mm .
`-Mimfanout
`
`Partition control parameters .
`-CUc
`CU.
`-FPi
`.
`-PUi
`.
`
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`. 263
`. 263
`. 263
`. 263
`. 264
`. 264
`. 264
`
`. 264
`
`. 264
`. 265
`. 265
`. 265
`. 266
`
`. 266
`
`. 266
`. 266
`. 267
`. 267
`. 267
`. 267
`
`. 268
`
`. 268
`. 269
`. 269
`. 269
`
`270
`
`_ 270
`
`. 270
`
`. 27)
`
`. 276
`. 276
`276
`
`_ 277
`_277
`278
`279
`. 280
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`Table of Contents
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`Database file suppression switches 2 ee ABT
`ewritevpd 22 BRI
`SNOVIO BRT
`orm ee, BET
`nodb ee BET
`
`Analysis/Transformation control. 6. 2. ee 2B
`“LBA. ee BRP
`
`OS 2RS
`-NoSyneQS 2.
`0
`2 wn Loe
`Coe ee ee BRA
`-NCH oo oo. BRA
`NFR, BBE
`NAMee BRI
`
`TNH we 290
`Se BOP
`re BOP
`-NoStfi
`22 BOS
`NOXOT
`20 295
`MOXCT 2 ee 295
`TOXFT
`20 ee 2S
`SMOXTAT2 285
`NMOXSAT 20 298
`OXTAT 2 0 ee BOE
`*XTAT2 ee BOG
`“SDPN 2we BOF
`
`2 0.) ee BOF
`2.
`2
`-fife_refold_portlimit
`-toclkopt| ee BOB
`eclkoptee BOB
`XCrossDonmuinlO© ee LOG
`-MFTL 2 WD LOS
`-noclockblocks
`oo.
`oo. Se BOD
`
`2 2. ww ee ee OT
`Control of output simulation models
`Vboeow 02 BOT
`hn ee. SOT
`SD eee ee . SOT
`wxID ee BOP
`VO B02
`svhdlout2 308
`
`2 0.2. BB
`Misecllancous
`Ve B08
`
`Qe. 303
`
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`VS. 304
`WOO oo oo. Se BOF
`We. BOF
`TersclOO ee ST
`-TerseProbe 2), ee 305
`
`
`
`-Dump 2 2.ee B05
`
`2 2. ee ee BOB
`Arguments notsetmanually.
`cLib BOR
`DB ee, BOB
`SNbO ee ee BOB
`NPB ee BOG
`Root.
`0 6 ee BOD
`Oko2.. BOY
`-Mem ww BOS
`-Probelnwe HOD
`-ProbeWindows
`2 0)ee BID
`-ProbeCard 2 oo.
`oo. Se BID
`-ProbeCore
`2
`2 2) Lo. ee ee ee BIO
`
`-ProbeMap 6. ee SG
`-ProbeDB 2 ww eee TT
`-IncProbe2 BIT
`-MultiAsic
`2
`6
`22 ee ee BT
`Pod ee ST
`
`sarecty ee B12
`elarectfile© ee BID
`esysparkwe B12
`eammpal ee ee BD
`Me.ee B12
`
`ememmap 22 BIB
`define 2 ee BIB
`
`6 2. ee ee . BIB
`-definesfile.
`eoond
`2we. BIB
`Th ee 314
`Mo... BIA
`AD ee ee B14
`MO0 ee 2 B14
`
`crypdwe 314
`POO ee BIS
`rr Lo. See eee BIS
`Pro.
`22 Lo.
`See ee ee. BIG
`PRO. ee B18
`
`Compiler options listed by category.
`
`2 2 BF
`
`VirtuaLagic 3.5 User Guide
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`vlecommands. 2...) ee BB
`
`Veee BIB
`
`rilLcompile 6. 0 ee BID
`rlcompileviask
`2
`2 2.) ee. BID
`vette ee. BID
`compile
`2 2.) ee 520
`A FAO
`
`Coe ee ee BBY
`2 wn Loe
`pprclean
`browse oo.
`oo. Se BBO
`
`wptabe2 SI
`TESIM ee ee ST
`frBI
`
`viask commands . 2... RBI
`
`add2 ee BT
`OMOVE| 3B
`mewlist2 322
`nee oo.
`oo. So BBD
`stauS Lo
`Loe ee ee . 328
`Oxi ee 323
`
`Mit B28
`help .
`3
`
`Syntax, Semantics, and Reference Library ................. 325
`
`Overview.
`
`20 BBS
`
`VirtuaLogic structural verilog subset
`
`2
`
`2 2 825
`
`Verilog identifiers,
`
`2
`
`0
`
`22, BBE
`
`2 2. 2 Lo.
`Module definitionsyntax 2
`Parameters.
`© 2. 2. en Lo
`
`tee ee BBG
`Soe ee ee . 326
`
`Example
`
`2 0)0 BF
`
`Simple assignments 2
`
`22 BDF
`
`Compiler directives
`
`2
`
`2 2. ee BF
`
`Unsupported verilog constructs.)we BBB
`
`Memory specification.
`
`©
`
`2 2)2 329
`
`2 ee B29
`Textualsvntax 2 6.
`Memorattributes.
`2 0.) BD
`Torminalbindings . 00... 0 ee aD
`
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`Table of Contents
`
`Semantics .
`
`Timing specification
`
`Syntax
`Semantics .
`
`Probe list format
`
`Textual syntax.
`
`VirtuaLogic reference library
`
`RTL Debug using the GUI... 2.2.22. 2 Le -
`
`ee ee eee 339
`
`Overview .
`
`RTLC debug capabilities
`Source debug window
`Limitations
`
`Graphical path browsing.
`Pruning
`Wavclonn viewer .
`
`Logic viewer .
`
`Trouble-shooting Guide. .............-.-
`
`re 351
`
`Overview .
`
`Software installation
`
`Design import and compilation .
`
`Additional import and compilation problems.
`Timescale issucs
`
`Input timing issues
`Clock ordering issucs
`Clock period issues
`
`Design compilation
`
`Partitioning .
`
`Configuration download.
`Emulation .
`
`Solaris 2.6.
`
`Debug activity .
`
`Virtual swapping.
`
`20
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`
`Ehagnosing the probicm .
`
`Command syntax
`
`virtual-swap command.
`
`Types of swap .
`Columnsvvap
`Rowswap
`Board swap
`
`Noncompiling FPGAs.
`
`Correcting noncompiling FPGAs with -FPi switch .
`
`Correcting fitting problems with -CUi switch .
`
`365
`
`365
`
`365
`
`. 366
`. 366
`. 366
`. 366
`
`367
`
`. 367
`
`. 368
`
`PC Farm . 1... ee ee et ens 369
`
`Overview .
`
`Hardware requirements .
`
`Software requirements
`
`PC setup
`
`Software installation
`
`Obtaining a RSH daemon .
`RSH daemon.
`oo.
`Test the RSH dacmon
`
`Obtaining a RSH dacmaon
`VMW/Xilins software .
`
`.
`
`YNC (optional) .
`Obtaining VNC software
`
`.
`
`Farm usage
`From the command lmc
`
`From the GUI
`
`Maintenance scripts.
`
`. 369
`
`. 369
`
`. 369
`
`370
`
`376
`
`_ 370
`_ 371
`37
`
`372
`. 372
`
`373
`373
`
`373
`373
`
`374
`
`374
`
`GHosSary.ceee 375
`
`Appendix A... 2... ..2.2.-.0-00. 0.022200. 002 ee eee ee eee 1
`
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`
`Logic analyzer setup=.)
`
`Sampling data
`Store
`
`.
`Capture data .
`Maxiimimsample depth .
`
`Downloading and running the logic analyzer .
`
`Connect to logie analvzer.
`
`2
`.2
`
`2
`2
`
`3
`
`3
`
`Run the logic analyzer ©2A
`
`Index 2.2. eee i
`
`22
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`
`List of Figures
`
`
`
`Figure 1
`Figure 2
`Figure 3
`Figure 4
`Figure 5
`Figure 6
`Figure 7
`Figure 8
`Figure
`Figure 10
`Figure 11]
`Figure 12
`Figure 13
`Figure 14
`Figure 15
`Figure 16
`Figure 17
`Figure 18
`Figure 19
`Figure 20
`Figure 2]
`Figure 22
`Figure 23
`Figure 24
`Figure 25
`Figure 26
`Figure 27
`Figure 28
`Figure 29
`Figure 30
`Figure 31
`Figure 32
`
`Transaction Interface Portal.2. 36
`In-circuit system components... 0... ....02.20........,.....32
`Screen elements22. 4d
`Button bars2 ee 47
`VirtualBrowser window.2. 49
`Find window... ...2..0.0.0022020..02022.22..2222.... 51
`Graphical path browser(Flattened design mode)... .........~,.... .54
`Graphical path browser(Design hierarchy mode)... 222. 2 5S
`Clipboard window...2 _.. 58
`Errors window0 6G
`Filebrowser,.2.2. _.. .61
`Design flow for RTL Venlog designs 2.2 _.. 66
`Design flow for RTL VHDL designs... ee 68
`Netlistimport.. 2.0222 _.. 71
`Technology mapping..- 2... 0-0-2022202022222-2022-.
`... 74
`Instance removal.0 76
`Memory specification... 2 2 BC _.. 78
`RegFileschematic 2... ....020222.202.02022........ _.. .86
`Timing specification.©. 88
`Unsupported circuit when Clk1 and CIk2 are in different domains... .
`. 92
`Rising edge synchronous inputs
`.. 2-2... 0 ee o4
`Falling edge synchronous inputs... 2... ee 95
`both edge synchronous inputs... 2... 0.0200220.022...... 0002. 06
`rising edge synchronous outputs... ee eee 97
`Falling edge synchronous outputs... ee 08
`Both edges synchronous outputs...2 ee 99
`Output clock2. 102
`Feedthrough.
`02 103
`Signalspage. 116
`Generate virsim configuration fle window... ........0.20....0..., 113
`RTLC-VLEflow forICE 0.00ee Lig
`A Sample logfile,2. 121
`
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`List of Figures
`
`Sample design report.2 136
`Figure 33
`Sample areareport... 2.2.2.22 140
`Figure 34
`RTL Compileform.. 0.0... Id
`Figure 35
`Edit module options window =
`=) ss BC _.
`. 143
`Figure 36
`RTL Compilation messapes..0) _.. 145
`Figure 37
`VLE Compile form.0 ee 147
`Figure 38
`No-flows to break multicycle paths 9.2... ... 153
`Figure 39
`No-flow bidirectionalVO net. 2 BC _.. 14
`Figure 40
`VLE Compilation messages... ee 167
`Figure 4]
`FPGA Compileform.. 2.2... 002 _.
`. 168
`Figure 42
`FPGA Cempilation messages. BC _. 175
`Figure 43
`RTL & VLE & FPGA data deletion. 20... 0 ee 176
`Figure 44
`VLE & FPGA datadeletion..2.0 176
`Figure 45
`FPGA datadeletion 2.2.00... 22 ee \77
`Figure 46
`VSMverification process steps.6 ee 179
`Figure 47
`Triggersform 2. ee 204
`Figure 48
`Add state window - attributes... ee 206
`Figure 49
`Next and Jump transition... ee 207
`Figure 50
`Adddomain... 2.0.2.0... 000000000000 000000000000, 208
`Figure 51]
`Add all domain window... 0... 2. ee 208
`Figure 52
`Add counter dialog box 2. 00 ee 209
`Figure 53
`Addtimer dialog box 22.00 ee 210
`Figure 54
`Set trigger location dialog box 20 ee 210
`Figure 35
`Emulationform.2.0 234
`Figure 56
`Setup hardware dialog...0 ee 2335
`Figure 57
`One Clock with Even Duty Cycle 2. 2 0 es 247
`Figure 58
`Two clocks with even duty cycle... 200 247
`Figure 59
`RTL Emulation/Debug use model 0. ee 340
`Figure 60
`Source level debug...2 ee 342
`Figure 61]
`Hierarchy browser... 2... 02 ee ee BAS
`Figure 62
`Show path.0 es 345
`Figure 63
`Graphical path browser(RTL Topology)... 000... 0-2022002.002. 346
`Figure 64
`Graphical path browser(Gate Topology)... 0... AP
`Figure 65
`Find Pathname Window...2 348
`Figure 66
`Figure 67 Pruning 349
`Figure 68
`Waveform viewer 20. 0 ee ee 350
`Figure 69
`Logic viewer0 330
`
`24
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`reaeB eo ay
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`~89R0 ®GRaa
`son OBacas
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`"1KOS
`
`List of Tables
`
`
`
`VirtuaLogic commands...) 40
`Table 1
`RTILCmessages... 122
`Table 2
`Configuration input files 220... 163
`Table 3
`New vrun Commands.2 164
`Table 4
`Saving and restoration of memories . 2...) 165
`Table 5
`MMCtarget commands (initial compile)...2 194
`Table 6
`MMC target commands (incremental compile} 2.2... 195
`Table 7
`RTLCE additionaloptions 252
`Table 8
`
`Table 9 VLEcompileroptions =...027 271
`Table 10
`Compiler options that canbeused together =... 2... we 317
`Table 11
`Unsupported verilog constructs. 28
`Table 12
`Compiler options forbehavicral code= 2...
`328
`Table 13
`Timing specification elements.0. 332
`Table 14
`VirttuaLogic reference library
`2
`2.
`2. 2. 4
`
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`List of Tables
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`26
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`VirtuaLagic 3.5 User Guide
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`Last Revision 25-Apr-2001
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`ATI Ex. 2075
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`"1KOS
`
`Introduction
`
`
`
`Overview
`
`Emulation is a technology that creates a prototype of an Application Specific Integrated
`Circuit (ASIC) design in hardware. The prototype is generally built through partitioning the
`design into smaller pieces and then mapping or compiling the design onto a large array of
`Field Programmabie Gate Arrays (FPGAs) or custom chips. The prototype is a complete
`functional implementation of the design including all digital functions and memories.
`
`The ASICs can be tested under real world operating conditions rather than using an
`approximation of their operating environment. [n-circuit emulators get their stimuli directly
`from the target system, unlike simulations, which require test programs, testbenches, and
`stimulus files. The advantages of emulation include full system integration and debugging
`before the ASIC design is finished and the device fabricated. This 15 especiallytrue of low
`level software, such as diagnostics and device drivers, which often require actual target
`systems for complete testing. The user can design and verify the ASICs, system hardware,
`and system software at the same time.
`
`VirtuaLogic’s technology advantages
`
`The VirtuaLogic Emulation System uses a unique patented technology called Virtual Wires.
`Virtual Wires provides significant improvements over previous technologies because it
`makes emulation less expensive and easier to use.
`
`Virtual Wires does not just map a design to the hardware, it actually compiles it for the
`specific hardware resources. ASIC designs do not map directly to FPGA and emulation
`custom chip architectures. Traditional emulation products execute a trivial translation
`process and mapthe design to the hardware, then attempt to tune the timing implementation
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`Last Revision 25-Apr-2001
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`VirtuaLagic 3.5 User Guide
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`27
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`ATI Ex. 2075
`IPR2023-00922
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`IPR2023-00922
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`Introduction Chapter 1
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`by inserting delays into the data path to compensate for hold time violations. Virtual Wires
`uses advanced synthesis technology to create a functionally identical design thatis targeted
`for the specific hardware of the VirtuaLogic emulator.
`
`With compilation of the design into a single high speed clock and pipelining signals through
`the machine using this clock, there is only one important delay, which 1s the worst case path
`through a Xilinx chip. If the VCLK period is longer than this path, then no setup and hold
`issues occur. As a result, the operating frequency of the design is immediately known at the
`completion of the configuration process.
`
`The use of Virtual Wires provides time_domain_multiplexing of multiple signals onto a
`single FPGA pin or backplane pin. This eliminates the constraint of interconnect, greatl