Texture Fetch Instruction
`
`Cycle 0
`FIELD bit DWORD bit
`OPCODE
`0
`0
`0
`OPCODE
`1
`0
`1
`OPCODE
`2
`0
`2
`OPCODE
`3
`0
`3
`OPCODE
`4
`0
`4
`FETCH_VALID_ONLY
`0
`0 19
`TX_COORD_DENORM 0
`0 25
`SAMPLE_LOCATION 0
`0 26
`0
`DST_SEL_X
`1
`0
`DST_SEL_X
`1
`1
`1
`DST_SEL_X
`2
`1
`2
`DST_SEL_Y
`0
`1
`3
`DST_SEL_Y
`1
`1
`4
`DST_SEL_Y
`2
`1
`5
`DST_SEL_Z
`0
`1
`6
`DST_SEL_Z
`1
`1
`7
`DST_SEL_Z
`2
`1
`8
`DST_SEL_W 0
`1
`9
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`
`Vertex Fetch Instruction
`
`Cycle 0
`FIELD bit DWORD bit
`OPCODE
`0
`0
`0
`OPCODE
`1
`0
`1
`OPCODE
`2
`0
`2
`OPCODE
`3
`0
`3
`OPCODE
`4
`0
`4
`FETCH_VALID_ONLY
`0
`0 19
`CONST_INDEX_SEL
`0
`0 25
`CONST_INDEX_SEL
`1
`0 26
`DST_SEL_X
`0
`1
`0
`DST_SEL_X
`1
`1
`1
`DST_SEL_X
`2
`1
`2
`DST_SEL_Y
`0
`1
`3
`DST_SEL_Y
`1
`1
`4
`DST_SEL_Y
`2
`1
`5
`DST_SEL_Z
`0
`1
`6
`DST_SEL_Z
`1
`1
`7
`DST_SEL_Z
`2
`1
`8
`DST_SEL_W 0
`1
`9
`
`Cycle 1
`FIELD bit DWORD bit
`DST_SEL_W 1
`1 10
`DST_SEL_W 1
`1 11
`MAG_FILTER 0
`1 12
`MAG_FILTER 1
`1 13
`MIN_FILTER 0
`1 14
`MIN_FILTER 1
`1 15
`MIP_FILTER 0
`1 16
`MIP_FILTER 1
`1 17
`ANISO_FILTER 0
`1 18
`ANISO_FILTER 1
`1 19
`ANISO_FILTER 2
`1 20
`ARBITRARY_FILTER 0
`1 21
`ARBITRARY_FILTER 1
`1 22
`ARBITRARY_FILTER 2
`1 23
`VOL_MAG_FILTER 0
`1 24
`VOL_MAG_FILTER 1
`1 25
`VOL_MIN_FILTER 0
`1 26
`VOL_MIN_FILTER 1
`1 27
`
`Cycle 2
`FIELD bit DWORD bit
`USE_COMP_LOD 0
`1 28
`USE_REG_LOD 0
`1 29
`USE_REG_LOD 1
`1 30
`unused
`-
`1 31
`USE_REG_GRADIENTS
`0
`2
`0
`SAMPLE_LOCATION 0
`2
`1
`LOD_BIAS
`0
`2
`2
`LOD_BIAS
`1
`2
`3
`LOD_BIAS
`2
`2
`4
`LOD_BIAS
`3
`2
`5
`LOD_BIAS
`4
`2
`6
`LOD_BIAS
`5
`2
`7
`LOD_BIAS
`6
`2
`8
`unused
`0
`2
`9
`unused
`1
`2 10
`unused
`2
`2 11
`unused
`3
`2 12
`unused
`4
`2 13
`
`Cycle 1
`FIELD bit DWORD bit
`DST_SEL_W 1
`1 10
`DST_SEL_W 1
`1 11
`0
`FORMAT_COMP_ALL
`1 12
`NUM_FORMAT_ALL
`0
`1 13
`SIGNED_RF_MODE_ALL
`0
`1 14
`INDEX_ROUND 0
`1 15
`DATA_FORMAT
`0
`1 16
`DATA_FORMAT
`1
`1 17
`DATA_FORMAT
`2
`1 18
`DATA_FORMAT
`3
`1 19
`DATA_FORMAT
`4
`1 20
`DATA_FORMAT
`5
`1 21
`unused
`-
`1 22
`unused
`-
`1 23
`EXP_ADJUST_ALL
`0
`1 24
`EXP_ADJUST_ALL
`1
`1 25
`EXP_ADJUST_ALL
`2
`1 26
`EXP_ADJUST_ALL
`3
`1 27
`
`Cycle 2
`FIELD bit DWORD bit
`EXP_ADJUST_ALL
`4
`1 28
`EXP_ADJUST_ALL
`5
`1 29
`unused
`-
`1 30
`unused
`-
`1 31
`STRIDE
`0
`2
`0
`STRIDE
`1
`2
`1
`STRIDE
`2
`2
`2
`STRIDE
`3
`2
`3
`STRIDE
`4
`2
`4
`STRIDE
`5
`2
`5
`STRIDE
`6
`2
`6
`STRIDE
`7
`2
`7
`OFFSET_X
`0
`2
`8
`OFFSET_X
`1
`2
`9
`OFFSET_X
`2
`2 10
`OFFSET_X
`3
`2 11
`OFFSET_X
`4
`2 12
`OFFSET_X
`5
`2 13
`
`Cycle 3
`FIELD bit DWORD bit 96 RD bit
`unused
`5
`2 14
`1
`0 5
`unused
`6
`2 15
`1
`0 6
`OFFSET_X
`0
`2 16
`1
`0 7
`OFFSET_X
`1
`2 17
`1
`0 8
`OFFSET_X
`2
`2 18
`1
`0 9
`OFFSET_X
`3
`2 19
`1
`0 10
`OFFSET_X
`4
`2 20
`1
`0 11
`OFFSET_Y
`0
`2 21
`1
`0 12
`OFFSET_Y
`1
`2 22
`1
`0 13
`OFFSET_Y
`2
`2 23
`1
`0 14
`OFFSET_Y
`3
`2 24
`1
`0 15
`OFFSET_Y
`4
`2 25
`1
`0 16
`OFFSET_Z
`0
`2 26
`1
`0 17
`OFFSET_Z
`1
`2 27
`1
`0 18
`OFFSET_Z
`2
`2 28
`1
`0 20
`OFFSET_Z
`3
`2 29
`1
`0 21
`OFFSET_Z
`4
`2 30
`1
`0 22
`unused
`-
`unused
`-
`1
`0 23
`1
`0 26
`1
`0 27
`1
`0 28
`Cycle 3
`1
`0 29
`FIELD bit DWORD bit
`1
`0 30
`6
`2 14
`OFFSET_X
`1
`0 31
`OFFSET_X
`7
`2 15
`1
`1 31
`OFFSET_X
`8
`2 16
`1
`2 31
`OFFSET_X
`9
`2 17
`OFFSET_X 10
`2 18 70
`OFFSET_X 11
`2 19
`OFFSET_X 12
`2 20
`OFFSET_X 13
`2 21
`OFFSET_X 14
`2 22
`OFFSET_X 15
`2 23
`OFFSET_X 16
`2 24
`OFFSET_X 17
`2 25
`OFFSET_X 18
`2 26
`OFFSET_X 19
`2 27
`OFFSET_X 20
`2 28
`OFFSET_X 21
`2 29
`OFFSET_X 22
`2 30
`unused
`-
`unused
`-
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 1 of 291
`
`

`

`Texture Fetch Constant Fields
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`
`Cycle 0
`FIELD bit DWORD bit
`unused
`-
`3
`0
`unused
`-
`3
`1
`FORMAT_COMP_X 0
`3
`2
`FORMAT_COMP_X 1
`3
`3
`FORMAT_COMP_Y 0
`3
`4
`FORMAT_COMP_Y 1
`3
`5
`0
`FORMAT_COMP_Z
`3
`6
`FORMAT_COMP_Z
`1
`3
`7
`FORMAT_COMP_W 0
`3
`8
`FORMAT_COMP_W 1
`3
`9
`CLAMP_X 0
`3 10
`CLAMP_X 1
`3 11
`CLAMP_X 2
`3 12
`0
`CLAMP_Y
`3 13
`CLAMP_Y
`1
`3 14
`CLAMP_Y
`2
`3 15
`CLAMP_Z
`0
`3 16
`CLAMP_Z
`1
`3 17
`CLAMP_Z
`2
`3 18
`SIGNED_RF_MODE_ALL
`0
`3 19
`DIM 0
`3 20
`DIM 1
`3 21
`PITCH 0
`3 22
`PITCH 1
`3 23
`PITCH 2
`3 24
`PITCH 3
`3 25
`PITCH 4
`3 26
`PITCH 5
`3 27
`PITCH 6
`3 28
`PITCH 7
`3 29
`PITCH 8
`3 30
`TILED 0
`3 31
`DATA_FORMAT
`0
`4
`0
`DATA_FORMAT
`1
`4
`1
`DATA_FORMAT
`2
`4
`2
`DATA_FORMAT
`3
`4
`3
`DATA_FORMAT
`4
`4
`4
`DATA_FORMAT
`5
`4
`5
`ENDIAN_SWAP
`0
`4
`6
`ENDIAN_SWAP
`1
`4
`7
`REQUEST_SIZE
`0
`4
`8
`REQUEST_LATENCY
`0
`4
`9
`unused
`-
`4 10
`NEAREST_CLAMP_POLICY
`0
`4 11
`BASE_ADDRESS
`0
`4 12
`BASE_ADDRESS
`1
`4 13
`BASE_ADDRESS
`2
`4 14
`BASE_ADDRESS
`3
`4 15
`
`Cycle 1
`FIELD bit DWORD bit
`BASE_ADDRESS
`4
`4 16
`BASE_ADDRESS
`5
`4 17
`BASE_ADDRESS
`6
`4 18
`BASE_ADDRESS
`7
`4 19
`BASE_ADDRESS
`8
`4 20
`BASE_ADDRESS
`9
`4 21
`BASE_ADDRESS 10
`4 22
`BASE_ADDRESS 11
`4 23
`BASE_ADDRESS 12
`4 24
`BASE_ADDRESS 13
`4 25
`BASE_ADDRESS 14
`4 26
`BASE_ADDRESS 15
`4 27
`BASE_ADDRESS 16
`4 28
`BASE_ADDRESS 17
`4 29
`BASE_ADDRESS 18
`4 30
`BASE_ADDRESS 19
`4 31
`SIZE
`0
`5
`0
`SIZE
`1
`5
`1
`SIZE
`2
`5
`2
`SIZE
`3
`5
`3
`SIZE
`4
`5
`4
`SIZE
`5
`5
`5
`SIZE
`6
`5
`6
`SIZE
`7
`5
`7
`SIZE
`8
`5
`8
`SIZE
`9
`5
`9
`SIZE 10
`5 10
`SIZE 11
`5 11
`SIZE 12
`5 12
`SIZE 13
`5 13
`SIZE 14
`5 14
`SIZE 15
`5 15
`SIZE 16
`5 16
`SIZE 17
`5 17
`SIZE 18
`5 18
`SIZE 19
`5 19
`SIZE 20
`5 20
`SIZE 21
`5 21
`SIZE 22
`5 22
`SIZE 23
`5 23
`SIZE 24
`5 24
`SIZE 25
`5 25
`SIZE 26
`5 26
`SIZE 27
`5 27
`SIZE 28
`5 28
`SIZE 29
`5 29
`SIZE 30
`5 30
`SIZE 31
`5 31
`
`Cycle 2
`FIELD bit DWORD bit
`0
`6
`0
`NUM_FORMAT_ALL
`DST_SEL_X
`0
`6
`1
`DST_SEL_X
`1
`6
`2
`DST_SEL_X
`2
`6
`3
`DST_SEL_Y
`0
`6
`4
`DST_SEL_Y
`1
`6
`5
`DST_SEL_Y
`2
`6
`6
`DST_SEL_Z
`0
`6
`7
`DST_SEL_Z
`1
`6
`8
`DST_SEL_Z
`2
`6
`9
`DST_SEL_W 0
`6 10
`DST_SEL_W 1
`6 11
`DST_SEL_W 2
`6 12
`EXP_ADJUST_ALL
`0
`6 13
`EXP_ADJUST_ALL
`1
`6 14
`EXP_ADJUST_ALL
`2
`6 15
`EXP_ADJUST_ALL
`3
`6 16
`EXP_ADJUST_ALL
`4
`6 17
`EXP_ADJUST_ALL
`5
`6 18
`MAG_FILTER 0
`6 19
`MAG_FILTER 1
`6 20
`MIN_FILTER 0
`6 21
`MIN_FILTER 1
`6 22
`MIP_FILTER 0
`6 23
`MIP_FILTER 1
`6 24
`ANISO_FILTER 0
`6 25
`ANISO_FILTER 1
`6 26
`ANISO_FILTER 2
`6 27
`ARBITRARY_FILTER 0
`6 28
`ARBITRARY_FILTER 1
`6 29
`ARBITRARY_FILTER 2
`6 30
`BORDER_SIZE
`0
`6 31
`VOL_MAG_FILTER 0
`7
`0
`VOL_MIN_FILTER 0
`7
`1
`0
`MIN_MIP_LEVEL
`7
`2
`MIN_MIP_LEVEL
`1
`7
`3
`MIN_MIP_LEVEL
`2
`7
`4
`MIN_MIP_LEVEL
`3
`7
`5
`MAX_MIP_LEVEL
`0
`7
`6
`MAX_MIP_LEVEL
`1
`7
`7
`MAX_MIP_LEVEL
`2
`7
`8
`MAX_MIP_LEVEL
`3
`7
`9
`MAG_ANISO_WALK
`0
`7 10
`MIN_ANISO_WALK
`0
`7 11
`LOD_BIAS
`0
`7 12
`LOD_BIAS
`1
`7 13
`LOD_BIAS
`2
`7 14
`LOD_BIAS
`3
`7 15
`
`Cycle 3
`FIELD bit DWORD bit
`LOD_BIAS
`4
`7 16
`LOD_BIAS
`5
`7 17
`LOD_BIAS
`6
`7 18
`LOD_BIAS
`7
`7 19
`LOD_BIAS
`8
`7 20
`LOD_BIAS
`9
`7 21
`GRAD_EXP_ADJUST_H 0
`7 22
`GRAD_EXP_ADJUST_H 1
`7 23
`GRAD_EXP_ADJUST_H 2
`7 24
`GRAD_EXP_ADJUST_H 3
`7 25
`GRAD_EXP_ADJUST_H 4
`7 26
`GRAD_EXP_ADJUST_V
`0
`7 27
`GRAD_EXP_ADJUST_V
`1
`7 28
`GRAD_EXP_ADJUST_V
`2
`7 29
`GRAD_EXP_ADJUST_V
`3
`7 30
`GRAD_EXP_ADJUST_V
`4
`7 31
`BORDER_COLOR 0
`8
`0
`BORDER_COLOR 1
`8
`1
`FORCE_BC_W_TO_MAX
`0
`8
`2
`TRI_JUICE
`0
`8
`3
`TRI_JUICE
`1
`8
`4
`unused
`-
`8
`5
`unused
`-
`8
`6
`unused
`-
`8
`7
`unused
`-
`8
`8
`unused
`-
`8
`9
`unused
`-
`8 10
`MIP_PACKING 0
`8 11
`MIP_ADDRESS
`0
`8 12
`MIP_ADDRESS
`1
`8 13
`MIP_ADDRESS
`2
`8 14
`MIP_ADDRESS
`3
`8 15
`MIP_ADDRESS
`4
`8 16
`MIP_ADDRESS
`5
`8 17
`MIP_ADDRESS
`6
`8 18
`MIP_ADDRESS
`7
`8 19
`MIP_ADDRESS
`8
`8 20
`MIP_ADDRESS
`9
`8 21
`MIP_ADDRESS 10
`8 22
`MIP_ADDRESS 11
`8 23
`MIP_ADDRESS 12
`8 24
`MIP_ADDRESS 13
`8 25
`MIP_ADDRESS 14
`8 26
`MIP_ADDRESS 15
`8 27
`MIP_ADDRESS 16
`8 28
`MIP_ADDRESS 17
`8 29
`MIP_ADDRESS 18
`8 30
`MIP_ADDRESS 19
`8 31
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 2 of 291
`
`

`

`Vertex Fetch Constant Fields
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`
`Cycle 0
`FIELD bit DWORD bit
`unused
`-
`3
`0
`unused
`-
`3
`1
`BASE_ADDRESS
`0
`3
`2
`BASE_ADDRESS
`1
`3
`3
`BASE_ADDRESS
`2
`3
`4
`BASE_ADDRESS
`3
`3
`5
`BASE_ADDRESS
`4
`3
`6
`BASE_ADDRESS
`5
`3
`7
`BASE_ADDRESS
`6
`3
`8
`BASE_ADDRESS
`7
`3
`9
`BASE_ADDRESS
`8
`3 10
`BASE_ADDRESS
`9
`3 11
`BASE_ADDRESS 10
`3 12
`BASE_ADDRESS 11
`3 13
`BASE_ADDRESS 12
`3 14
`BASE_ADDRESS 13
`3 15
`BASE_ADDRESS 14
`3 16
`BASE_ADDRESS 15
`3 17
`BASE_ADDRESS 16
`3 18
`BASE_ADDRESS 17
`3 19
`BASE_ADDRESS 18
`3 20
`BASE_ADDRESS 19
`3 21
`BASE_ADDRESS 20
`3 22
`BASE_ADDRESS 21
`3 23
`BASE_ADDRESS 22
`3 24
`BASE_ADDRESS 23
`3 25
`BASE_ADDRESS 24
`3 26
`BASE_ADDRESS 25
`3 27
`BASE_ADDRESS 26
`3 28
`BASE_ADDRESS 27
`3 29
`BASE_ADDRESS 28
`3 30
`BASE_ADDRESS 29
`3 31
`ENDIAN_SWAP
`0
`4
`0
`ENDIAN_SWAP
`1
`4
`1
`SIZE
`0
`4
`2
`SIZE
`1
`4
`3
`SIZE
`2
`4
`4
`SIZE
`3
`4
`5
`SIZE
`4
`4
`6
`SIZE
`5
`4
`7
`SIZE
`6
`4
`8
`SIZE
`7
`4
`9
`SIZE
`8
`4 10
`SIZE
`9
`4 11
`SIZE 10
`4 12
`SIZE 11
`4 13
`SIZE 12
`4 14
`SIZE 13
`4 15
`
`Cycle 1
`FIELD bit DWORD bit
`SIZE 14
`4 16
`SIZE 15
`4 17
`SIZE 16
`4 18
`SIZE 17
`4 19
`SIZE 18
`4 20
`SIZE 19
`4 21
`SIZE 20
`4 22
`SIZE 21
`4 23
`SIZE 22
`4 24
`SIZE 23
`4 25
`CLAMP_X 0
`4 26
`BORDER_COLOR 0
`4 27
`REQUEST_SIZE
`0
`4 28
`REQUEST_SIZE
`1
`4 29
`CLAMP_DISABLE
`0
`4 30
`unused
`-
`4 31
`unused
`-
`5
`0
`unused
`-
`5
`1
`BASE_ADDRESS
`0
`5
`2
`BASE_ADDRESS
`1
`5
`3
`BASE_ADDRESS
`2
`5
`4
`BASE_ADDRESS
`3
`5
`5
`BASE_ADDRESS
`4
`5
`6
`BASE_ADDRESS
`5
`5
`7
`BASE_ADDRESS
`6
`5
`8
`BASE_ADDRESS
`7
`5
`9
`BASE_ADDRESS
`8
`5 10
`BASE_ADDRESS
`9
`5 11
`BASE_ADDRESS 10
`5 12
`BASE_ADDRESS 11
`5 13
`BASE_ADDRESS 12
`5 14
`BASE_ADDRESS 13
`5 15
`BASE_ADDRESS 14
`5 16
`BASE_ADDRESS 15
`5 17
`BASE_ADDRESS 16
`5 18
`BASE_ADDRESS 17
`5 19
`BASE_ADDRESS 18
`5 20
`BASE_ADDRESS 19
`5 21
`BASE_ADDRESS 20
`5 22
`BASE_ADDRESS 21
`5 23
`BASE_ADDRESS 22
`5 24
`BASE_ADDRESS 23
`5 25
`BASE_ADDRESS 24
`5 26
`BASE_ADDRESS 25
`5 27
`BASE_ADDRESS 26
`5 28
`BASE_ADDRESS 27
`5 29
`BASE_ADDRESS 28
`5 30
`BASE_ADDRESS 29
`5 31
`
`Cycle 2
`FIELD bit DWORD bit
`ENDIAN_SWAP
`0
`6
`0
`ENDIAN_SWAP
`1
`6
`1
`SIZE
`0
`6
`2
`SIZE
`1
`6
`3
`SIZE
`2
`6
`4
`SIZE
`3
`6
`5
`SIZE
`4
`6
`6
`SIZE
`5
`6
`7
`SIZE
`6
`6
`8
`SIZE
`7
`6
`9
`SIZE
`8
`6 10
`SIZE
`9
`6 11
`SIZE 10
`6 12
`SIZE 11
`6 13
`SIZE 12
`6 14
`SIZE 13
`6 15
`SIZE 14
`6 16
`SIZE 15
`6 17
`SIZE 16
`6 18
`SIZE 17
`6 19
`SIZE 18
`6 20
`SIZE 19
`6 21
`SIZE 20
`6 22
`SIZE 21
`6 23
`SIZE 22
`6 24
`SIZE 23
`6 25
`CLAMP_X 0
`6 26
`BORDER_COLOR 0
`6 27
`REQUEST_SIZE
`0
`6 28
`REQUEST_SIZE
`1
`6 29
`CLAMP_DISABLE
`0
`6 30
`unused
`-
`6 31
`unused
`-
`7
`0
`unused
`-
`7
`1
`BASE_ADDRESS
`0
`7
`2
`BASE_ADDRESS
`1
`7
`3
`BASE_ADDRESS
`2
`7
`4
`BASE_ADDRESS
`3
`7
`5
`BASE_ADDRESS
`4
`7
`6
`BASE_ADDRESS
`5
`7
`7
`BASE_ADDRESS
`6
`7
`8
`BASE_ADDRESS
`7
`7
`9
`BASE_ADDRESS
`8
`7 10
`BASE_ADDRESS
`9
`7 11
`BASE_ADDRESS 10
`7 12
`BASE_ADDRESS 11
`7 13
`BASE_ADDRESS 12
`7 14
`BASE_ADDRESS 13
`7 15
`
`Cycle 3
`FIELD bit DWORD bit
`BASE_ADDRESS 14
`7 16
`BASE_ADDRESS 15
`7 17
`BASE_ADDRESS 16
`7 18
`BASE_ADDRESS 17
`7 19
`BASE_ADDRESS 18
`7 20
`BASE_ADDRESS 19
`7 21
`BASE_ADDRESS 20
`7 22
`BASE_ADDRESS 21
`7 23
`BASE_ADDRESS 22
`7 24
`BASE_ADDRESS 23
`7 25
`BASE_ADDRESS 24
`7 26
`BASE_ADDRESS 25
`7 27
`BASE_ADDRESS 26
`7 28
`BASE_ADDRESS 27
`7 29
`BASE_ADDRESS 28
`7 30
`BASE_ADDRESS 29
`7 31
`ENDIAN_SWAP
`0
`8
`0
`ENDIAN_SWAP
`1
`8
`1
`SIZE
`0
`8
`2
`SIZE
`1
`8
`3
`SIZE
`2
`8
`4
`SIZE
`3
`8
`5
`SIZE
`4
`8
`6
`SIZE
`5
`8
`7
`SIZE
`6
`8
`8
`SIZE
`7
`8
`9
`SIZE
`8
`8 10
`SIZE
`9
`8 11
`SIZE 10
`8 12
`SIZE 11
`8 13
`SIZE 12
`8 14
`SIZE 13
`8 15
`SIZE 14
`8 16
`SIZE 15
`8 17
`SIZE 16
`8 18
`SIZE 17
`8 19
`SIZE 18
`8 20
`SIZE 19
`8 21
`SIZE 20
`8 22
`SIZE 21
`8 23
`SIZE 22
`8 24
`SIZE 23
`8 25
`CLAMP_X 0
`8 26
`BORDER_COLOR 0
`8 27
`REQUEST_SIZE
`0
`8 28
`REQUEST_SIZE
`1
`8 29
`CLAMP_DISABLE
`0
`8 30
`unused
`-
`8 31
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 3 of 291
`
`

`

`SQ_TP_thread_id
`
`SQ_TP
`0
`1
`
`Cycle 0
`FIELD bit DWORD bit
`SQ_TP_thread_id
`0
`-
`-
`SQ_TP_thread_id
`1
`-
`-
`
`Cycle 1
`FIELD bit DWORD bit
`SQ_TP_thread_id
`2
`-
`-
`SQ_TP_thread_id
`3
`-
`-
`
`Cycle 2
`FIELD bit DWORD bit
`SQ_TP_thread_id
`4
`-
`-
`SQ_TP_thread_id
`5
`-
`-
`
`Cycle 3
`FIELD bit DWORD bit
`SQ_TP_end_of_clause
`0
`-
`-
`unused
`-
`-
`-
`
`SQ_TP_gpr_wr_addr
`
`SQ_TP
`0
`1
`
`Cycle 0
`FIELD bit DWORD bit
`SQ_TP_type
`0
`-
`-
`SQ_TP_gpr_wr_addr
`0
`-
`-
`
`Cycle 1
`FIELD bit DWORD bit
`1
`-
`-
`SQ_TP_gpr_wr_addr
`SQ_TP_gpr_wr_addr
`2
`-
`-
`
`Cycle 2
`FIELD bit DWORD bit
`SQ_TP_gpr_wr_addr
`3
`-
`-
`SQ_TP_gpr_wr_addr
`4
`-
`-
`
`Cycle 3
`FIELD bit DWORD bit
`SQ_TP_gpr_wr_addr
`5
`-
`-
`SQ_TP_gpr_wr_addr
`6
`-
`-
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 4 of 291
`
`

`

`Texture Fetch Instruction
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`
`Cycle 0
`FIELD bit DWORD bit
`OPCODE
`0
`0
`0
`OPCODE
`1
`0
`1
`OPCODE
`2
`0
`2
`OPCODE
`3
`0
`3
`OPCODE
`4
`0
`4
`FETCH_VALID_ONLY
`0
`0 19
`TX_COORD_NUM 0
`0 25
`unused
`-
`0 26
`DST_SEL_X
`0
`1
`0
`DST_SEL_X
`1
`1
`1
`DST_SEL_X
`2
`1
`2
`DST_SEL_Y
`0
`1
`3
`DST_SEL_Y
`1
`1
`4
`DST_SEL_Y
`2
`1
`5
`DST_SEL_Z
`0
`1
`6
`DST_SEL_Z
`1
`1
`7
`DST_SEL_Z
`2
`1
`8
`DST_SEL_W 0
`1
`9
`
`Cycle 1
`FIELD bit DWORD bit
`DST_SEL_W 1
`1 10
`DST_SEL_W 1
`1 11
`MAG_FILTER 0
`1 12
`MAG_FILTER 1
`1 13
`MIN_FILTER 0
`1 14
`MIN_FILTER 1
`1 15
`MIP_FILTER 0
`1 16
`MIP_FILTER 1
`1 17
`ANISO_FILTER 0
`1 18
`ANISO_FILTER 1
`1 19
`ANISO_FILTER 2
`1 20
`ARBITRARY_FILTER 0
`1 21
`ARBITRARY_FILTER 1
`1 22
`ARBITRARY_FILTER 2
`1 23
`VOL_MAG_FILTER 0
`1 24
`VOL_MAG_FILTER 1
`1 25
`VOL_MIN_FILTER 0
`1 26
`VOL_MIN_FILTER 1
`1 27
`
`Vertex Fetch Instruction
`
`Cycle 1
`Cycle 0
`FIELD bit DWORD bit
`FIELD bit DWORD bit
`DST_SEL_W 1
`1 10
`OPCODE
`0
`0
`0
`DST_SEL_W 1
`1 11
`OPCODE
`1
`0
`1
`0
`FORMAT_COMP_ALL
`1 12
`OPCODE
`2
`0
`2
`NUM_FORMAT_ALL
`0
`1 13
`OPCODE
`3
`0
`3
`4 SIGNED_RF_MODE_ALL
`0
`1 14
`OPCODE
`4
`0
`unused
`-
`0 19
`unused
`-
`1 15
`CONST_INDEX_SEL
`0
`0 25
`DATA_FORMAT
`0
`1 16
`CONST_INDEX_SEL
`1
`0 26
`DATA_FORMAT
`1
`1 17
`DST_SEL_X
`0
`1
`0
`DATA_FORMAT
`2
`1 18
`DST_SEL_X
`1
`1
`1
`DATA_FORMAT
`3
`1 19
`DST_SEL_X
`2
`1
`2
`DATA_FORMAT
`4
`1 20
`DST_SEL_Y
`0
`1
`3
`DATA_FORMAT
`5
`1 21
`DST_SEL_Y
`1
`1
`4
`unused
`-
`1 22
`DST_SEL_Y
`2
`1
`5
`unused
`-
`1 23
`DST_SEL_Z
`0
`1
`6
`EXP_ADJUST_ALL
`0
`1 24
`DST_SEL_Z
`1
`1
`7
`EXP_ADJUST_ALL
`1
`1 25
`DST_SEL_Z
`2
`1
`8
`EXP_ADJUST_ALL
`2
`1 26
`DST_SEL_W 0
`1
`9
`EXP_ADJUST_ALL
`3
`1 27
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`
`Cycle 2
`FIELD bit DWORD bit
`USE_COMP_LOD 0
`1 28
`USE_REG_LOD 0
`1 29
`USE_REG_LOD 1
`1 30
`unused
`-
`1 31
`LOD_BIAS_H 0
`2
`0
`LOD_BIAS_H 1
`2
`1
`LOD_BIAS_H 2
`2
`2
`LOD_BIAS_H 3
`2
`3
`LOD_BIAS_H 4
`2
`4
`LOD_BIAS_H 5
`2
`5
`LOD_BIAS_H 6
`2
`6
`LOD_BIAS_H 7
`2
`7
`LOD_BIAS_V
`0
`2
`8
`LOD_BIAS_V
`1
`2
`9
`LOD_BIAS_V
`2
`2 10
`LOD_BIAS_V
`3
`2 11
`LOD_BIAS_V
`4
`2 12
`LOD_BIAS_V
`5
`2 13
`
`Cycle 2
`FIELD bit DWORD bit
`EXP_ADJUST_ALL
`4
`1 28
`EXP_ADJUST_ALL
`5
`1 29
`unused
`-
`1 30
`unused
`-
`1 31
`STRIDE
`0
`2
`0
`STRIDE
`1
`2
`1
`STRIDE
`2
`2
`2
`STRIDE
`3
`2
`3
`STRIDE
`4
`2
`4
`STRIDE
`5
`2
`5
`STRIDE
`6
`2
`6
`STRIDE
`7
`2
`7
`unused
`-
`2
`8
`unused
`-
`2
`9
`unused
`-
`2 10
`unused
`-
`2 11
`unused
`-
`2 12
`unused
`-
`2 13
`
`96 DWORD bit
`1
`0 5
`1
`0 6
`1
`0 7
`1
`0 8
`1
`0 9
`1
`0 10
`1
`0 11
`1
`0 12
`1
`0 13
`1
`0 14
`1
`0 15
`1
`0 16
`1
`0 17
`1
`0 18
`1
`0 20
`1
`0 21
`1
`0 22
`1
`0 23
`1
`0 26
`1
`0 27
`1
`0 28
`1
`0 29
`1
`0 30
`1
`0 31
`1
`1 31
`1
`2 31
`70
`
`Cycle 3
`FIELD bit DWORD bit
`LOD_BIAS_V
`6
`2 14
`LOD_BIAS_V
`7
`2 15
`SAMPLE_SHIFT_X 0
`2 16
`SAMPLE_SHIFT_X 1
`2 17
`SAMPLE_SHIFT_X 2
`2 18
`SAMPLE_SHIFT_X 3
`2 19
`SAMPLE_SHIFT_X 4
`2 20
`SAMPLE_SHIFT_Y
`0
`2 21
`SAMPLE_SHIFT_Y
`1
`2 22
`SAMPLE_SHIFT_Y
`2
`2 23
`SAMPLE_SHIFT_Y
`3
`2 24
`SAMPLE_SHIFT_Y
`4
`2 25
`SAMPLE_SHIFT_Z
`0
`2 26
`SAMPLE_SHIFT_Z
`1
`2 27
`SAMPLE_SHIFT_Z
`2
`2 28
`SAMPLE_SHIFT_Z
`3
`2 29
`SAMPLE_SHIFT_Z
`4
`2 30
`unused
`-
`unused
`-
`
`Cycle 3
`FIELD bit DWORD bit
`unused
`-
`2 14
`unused
`-
`2 15
`OFFSET
`0
`2 16
`OFFSET
`1
`2 17
`OFFSET
`2
`2 18
`OFFSET
`3
`2 19
`OFFSET
`4
`2 20
`OFFSET
`5
`2 21
`OFFSET
`6
`2 22
`OFFSET
`7
`2 23
`unused
`-
`2 24
`unused
`-
`2 25
`unused
`-
`2 26
`unused
`-
`2 27
`unused
`-
`2 28
`unused
`-
`2 29
`unused
`-
`2 30
`unused
`-
`unused
`-
`
`Cycle 3
`FIELD bit DWORD bit
`LOD_BIAS_H 6
`7 16
`LOD_BIAS_H 7
`7 17
`LOD_BIAS_H 8
`7 18
`LOD_BIAS_H 9
`7 19
`LOD_BIAS_V
`0
`7 20
`LOD_BIAS_V
`1
`7 21
`LOD_BIAS_V
`2
`7 22
`LOD_BIAS_V
`3
`7 23
`LOD_BIAS_V
`4
`7 24
`LOD_BIAS_V
`5
`7 25
`LOD_BIAS_V
`6
`7 26
`
`Texture Fetch Constant Fields
`
`Cycle 0
`FIELD bit DWORD bit
`unused
`-
`3
`0
`unused
`-
`3
`1
`FORMAT_COMP_X 0
`3
`2
`FORMAT_COMP_X 1
`3
`3
`FORMAT_COMP_Y 0
`3
`4
`FORMAT_COMP_Y 1
`3
`5
`0
`FORMAT_COMP_Z
`3
`6
`FORMAT_COMP_Z
`1
`3
`7
`FORMAT_COMP_W 0
`3
`8
`FORMAT_COMP_W 1
`3
`9
`CLAMP_X 0
`3 10
`
`Cycle 1
`FIELD bit DWORD bit
`BASE_ADDRESS
`4
`4 16
`BASE_ADDRESS
`5
`4 17
`BASE_ADDRESS
`6
`4 18
`BASE_ADDRESS
`7
`4 19
`BASE_ADDRESS
`8
`4 20
`BASE_ADDRESS
`9
`4 21
`BASE_ADDRESS 10
`4 22
`BASE_ADDRESS 11
`4 23
`BASE_ADDRESS 12
`4 24
`BASE_ADDRESS 13
`4 25
`BASE_ADDRESS 14
`4 26
`
`Cycle 2
`FIELD bit DWORD bit
`0
`6
`0
`NUM_FORMAT_ALL
`DST_SEL_X
`0
`6
`1
`DST_SEL_X
`1
`6
`2
`DST_SEL_X
`2
`6
`3
`DST_SEL_Y
`0
`6
`4
`DST_SEL_Y
`1
`6
`5
`DST_SEL_Y
`2
`6
`6
`DST_SEL_Z
`0
`6
`7
`DST_SEL_Z
`1
`6
`8
`DST_SEL_Z
`2
`6
`9
`DST_SEL_W 0
`6 10
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 5 of 291
`
`

`

`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`
`CLAMP_X 1
`CLAMP_X 2
`0
`CLAMP_Y
`CLAMP_Y
`1
`CLAMP_Y
`2
`CLAMP_Z
`0
`CLAMP_Z
`1
`CLAMP_Z
`2
`SIGNED_RF_MODE_ALL
`0
`DIM 0
`DIM 1
`PITCH 0
`PITCH 1
`PITCH 2
`PITCH 3
`PITCH 4
`PITCH 5
`PITCH 6
`PITCH 7
`PITCH 8
`TILED 0
`DATA_FORMAT
`0
`DATA_FORMAT
`1
`DATA_FORMAT
`2
`DATA_FORMAT
`3
`DATA_FORMAT
`4
`DATA_FORMAT
`5
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`BASE_ADDRESS
`0
`BASE_ADDRESS
`1
`BASE_ADDRESS
`2
`BASE_ADDRESS
`3
`
`3 11
`3 12
`3 13
`3 14
`3 15
`3 16
`3 17
`3 18
`3 19
`3 20
`3 21
`3 22
`3 23
`3 24
`3 25
`3 26
`3 27
`3 28
`3 29
`3 30
`3 31
`4
`0
`4
`1
`4
`2
`4
`3
`4
`4
`4
`5
`4
`6
`4
`7
`4
`8
`4
`9
`4 10
`4 11
`4 12
`4 13
`4 14
`4 15
`
`Vertex Fetch Constant Fields
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`
`Cycle 0
`FIELD bit DWORD bit
`unused
`-
`3
`0
`unused
`-
`3
`1
`BASE_ADDRESS
`0
`3
`2
`BASE_ADDRESS
`1
`3
`3
`BASE_ADDRESS
`2
`3
`4
`BASE_ADDRESS
`3
`3
`5
`BASE_ADDRESS
`4
`3
`6
`BASE_ADDRESS
`5
`3
`7
`BASE_ADDRESS
`6
`3
`8
`BASE_ADDRESS
`7
`3
`9
`BASE_ADDRESS
`8
`3 10
`BASE_ADDRESS
`9
`3 11
`BASE_ADDRESS 10
`3 12
`BASE_ADDRESS 11
`3 13
`BASE_ADDRESS 12
`3 14
`BASE_ADDRESS 13
`3 15
`BASE_ADDRESS 14
`3 16
`
`BASE_ADDRESS 15
`BASE_ADDRESS 16
`BASE_ADDRESS 17
`BASE_ADDRESS 18
`BASE_ADDRESS 19
`SIZE
`0
`SIZE
`1
`SIZE
`2
`SIZE
`3
`SIZE
`4
`SIZE
`5
`SIZE
`6
`SIZE
`7
`SIZE
`8
`SIZE
`9
`SIZE 10
`SIZE 11
`SIZE 12
`SIZE 13
`SIZE 14
`SIZE 15
`SIZE 16
`SIZE 17
`SIZE 18
`SIZE 19
`SIZE 20
`SIZE 21
`SIZE 22
`SIZE 23
`SIZE 24
`SIZE 25
`SIZE 26
`SIZE 27
`SIZE 28
`SIZE 29
`ENDIAN_SWAP
`0
`ENDIAN_SWAP
`1
`
`4 27
`4 28
`4 29
`4 30
`4 31
`5
`0
`5
`1
`5
`2
`5
`3
`5
`4
`5
`5
`5
`6
`5
`7
`5
`8
`5
`9
`5 10
`5 11
`5 12
`5 13
`5 14
`5 15
`5 16
`5 17
`5 18
`5 19
`5 20
`5 21
`5 22
`5 23
`5 24
`5 25
`5 26
`5 27
`5 28
`5 29
`5 30
`5 31
`
`DST_SEL_W 1
`DST_SEL_W 2
`EXP_ADJUST_ALL
`0
`EXP_ADJUST_ALL
`1
`EXP_ADJUST_ALL
`2
`EXP_ADJUST_ALL
`3
`EXP_ADJUST_ALL
`4
`EXP_ADJUST_ALL
`5
`MAG_FILTER 0
`MAG_FILTER 1
`MIN_FILTER 0
`MIN_FILTER 1
`MIP_FILTER 0
`MIP_FILTER 1
`ANISO_FILTER 0
`ANISO_FILTER 1
`ANISO_FILTER 2
`ARBITRARY_FILTER 0
`ARBITRARY_FILTER 1
`ARBITRARY_FILTER 2
`BORDER_SIZE
`0
`VOL_MAG_FILTER 0
`VOL_MIN_FILTER 0
`0
`MIN_MIP_LEVEL
`MIN_MIP_LEVEL
`1
`MIN_MIP_LEVEL
`2
`MIN_MIP_LEVEL
`3
`MAX_MIP_LEVEL
`0
`MAX_MIP_LEVEL
`1
`MAX_MIP_LEVEL
`2
`MAX_MIP_LEVEL
`3
`LOD_BIAS_H 0
`LOD_BIAS_H 1
`LOD_BIAS_H 2
`LOD_BIAS_H 3
`LOD_BIAS_H 4
`LOD_BIAS_H 5
`
`6 11
`6 12
`6 13
`6 14
`6 15
`6 16
`6 17
`6 18
`6 19
`6 20
`6 21
`6 22
`6 23
`6 24
`6 25
`6 26
`6 27
`6 28
`6 29
`6 30
`6 31
`7
`0
`7
`1
`7
`2
`7
`3
`7
`4
`7
`5
`7
`6
`7
`7
`7
`8
`7
`9
`7 10
`7 11
`7 12
`7 13
`7 14
`7 15
`
`7
`LOD_BIAS_V
`8
`LOD_BIAS_V
`9
`LOD_BIAS_V
`DIM_3D 0
`unused
`-
`BORDER_COLOR 0
`BORDER_COLOR 1
`FORCE_BC_W_TO_MAX
`0
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`unused
`-
`MIP_ADDRESS
`0
`MIP_ADDRESS
`1
`MIP_ADDRESS
`2
`MIP_ADDRESS
`3
`MIP_ADDRESS
`4
`MIP_ADDRESS
`5
`MIP_ADDRESS
`6
`MIP_ADDRESS
`7
`MIP_ADDRESS
`8
`MIP_ADDRESS
`9
`MIP_ADDRESS 10
`MIP_ADDRESS 11
`MIP_ADDRESS 12
`MIP_ADDRESS 13
`MIP_ADDRESS 14
`MIP_ADDRESS 15
`MIP_ADDRESS 16
`MIP_ADDRESS 17
`MIP_ADDRESS 18
`MIP_ADDRESS 19
`
`7 27
`7 28
`7 29
`7 30
`7 31
`8
`0
`8
`1
`8
`2
`8
`3
`8
`4
`8
`5
`8
`6
`8
`7
`8
`8
`8
`9
`8 10
`8 11
`8 12
`8 13
`8 14
`8 15
`8 16
`8 17
`8 18
`8 19
`8 20
`8 21
`8 22
`8 23
`8 24
`8 25
`8 26
`8 27
`8 28
`8 29
`8 30
`8 31
`
`Cycle 1
`FIELD bit DWORD bit
`LIMIT_ADDRESS 14
`4 16
`LIMIT_ADDRESS 15
`4 17
`LIMIT_ADDRESS 16
`4 18
`LIMIT_ADDRESS 17
`4 19
`LIMIT_ADDRESS 18
`4 20
`LIMIT_ADDRESS 19
`4 21
`LIMIT_ADDRESS 20
`4 22
`LIMIT_ADDRESS 21
`4 23
`LIMIT_ADDRESS 22
`4 24
`LIMIT_ADDRESS 23
`4 25
`LIMIT_ADDRESS 24
`4 26
`LIMIT_ADDRESS 25
`4 27
`LIMIT_ADDRESS 26
`4 28
`LIMIT_ADDRESS 27
`4 29
`LIMIT_ADDRESS 28
`4 30
`LIMIT_ADDRESS 29
`4 31
`unused
`-
`5
`0
`
`Cycle 2
`FIELD bit DWORD bit
`ENDIAN_SWAP
`0
`6
`0
`ENDIAN_SWAP
`1
`6
`1
`LIMIT_ADDRESS
`0
`6
`2
`LIMIT_ADDRESS
`1
`6
`3
`LIMIT_ADDRESS
`2
`6
`4
`LIMIT_ADDRESS
`3
`6
`5
`LIMIT_ADDRESS
`4
`6
`6
`LIMIT_ADDRESS
`5
`6
`7
`LIMIT_ADDRESS
`6
`6
`8
`LIMIT_ADDRESS
`7
`6
`9
`LIMIT_ADDRESS
`8
`6 10
`LIMIT_ADDRESS
`9
`6 11
`LIMIT_ADDRESS 10
`6 12
`LIMIT_ADDRESS 11
`6 13
`LIMIT_ADDRESS 12
`6 14
`LIMIT_ADDRESS 13
`6 15
`LIMIT_ADDRESS 14
`6 16
`
`Cycle 3
`FIELD bit DWORD bit
`BASE_ADDRESS 14
`7 16
`BASE_ADDRESS 15
`7 17
`BASE_ADDRESS 16
`7 18
`BASE_ADDRESS 17
`7 19
`BASE_ADDRESS 18
`7 20
`BASE_ADDRESS 19
`7 21
`BASE_ADDRESS 20
`7 22
`BASE_ADDRESS 21
`7 23
`BASE_ADDRESS 22
`7 24
`BASE_ADDRESS 23
`7 25
`BASE_ADDRESS 24
`7 26
`BASE_ADDRESS 25
`7 27
`BASE_ADDRESS 26
`7 28
`BASE_ADDRESS 27
`7 29
`LIMIT_ADDRESS 29
`7 30
`BASE_ADDRESS 29
`7 31
`ENDIAN_SWAP
`0
`8
`0
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 6 of 291
`
`

`

`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`
`BASE_ADDRESS 15
`BASE_ADDRESS 16
`BASE_ADDRESS 17
`BASE_ADDRESS 18
`BASE_ADDRESS 19
`BASE_ADDRESS 20
`BASE_ADDRESS 21
`BASE_ADDRESS 22
`BASE_ADDRESS 23
`BASE_ADDRESS 24
`BASE_ADDRESS 25
`BASE_ADDRESS 26
`BASE_ADDRESS 27
`BASE_ADDRESS 28
`BASE_ADDRESS 29
`ENDIAN_SWAP
`0
`ENDIAN_SWAP
`1
`LIMIT_ADDRESS
`0
`LIMIT_ADDRESS
`1
`LIMIT_ADDRESS
`2
`LIMIT_ADDRESS
`3
`LIMIT_ADDRESS
`4
`LIMIT_ADDRESS
`5
`LIMIT_ADDRESS
`6
`LIMIT_ADDRESS
`7
`LIMIT_ADDRESS
`8
`LIMIT_ADDRESS
`9
`LIMIT_ADDRESS 10
`LIMIT_ADDRESS 11
`LIMIT_ADDRESS 12
`LIMIT_ADDRESS 13
`
`3 17
`3 18
`3 19
`3 20
`3 21
`3 22
`3 23
`3 24
`3 25
`3 26
`3 27
`3 28
`3 29
`3 30
`3 31
`4
`0
`4
`1
`4
`2
`4
`3
`4
`4
`4
`5
`4
`6
`4
`7
`4
`8
`4
`9
`4 10
`4 11
`4 12
`4 13
`4 14
`4 15
`
`-
`unused
`0
`BASE_ADDRESS
`1
`BASE_ADDRESS
`2
`BASE_ADDRESS
`3
`BASE_ADDRESS
`4
`BASE_ADDRESS
`5
`BASE_ADDRESS
`6
`BASE_ADDRESS
`7
`BASE_ADDRESS
`8
`BASE_ADDRESS
`9
`BASE_ADDRESS
`BASE_ADDRESS 10
`BASE_ADDRESS 11
`BASE_ADDRESS 12
`BASE_ADDRESS 13
`BASE_ADDRESS 14
`BASE_ADDRESS 15
`BASE_ADDRESS 16
`BASE_ADDRESS 17
`BASE_ADDRESS 18
`BASE_ADDRESS 19
`BASE_ADDRESS 20
`BASE_ADDRESS 21
`BASE_ADDRESS 22
`BASE_ADDRESS 23
`BASE_ADDRESS 24
`BASE_ADDRESS 25
`BASE_ADDRESS 26
`BASE_ADDRESS 27
`BASE_ADDRESS 28
`BASE_ADDRESS 29
`
`1
`5
`2
`5
`3
`5
`4
`5
`5
`5
`6
`5
`7
`5
`8
`5
`9
`5
`5 10
`5 11
`5 12
`5 13
`5 14
`5 15
`5 16
`5 17
`5 18
`5 19
`5 20
`5 21
`5 22
`5 23
`5 24
`5 25
`5 26
`5 27
`5 28
`5 29
`5 30
`5 31
`
`LIMIT_ADDRESS 15
`LIMIT_ADDRESS 16
`LIMIT_ADDRESS 17
`LIMIT_ADDRESS 18
`LIMIT_ADDRESS 19
`LIMIT_ADDRESS 20
`LIMIT_ADDRESS 21
`LIMIT_ADDRESS 22
`LIMIT_ADDRESS 23
`LIMIT_ADDRESS 24
`LIMIT_ADDRESS 25
`LIMIT_ADDRESS 26
`LIMIT_ADDRESS 27
`LIMIT_ADDRESS 28
`BASE_ADDRESS 28
`unused
`-
`unused
`-
`BASE_ADDRESS
`0
`BASE_ADDRESS
`1
`BASE_ADDRESS
`2
`BASE_ADDRESS
`3
`BASE_ADDRESS
`4
`BASE_ADDRESS
`5
`BASE_ADDRESS
`6
`BASE_ADDRESS
`7
`BASE_ADDRESS
`8
`BASE_ADDRESS
`9
`BASE_ADDRESS 10
`BASE_ADDRESS 11
`BASE_ADDRESS 12
`BASE_ADDRESS 13
`
`6 17
`6 18
`6 19
`6 20
`6 21
`6 22
`6 23
`6 24
`6 25
`6 26
`6 27
`6 28
`6 29
`6 30
`6 31
`7
`0
`7
`1
`7
`2
`7
`3
`7
`4
`7
`5
`7
`6
`7
`7
`7
`8
`7
`9
`7 10
`7 11
`7 12
`7 13
`7 14
`7 15
`
`1
`ENDIAN_SWAP
`0
`LIMIT_ADDRESS
`1
`LIMIT_ADDRESS
`2
`LIMIT_ADDRESS
`3
`LIMIT_ADDRESS
`4
`LIMIT_ADDRESS
`5
`LIMIT_ADDRESS
`6
`LIMIT_ADDRESS
`7
`LIMIT_ADDRESS
`8
`LIMIT_ADDRESS
`9
`LIMIT_ADDRESS
`LIMIT_ADDRESS 10
`LIMIT_ADDRESS 11
`LIMIT_ADDRESS 12
`LIMIT_ADDRESS 13
`LIMIT_ADDRESS 14
`LIMIT_ADDRESS 15
`LIMIT_ADDRESS 16
`LIMIT_ADDRESS 17
`LIMIT_ADDRESS 18
`LIMIT_ADDRESS 19
`LIMIT_ADDRESS 20
`LIMIT_ADDRESS 21
`LIMIT_ADDRESS 22
`LIMIT_ADDRESS 23
`LIMIT_ADDRESS 24
`LIMIT_ADDRESS 25
`LIMIT_ADDRESS 26
`LIMIT_ADDRESS 27
`LIMIT_ADDRESS 28
`LIMIT_ADDRESS 29
`
`1
`8
`2
`8
`3
`8
`4
`8
`5
`8
`6
`8
`7
`8
`8
`8
`9
`8
`8 10
`8 11
`8 12
`8 13
`8 14
`8 15
`8 16
`8 17
`8 18
`8 19
`8 20
`8 21
`8 22
`8 23
`8 24
`8 25
`8 26
`8 27
`8 28
`8 29
`8 30
`8 31
`
`SQ_TP_clause
`
`SQ_TP
`0
`
`Cycle 0
`FIELD bit DWORD bit
`SQ_TP_clause_num 0
`-
`-
`
`Cycle 1
`FIELD bit DWORD bit
`SQ_TP_clause_num 1
`-
`-
`
`Cycle 2
`FIELD bit DWORD bit
`SQ_TP_clause_num 2
`-
`-
`
`Cycle 3
`FIELD bit DWORD bit
`SQ_TP_end_of_clause
`0
`-
`-
`
`SQ_TP_gpr_wr_addr
`
`SQ_TP
`0
`1
`
`Cycle 0
`FIELD bit DWORD bit
`SQ_TP_type
`0
`-
`-
`SQ_TP_gpr_wr_addr
`0
`-
`-
`
`Cycle 1
`FIELD bit DWORD bit
`1
`-
`-
`SQ_TP_gpr_wr_addr
`SQ_TP_gpr_wr_addr
`2
`-
`-
`
`Cycle 2
`FIELD bit DWORD bit
`SQ_TP_gpr_wr_addr
`3
`-
`-
`SQ_TP_gpr_wr_addr
`4
`-
`-
`
`Cycle 3
`FIELD bit DWORD bit
`SQ_TP_gpr_wr_addr
`5
`-
`-
`SQ_TP_gpr_wr_addr
`6
`-
`-
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 7 of 291
`
`

`

`Vertex Fetch Constant Fields
`
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`0
`x Fetch Instr
`0
`SQ_TP
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`0
`Fetch Const
`0
`SQ_TP
`0
`1
`2
`
`Cycle 0
`FIELD bit DWORD bit
`unused
`-
`2 30
`unused
`-
`2 31
`BASE_ADDRESS
`0
`0
`2
`BASE_ADDRESS
`1
`0
`3
`BASE_ADDRESS
`2
`0
`4
`BASE_ADDRESS
`3
`0
`5
`BASE_ADDRESS
`4
`0
`6
`BASE_ADDRESS
`5
`0
`7
`BASE_ADDRESS
`6
`0
`8
`BASE_ADDRESS
`7
`0
`9
`BASE_ADDRESS
`8
`0 10
`BASE_ADDRESS
`9
`0 11
`BASE_ADDRESS 10
`0 12
`BASE_ADDRESS 11
`0 13
`BASE_ADDRESS 12
`0 14
`BASE_ADDRESS 13
`0 15
`BASE_ADDRESS 14
`0 16
`BASE_ADDRESS 15
`0 17
`BASE_ADDRESS 16
`0 18
`BASE_ADDRESS 17
`0 19
`BASE_ADDRESS 18
`0 20
`BASE_ADDRESS 19
`0 21
`BASE_ADDRESS 20
`0 22
`BASE_ADDRESS 21
`0 23
`BASE_ADDRESS 22
`0 24
`BASE_ADDRESS 23
`0 25
`BASE_ADDRESS 24
`0 26
`BASE_ADDRESS 25
`0 27
`BASE_ADDRESS 26
`0 28
`BASE_ADDRESS 27
`0 29
`BASE_ADDRESS 28
`0 30
`BASE_ADDRESS 29
`0 31
`unused
`-
`5
`0
`unused
`-
`5
`1
`unused
`-
`3
`0
`unused
`-
`3
`1
`unused
`-
`3
`2
`unused
`-
`3
`3
`unused
`-
`3
`4
`unused
`-
`3
`5
`unused
`-
`3
`6
`unused
`-
`3
`7
`unused
`-
`3
`8
`unused
`-
`3
`9
`unused
`-
`3 10
`unused
`-
`3 11
`unused
`-
`3 12
`
`Cycle 1
`FIELD bit DWORD bit
`unused
`-
`2
`0
`unused
`-
`2
`1
`unused
`-
`2
`2
`unused
`-
`2
`3
`unused
`-
`2
`4
`unused
`-
`2
`5
`unused
`-
`2
`6
`unused
`-
`2
`7
`unused
`-
`2
`8
`unused
`-
`2
`9
`unused
`-
`2 10
`unused
`-
`2 11
`unused
`-
`2 12
`unused
`-
`2 13
`unused
`-
`2 14
`unused
`-
`2 15
`unused
`-
`2 16
`unused
`-
`2 17
`unused
`-
`2 18
`unused
`-
`2 19
`unused
`-
`2 20
`unused
`-
`2 21
`unused
`-
`2 22
`unused
`-
`2 23
`unused
`-
`2 24
`unused
`-
`2 25
`unused
`-
`2 26
`unused
`-
`2 27
`unused
`-
`2 28
`unused
`-
`2 29
`BASE_ADDRESS 18
`0 20
`BASE_ADDRESS 19
`0 21
`unused
`-
`4 30
`unused
`-
`3 19
`unused
`-
`3 20
`unused
`-
`3 21
`unused
`-
`3 22
`unused
`-
`3 23
`unused
`-
`3 24
`unused
`-
`3 25
`unused
`-
`3 26
`unused
`-
`3 27
`unused
`-
`3 28
`unused
`-
`3 29
`unused
`-
`3 30
`unused
`-
`4
`0
`unused
`-
`4
`1
`
`Vertex Fetch Constant Fields (Straightforward Packing)
`1 2.65625
`0
`2.6875
`0 2
`0 3
`0 4
`0 5
`
`6
`7
`8
`9
`10
`
`FORMAT_COMP_Z
`BASE_ADDRESS 0
`BASE_ADDRESS 1
`BASE_ADDRESS 2
`BASE_ADDRESS 3
`
`6
`
`9 4.15625
`BASE_ADDRESS 10
`4.1875 22
`LIMIT_ADDRESS 15
`1 17
`LIMIT_ADDRESS 16
`1 18
`LIMIT_ADDRESS 17
`1 19
`LIMIT_ADDRESS 18
`1 20
`
`Cycle 2
`FIELD bit DWORD bit
`unused
`-
`5
`6
`unused
`-
`5
`7
`unused
`-
`5
`8
`unused
`-
`5
`9
`unused
`-
`5 10
`unused
`-
`5 11
`unused
`-
`5 12
`unused
`-
`5 13
`unused
`-
`5 14
`unused
`-
`5 15
`unused
`-
`5 16
`unused
`-
`5 17
`unused
`-
`5 18
`unused
`-
`5 19
`unused
`-
`5 20
`unused
`-
`5 21
`unused
`-
`5 22
`unused
`-
`5 23
`unused
`-
`5 24
`unused
`-
`4
`2
`unused
`-
`4
`3
`unused
`-
`4
`4
`unused
`-
`4
`5
`unused
`-
`4
`6
`unused
`-
`4
`7
`unused
`-
`4
`8
`unused
`-
`4
`9
`unused
`-
`4 10
`unused
`-
`4 11
`unused
`-
`4 12
`unused
`-
`4 13
`unused
`-
`4 14
`unused
`-
`4 15
`unused
`-
`4 16
`unused
`-
`4 17
`unused
`-
`4 18
`unused
`-
`4 19
`unused
`-
`4 20
`unused
`-
`4 21
`unused
`-
`4 22
`unused
`-
`4 23
`unused
`-
`4 24
`unused
`-
`4 25
`unused
`-
`4 26
`unused
`-
`4 27
`unused
`-
`4 28
`unused
`-
`4 29
`
`Cycle 3
`FIELD bit DWORD bit
`ENDIAN_SWAP
`0
`1
`0
`ENDIAN_SWAP
`1
`1
`1
`LIMIT_ADDRESS
`0
`1
`2
`LIMIT_ADDRESS
`1
`1
`3
`LIMIT_ADDRESS
`2
`1
`4
`LIMIT_ADDRESS
`3
`1
`5
`LIMIT_ADDRESS
`4
`1
`6
`LIMIT_ADDRESS
`5
`1
`7
`LIMIT_ADDRESS
`6
`1
`8
`LIMIT_ADDRESS
`7
`1
`9
`LIMIT_ADDRESS
`8
`1 10
`LIMIT_ADDRESS
`9
`1 11
`LIMIT_ADDRESS 10
`1 12
`LIMIT_ADDRESS 11
`1 13
`LIMIT_ADDRESS 12
`1 14
`LIMIT_ADDRESS 13
`1 15
`LIMIT_ADDRESS 14
`1 16
`LIMIT_ADDRESS 15
`1 17
`LIMIT_ADDRESS 16
`1 18
`LIMIT_ADDRESS 17
`1 19
`LIMIT_ADDRESS 18
`1 20
`LIMIT_ADDRESS 19
`1 21
`LIMIT_ADDRESS 20
`1 22
`LIMIT_ADDRESS 21
`1 23
`LIMIT_ADDRESS 22
`1 24
`LIMIT_ADDRESS 23
`1 25
`LIMIT_ADDRESS 24
`1 26
`LIMIT_ADDRESS 25
`1 27
`LIMIT_ADDRESS 26
`1 28
`LIMIT_ADDRESS 27
`1 29
`LIMIT_ADDRESS 28
`1 30
`LIMIT_ADDRESS 29
`1 31
`unused
`-
`3 31
`unused
`-
`5
`2
`unused
`-
`5 25
`unused
`-
`5 26
`unused
`-
`5 27
`unused
`-
`5 28
`unused
`-
`5 29
`unused
`-
`5 30
`unused
`-
`5 31
`unused
`-
`3 13
`unused
`-
`3 14
`unused
`-
`3 15
`unused
`-
`3 16
`unused
`-
`3 17
`unused
`-
`3 18
`
`DST_SEL_Y
`unused -
`unused -
`unused -
`unused -
`
`1 5.65625
`2
`5.6875
`3 0
`3 1
`3 2
`3 3
`
`6 AD_EXP_ADJUST_H
`unused -
`unused -
`unused -
`unused -
`
`9 7.15625
`0
`7.1875 22
`4 15
`4 16
`4 17
`4 18
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 8 of 291
`
`

`

`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`0
`etch Consta
`0
`SQ_TP
`0
`1
`
`BASE_ADDRESS 4
`BASE_ADDRESS 5
`BASE_ADDRESS 6
`BASE_ADDRESS 7
`BASE_ADDRESS 8
`BASE_ADDRESS 9
`BASE_ADDRESS 10
`BASE_ADDRESS 11
`BASE_ADDRESS 12
`BASE_ADDRESS 13
`BASE_ADDRESS 14
`BASE_ADDRESS 15
`BASE_ADDRESS 16
`BASE_ADDRESS 17
`BASE_ADDRESS 18
`BASE_ADDRESS 19
`BASE_ADDRESS 20
`BASE_ADDRESS 21
`BASE_ADDRESS 22
`BASE_ADDRESS 23
`BASE_ADDRESS 24
`BASE_ADDRESS 25
`BASE_ADDRESS 26
`BASE_ADDRESS 27
`BASE_ADDRESS 28
`BASE_ADDRESS 29
`ENDIAN_SWAP 0
`ENDIAN_SWAP 1
`LIMIT_ADDRESS 0
`LIMIT_ADDRESS 1
`LIMIT_ADDRESS 2
`LIMIT_ADDRESS 3
`LIMIT_ADDRESS 4
`LIMIT_ADDRESS 5
`LIMIT_ADDRESS 6
`LIMIT_ADDRESS 7
`LIMIT_ADDRESS 8
`LIMIT_ADDRESS 9
`LIMIT_ADDRESS 10
`LIMIT_ADDRESS 11
`LIMIT_ADDRESS 12
`LIMIT_ADDRESS 13
`LIMIT_ADDRESS 14
`
`0 6
`0 7
`0 8
`0 9
`0 10
`0 11
`0 12
`0 13
`0 14
`0 15
`0 16
`0 17
`0 18
`0 19
`0 20
`0 21
`0 22
`0 23
`0 24
`0 25
`0 26
`0 27
`0 28
`0 29
`0 30
`0 31
`1 0
`1 1
`1 2
`1 3
`1 4
`1 5
`1 6
`1 7
`1 8
`1 9
`1 10
`1 11
`1 12
`1 13
`1 14
`1 15
`1 16
`
`LIMIT_ADDRESS 19
`LIMIT_ADDRESS 20
`LIMIT_ADDRESS 21
`LIMIT_ADDRESS 22
`LIMIT_ADDRESS 23
`LIMIT_ADDRESS 24
`LIMIT_ADDRESS 25
`LIMIT_ADDRESS 26
`LIMIT_ADDRESS 27
`LIMIT_ADDRESS 28
`LIMIT_ADDRESS 29
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`
`1 21
`1 22
`1 23
`1 24
`1 25
`1 26
`1 27
`1 28
`1 29
`1 30
`1 31
`2 0
`2 1
`2 2
`2 3
`2 4
`2 5
`2 6
`2 7
`2 8
`2 9
`2 10
`2 11
`2 12
`2 13
`2 14
`2 15
`2 16
`2 17
`2 18
`2 19
`2 20
`2 21
`2 22
`2 23
`2 24
`2 25
`2 26
`2 27
`2 28
`2 29
`2 30
`2 31
`
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
`unused -
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`
`3 4
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`3 20
`3 21
`3 22
`3 23
`3 24
`3 25
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`3 27
`3 28
`3 29
`3 30
`3 31
`4 0
`4 1
`4 2
`4 3
`4 4
`4 5
`4 6
`4 7
`4 8
`4 9
`4 10
`4 11
`4 12
`4 13
`4 14
`
`unused -
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`
`4 19
`4 20
`4 21
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`4 24
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`4 28
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`4 30
`5 0
`5 1
`5 2
`5 6
`5 7
`5 8
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`5 10
`5 11
`5 12
`5 13
`5 14
`5 15
`5 16
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`5 19
`5 20
`5 21
`5 22
`5 23
`5 24
`5 25
`5 26
`5 27
`5 28
`5 29
`5 30
`5 31
`unused -
`unused -
`
`AMD1044_0207649
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 9 of 291
`
`

`

`Vl
`: i
`
`ORIGINATE DATE
`4 June, 2002
`
`EDIT DATE
`[date Wa “d MMMM,
`
`DOCUMENT-REV. NUM.
`GEN-CRAAXS-REVA
`
`PAGE
`1 of 32
`
`Author:
`
`Jay GC. Wilkinson
`
`pond
`
`ic
`
`R400 RB Depth
`(RBD)
`
`ver 0.1
`
`form or by any means without the prior written permission of ATI Technologies Inc,”
`
`Overview: The R400 RB Depth computes stencil and depth tests on quads of pixels,
`
`WARKING: Familiarity wih “R400 Memory Format Specification” (Perforce depot'réO0/doc_lb/designichipimemory-
`R400_MemoryFormat.pah) is required.
`
`AUTOMATICALLY UPDATED FIELDS:
`Document Location:
`C400\Wec_libiWesigniblockswbiR400 RB Depth.doc
`Current Intranet Search Tithe :
`R400 RB Depth (RBD)
`APPROVALS
`
`Signature/Date
`
`Remarks:
`
`THIS DOCUMENT CONTAINS CONFIDENTIAL INFORMATION THAT COULD BE
`SUBSTANTIALLY DETRIMENTAL TO THE INTEREST OF ATI TECHNOLOGIES
`INC. THROUGH UNAUTHORIZED USE OR DISCLOSURE.
`
`“Copyright 2000, AT! Technologies Inc. All rights reserved. The material in this document constitutes an unpublished
`work created in 2000. The use of (his copyright notice is intended to provide notice that ATI owns @ copyright in this
`unpublished work. The copyright notice is mot an admission thal publication has occured. This work contains confidential,
`propriciary information and trade secrets of ATI, No part of this document may be used, reproduced, or transmitted in any
`
`etO Mi Depth ac
`
`sat oie@ ATI Confidential. Reference Copyright Notice on Cover Page © #**0600 9447 ou
`
`AMD CONFIDENTIAL BUSINESS INFORMATION - SUBJECT TO THE PROTECTIVE ORDER
`
`AMD1044_020683938
`
`ATI Ex. 2066
`IPR2023-00922
`Page 10 of 291
`
`ATI Ex. 2066
`
`IPR2023-00922
`Page 10 of 291
`
`

`

`i
`
` Vat
`ORIGINATE DATE
`EDIT DATE
`DOCUMENT-REV. NUM.
`4 June, 2002
`[date Va “d MMMM,
`R400 RB Depth (RBD)
`Table Of Contents
`
`;
`
`ARCHITECTURAL REQUIREMENTS...
`
`6
`
`eeLeSdfa ee
`
`aaejbecsiitee Neee
`No Stencil Data (FrameBufferonly)...
`sjuuteuaussestsuseasecssestvwsvedeeessorscavensereveneaseerreaee B
`Uncompressed Stencil Data..
`i
`Compressed Stencil Data (Frame Buffer only)...began ILM=PASLSARLAONAET ROU MER EATE IURAONSSAaRemNETOePEe aE LaRen 8
`23.1
`Compressed Stencil format..........0.00..cccccccccccccccscscesesscasesuecesoesseescccetsovecesoaseesesseeavensenees 9
`;DERRYRRR viiecsshcteccseavscabevacactitedviveceavecsiuaneevienwas oiveavistuaiekedtatesuvedeuldventis écivcisbudvcvoiive 12
`4.3 Depth, 24 bit FloatingPPoint...
`sidiovew'nusgunimns avad'vaud/euuguuvidusau'vavwusvwnvuesecdueteavewnsnvteavanvnceven Ll
`
`42 Depth, 24 bit URF..
`
`ighpaigustbuasaaiedelsea
`
`pal
`
`adealan ac umalcae abhi anova oa ied mua pvaada
`
`sab baa iaaea a
`
`Rimoe NON PAPRSSA i nna paniba i yeaivandanOiTen pyoqihanwik! RACE
`ssi vito beeen Nb SEOH RA
`44 Depth, 96 bit Zplane...
`i EPRNE inespansiattaces acess whaaaaheieli linnbdbck aac 14
`6,
`DEPTH CACHE FORMATS...
`sank
`iiseeAbanibapWaal sine nnsale otiseae ees
`6.1
`Stencil & Pmask Depth CacheFormate. cccccccccccscsvcsssssoosessvivsssssssessesvusvasanesseseseensnnen 14
`6.2
`Single Sample Stencil & Pmask Frame Buffer Format...ee eceeeeeneeeeeeeeneees 15
`63:
`“(60 Daoth Gache Word Fonnatic choice at aaalee 21
`64
`24 bit (URF or FP) Depth Cache Word Format .........0.0..:..0000:0c0cccisceeceeeedtecseeseasene