aappllkhna1
`@|
`
`
`
`
`ATI Technologies Inc.
`
`Phase-Locked Loop
`for AGP 8X Interface
`
`Requirement Specification for 0.1541m Development
`
`Karen Wan
`
`IC Development Group
`
`Revision 0.1
`
`Last Updated on May 10, 2001
`
`
`
`Copyright © 2000, ATI Technologies Inc. All rights reserved. The material in this document constitutes an unpublished work created
`in 2000. The use of this copyright notice is intended to provide notice that ATI Technologies Inc. owns a copyright
`in this
`unpublished work. The copyright notice is not an admission that publication has occurred. This work contains confidential,
`proprietary information and trade secrets of ATI Technologies Inc. No part of this document may be used,
`reproduced, or
`transmitted in any form or by any meanswithout the prior written permission of ATI Technologies Inc.
`
`ATI Ex. 2064
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`il
`
`Phase-Locked Loop for AGP 8X interface
`
`— ATI Technologies Inc.
`Page 2 of 20
`
`
`Revision History
`
`Revision
`Date
`Author
`Remark
`
`
`01
`
`May 10,
`2001
`
`Karen Wan
`
`Initial Revision
`
`
`Printed on Mar 22 2002 4:07:00 PM
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
`
`ATI Ex. 2064
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`ATI Technologies Inc.
`Page 3 of 20
`
`Phase-Locked Loop for AGP 8X interface
`
`Table of Contents
`
`INCFOCUCHION. 00. ceeee ceases teeter nee nienii enti nnnneeiieeneeneceneeeeeeeeeeeeeenensessneeees 4
`
`Functional Specification ........ccccceccccceecsseesssessssssessseesssseeessenssseeneeenneeesneees 5
`
`Electrical Specification ..........ccccceeeseeeeeeeeee eee eeeeeneeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeseees 11
`
`Qualification Plan .............c.:.ccccccceeeeeeeeeeenessseeeeeeeeeeeeeeeeeenssseneeeeeeeeeeeeeeenees 16
`
`Production Test Plan.............cccccceeceeeeccceeeeeceeeeeeeeeaeeeesseesseeeteeeeneeeeeeeeeeees 17
`
`Circuit Design Guideline ............ eee ccceeecseeeeeeeeeeeeeeeeeeeesseeeeeeeeeeeeeeeeenees 17
`
`RTL Design and Behavioral Modeling Guideline....................:::ceeee 18
`
`Place and Route Guideline .............ccccccsesecceeeeeeeeeeeeeeeeseeeeeeeeeseeeeeeeneseneees 19
`
`Package DeSign Guideline................ccccceeccceeeeeeeeeeeeneneeeeeeeeeeeeeeeeeeneenscees 20
`
`PCB DeSiQn Guideline..........ccccccceessseeeeeeeeeeeereiieeeeeecceneeieeeeeaneeeeesceneees 20
`
`BIOS/Software Programming Guideline ..........cccesceeseeereeeeeeeeeeeeeeeeeee 20
`
`
`
`ATI TechnologiesInc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
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`ATI Technologies Inc. Page 4 of 20
`
`Phase-Locked Loop for AGP 8X interface
`
`Introduction
`
`is designed to provide the hardware design teams with the technical
`This document
`specifications required by a fully integrated PLL-based clock synthesizer for AGP 8X interface
`to meet ATI’s future product requirements. The use of standard 0.15um single-gate-oxide
`1P7M digital CMOS processwith 1.8Vtg power supply is a stated requirementfor this class of
`products.
`
`This specification is intended to provide circuit designers a well-defined and measurable
`design target that will meet the system-level clocking requirements. While the focus of this
`documentis on functionality and electrical and timing parameters, verification procedures at
`different design stages are also covered in detail to ensure sufficient
`level of testability.
`Finally,
`the design guidelines for other development and qualification groups place the
`documentin a system-level context.
`
`This specification provides a baseline of developmentfor the clocking requirements in future
`ATI products. It is not the only implementation that can be developed; however, this baseline
`functionality is required for most systems.
`
`Note: The PLL specified in this documentis dedicated for AGP 8X interface and may not be
`suitable for any other purposes.
`
`Key Features
`
`e
`
`Input bus clock frequency ranges from 33 to 66MHz
`
`e VCO frequency ranges from 528MHz to 1.056GHz
`
`e
`
`e
`
`Less than 50ps cycle-to-cycle, and 200ps peak-to-peak jitter with 100mVpp sinusoidal
`supply ripple
`
`Support spread spectrum bus clock from Intel CK97-compliant clock synthesizer/driver
`
`e=Fully integrated with built-in self-biasing circuitry
`
`e
`
`Less than 8mAaverage current consumption under nominal conditions
`
`e Designed using standard 1.8Vtg, 0.15um single-gate-oxide digital CMOS process
`
`AGP Interface
`
`TBW
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
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`Page 5 of 20
`ATI Technologies Inc.
`
`Phase-Locked Loop for AGP 8X interface
`
`Functional Specification
`
`This section details the functional requirement of a PLL optimized for AGP 8X interface.
`
`Port Definition and Building Blocks
`
`The following diagram shows the basic building blocks of the macro:
`
`
`
`T¥COMAX
`IPVG(2:0)
`
`OKBCLK
`
`MODES
`ITXBCLK
`
`OXICLK
`
`IM@DE[3]
`
`MODES4]
`
`COX2CLK
`
`IMODE[0]
`
`IMO@DE[2.1]
`
`SCA
`
`
`
`
`
`IPBCA2:0]
`
`
`‘
`
`
`
`LC
`
`SCB
`
`
`
`
`IPSCBI2.0|
`
`PLL
`
`
`
`
`
`IPCP[2:0]
`IPSCREF[2:0]
`ITREFSEL
`
`
`!
`
`__j
`'
`
`UP
`
`DN
`
`cP
`
`¥
`
`| |
`
`ve
`
`5 28MHz-
`1.066Mhz
`
`VCO __
`
`a0
`
`
`
`
`
`
`
`
`
`IREFCLK
`
`ITREFCLK
`
`IFBCLK
`ITFACLK
`
`1
`
`:
`
`ITFBSEL
`IPSCFEI2:0]
`ITSPGFF
`
`:
`
`ITH1CLK
`IDOL
`IRESET __' Reset
`IPWBN
`‘ pe Power down
`
`Phase/Frequency Detector
`PFD:
`Charge Pump
`CP.
`Loop Filter
`LF:
`Yeo—Valtage-Controlled Cscillater
`sc.
`Programmable Skew Control
`DIV?
`Frequency Divider (divide by 7]
`
`e Figure 1: Functional Block Diagram
`
`The macro has 38 input ports and 3 output ports. It also requires a pair of dedicated power
`and ground for the analog portion of the macro, along with the core VDD and V&S.
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
`ATI Ex. 2064
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`
`ATI TechnologiesInc.
`Port Name
`Description
`
`Phase-Locked Loop for AGP 8X interface
`
`Page 6 of 20
`
`IREFCLK
`
`IFBCLK
`
`IRESET
`
`IPWDN
`
`IMODE[6:0]
`
`IPCP[2:0]
`
`IPSCA[2:0]
`IPSCB[2:0]
`
`IPSCREF[2:0]
`
`IPSCFB[2:0]
`
`IPVG[2:0]
`
`ITREFCLK
`
`ITREFSEL
`
`ITFBCLK
`
`ITFBSEL
`
`ITX2CLK
`
`ITX8CLK
`
`ITCPOFF
`
`Reference Clock. This is the clock signal that the PLLtries to lock to. The front-end of
`the macrois rising edge sensitive and, therefore, its duty-cycle is ignored.
`
`FeedbackClock. This is the clock signal that the PLL used to compare with IREFCLK.
`Like IREFCLK,its duty-cycle is not important.
`
`Reset Signal (active high, level sensitive). A low level puts the PLL in normal operating
`mode.A high level resets the PLL. The macro will not operate properly before going
`through the reset sequence. During reset, OX1CLK and OX2CLK shall remain at logic
`low.
`
`Power-down Enable (active high, level sensitive). A low level indicates normal operation.
`A high level puts the macro into power-downstate.
`
`Output Clock Source Select. Select the output clock sources for OX1CLK, OX2CLK and
`OX8CLK asdifferent bus transfer modes have different clocking requirements.
`
`Charge-pump Current Adjustment.
`
`Output Clock Skew Adjustment. Adjust the propagation delay of SC A and B
`respectively, whichin turn introduces phase offset between the different output clock
`sources. The delay can be used to compensatetiming mismatch between BCLK CT
`(runs off OX1CLK) and BCLKX2 CT(runs off OX2CLK).
`
`Reference Clock Skew Adjustment. Adjust the propagation delay of SC REF, a
`programmable skew control, whichin turn introduces phase offset between the
`reference and the feedback inputs. The delay can be used to compensate timing
`mismatch between external bus clock and BCLK CT (runs off OX1CLK).
`
`Feedback Clock Skew Adjustment. Adjust the propagation delay of SC FB, a
`programmable skew control, whichin turn introduces phase offset between the
`reference and the feedback inputs. The delay can be used to compensate timing
`mismatch between external bus clock and BCLK CT(runs off OX1CLK).
`
`VCO Gain Adjustment.
`
`Test Reference Clock. A clock signal that can replace IREFCLK as the reference input
`to the PFD during various ASIC test modes.
`
`Test Reference Clock Select. A low level selects IREFCLKas the reference input to the
`PFD. A high level selects ITREFCLK.
`
`Test Feedback Clock. A clock signal that can replace IFBCLK as the feedbackinput to
`the PFD during various ASIC test modes.
`
`Test Feedback Clock Select. A low level selects IFBCLK as the feedbackinput to the
`PFD. A high level selects ITFBCLK.
`
`Test Clock for BCLKX2 CT. A clock signal that can be selected to become OX2CLK
`during various ASIC test modes.
`
`Test Clock for AGP8X clock. A clock signal that can be selected to become OX8CLK
`during various ASIC test modes.
`
`Charge-pump Output Hi-Z Test Mode Enable (active high, level sensitive). A low level
`indicates normal operation. A high level forces the charge-pump output to become high
`impedance,letting the VCO free running.
`
`ITVCOMAX
`
`Maximum VCO Frequency Test Mode Enable (active high, level sensitive). A low level
`indicates normal operation. A high level at both this signal and ITCPOFF simultaneously
`
`shall force the VCO to run at maximum possible frequency (a.k.a. runaway).
`
`OX1CLK
`
`OX2CLK
`
`Output Clock for BCLK CT. Aclock signal for driving BCLK CT. The macro provides
`multiple output clock sources and can be selected through IMODE[2:0] depending on
`the bus transfer mode.
`
`Output Clock for BCLKX2 CT. A clock signal for driving BCLKX2 CT. The macro
`provides multiple output clack sources and can be selected through IMODE[5:3]
`depending on the bus transfer mode.
`
`OX8CLK
`Output Clock for AGP8X clock whichis output to 1/0 pad. The output can be the AGP8X
`
`clock or the ITX8CLK depending on the IMODE[6].
`
`VDDCK
`
`Analog Power. It should be a well-regulated power for the analog portion of the macro.
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
`ATI Ex. 2064
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`
`
`ATI Technologies Inc.
`Port Name
`Description
`
`Phase-Locked Loop for AGP 8X interface
`
`Page 7 of 20
`
`Analog Ground. It should be a well-regulated, low-impedance ground return path for the
`VSSCK
`analog partion of the macro,
`
`« Table 1: Port Definition
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
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`Printed on Mar 22 2002 4:07:00 PM
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`ATI Technologies Inc. Page 8 of 20
`
`e
`
`Phase-Locked Loop for AGP 8X interface
`
`Function Table
`
`The following table summarizes the required settings to place the macroin the 5 different
`operating modes. While X’s in the table mark don’t-care situations, they do not mean the
`signals can toggle or be held at any other voltage levels except logic high and logic low.
`
`
`Port Name
`
`IREFCLK
`
`IFBCLK
`
`IRESET
`
`IPWDN
`
`IMODE[6:0]
`
`IPCP[2:0]
`
`IPSCA[2:0]
`
`IPSCB[2:0]
`
`IPSCC[2:0]
`
`IPSCD[2:0]
`
`Normal
`
`clock
`
`clock
`
`0
`
`0
`
`MODE
`
`PCP
`
`PSCA
`
`PSCB
`
`PSCC
`
`PSCD
`
`Power-
`Down
`
`Hi-Z CP
`Test
`
`Max. VCO
`Test
`
`Xx
`
`Xx
`
`xX
`
`1
`
`Xx
`
`xX
`
`x
`
`X
`
`Xx
`
`x
`
`x
`
`XK
`
`0
`
`0
`
`MODE
`
`PCP
`
`PSCA
`
`PSCB
`
`PSCC
`
`PSCD
`
`x
`
`xX
`
`0
`
`0
`
`MODE
`
`PCP
`
`PSCA
`
`PSCB
`
`PSCC
`
`PSCD
`
`PSCREF
`
`IPSCREF[2:0]
`
`IPSCFB[2:0]
`
`IPVG[20]
`ITREFCLK
`
`ITREFSEL
`
`ITFBCLK
`
`ITFBSEL
`
`ITX1CLK
`
`ITX2CLK
`
`ITCPOFF
`
`PSCREF
`
`PSCFB
`
`PVG
`x
`
`0
`
`x
`
`0
`
`xX
`
`x
`
`0
`
`X
`
`Xx
`
`x
`X
`
`Xx
`
`x
`
`X
`
`Xx
`
`x
`
`0
`
`PSCREF
`
`PSCFB
`
`PVG
`0
`
`PSCFB
`
`PVG
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`1
`
`0
`
`0
`
`0
`
`0
`
`0
`
`1
`
`ITVCOMAX
`0
`0
`0
`1
`
`
`OX1CLK
`
`OX2CLK
`
`clock
`
`clock
`
`0
`
`0
`
`clock
`
`clock
`
`clock
`
`clock
`
`OX8CLK
`clock
`0
`clock
`clock
`
`
`e Table 2: Function Table
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
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`Phase-Locked Loop for AGP 8X interface
`
`
`
`
`
`
`
`ATI Technologies Inc.
`Page 9 of 20
`Normal Operation
`
`During normal operation, the macro should behave like a clock generator and phase aligning
`circuit. The timing characteristics of its output clocks at OX1CLK and OX2CLK should fall
`within the requirements specified by this document.
`
`Power-down Mode
`
`The macro shall be placed in a zero-power suspend state when IPWDN is held at logic high
`while switching activities at all other input ports are stopped. Once in Power-down Mode, the
`macro should consume neither dynamic nor standing power except the inevitable tiny
`leakage current that are common to all CMOS design. The output ports OX1CLK and
`OX2CLK shall be stopped and forced to remain at logic low immediately.
`
`To bring the macro back to normal operation, the IPVVDN signal shall first be de-asserted,
`followed by resetting the macro properly as prescribed below.
`
`If glitches on the output clocks are not acceptable, one may elect to assert IRESET before
`IPWDN during the power-down sequence. To turn on the macro and haveit reset, reverse
`the order by de-asserting IPWDN before IRESET. By “bracketing” IPWDN signal with
`IRESETsignal the macro should produceno glitch at its output ports.
`
`
`Test Mode: Charge-pump Output High Impedance
`
`In this test mode, the charge-pump of the macro will be shutoff, letting the VCO free running.
`The purposeof this test mode is to provide a mean to quantify the loop filter leakage, which is
`one of the mostcritical process parameters affecting the performance of the macro.
`
`To put the macro in this test mode, the ITCPOFF signal should be held at logic high. The
`charge-pump should then be shut off, leaving the loop filter, which is the input control to the
`VCO, at high impedance. The amount, as well as the direction, of the leakage current can
`then be monitored indirectly through the VCO output frequency. The macro shall stay in this
`test mode indefinitely until the signal ITCPOFF is de-asserted. Proper reset sequence should
`then be followed to put the macro back to normal operation.
`
`Test Mode: Maximum VCO Frequency
`
`The maximum oscillation frequency of the VCO shall be able to be characterized. The testis
`good for characterizing the macro and correlating the real silicon with SPICE simulations. It
`can also be an overall performanceindicator of a process.
`
`To put the macro in this test mode, both ITCPOFF and ITVCOMAX will be held at logic high.
`The charge-pump should then be shut off, allowing the VCO to be forced to run at
`its
`maximum frequency within a specified period. The macro shall stay in this test mode
`indefinitely until
`the signals ITCPOFF and ITVCOMAX are de-asserted. Proper reset
`sequence should then be followed to put the macro back ta normal operation.
`
`Reset Procedure
`
`Resetting the PLL shall putits logic portion into a known state, and force the VCO to run atits
`slowest possible speed by discharging the loop filter completely. The output clocks are also
`gated to remain at logic low throughout the reset period. The reset signal is level sensitive,
`and hasto be assertedfor at least the minimal amountof time specified.
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
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`Phase-Locked Loop for AGP 8X interface
`
`
`ATI TechnologiesInc.
`Page10 of 20
`Oncethe reset signal is de-asserted, the VCO frequencywill start ramping up slowly until the
`PLL acquired lock. The actual time required for the PLL to lock varies with different operating
`conditions and target frequency, but it shall never exceed the maximum lock time specified.
`Note that the output clock frequency may overshoot up to a maximum allowable amount
`before reaching steady state at the target frequency.
`
`The PLL should be resetif one or more of the following applies:
`
`e
`
`Upon power up;
`
`e Has been waken up from Power-down Mode or any one of the test modes; or
`
`e
`
`Reference and/or feedback frequencies have been changed for whatever reason.
`
`For any change in the value of the adjustment inputs that would stimulate the feedback
`system, reset is not necessary but time has to be given for the PLL to re-lock. Input ports
`including IPCP, IPVG, IPSCREF, IPSCFB, and IPSCA all fall under this category.
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`Printed on Mar 22 2002 4:07:00 PM
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`ATI Technologies Inc. Page 11 of 20
`
`Phase-Locked Loop for AGP 8X interface
`
`Electrical Specification
`
`This section defines the DC operating requirements, electrical and timing requirements, as
`well as physical requirements of the macro.
`
`DC Operating Requirements
`
`In order to ensure the macro has enough design margin to function properly over a wide
`range of operating conditions,
`it should be designed to meet the electrical and timing
`requirements under all specified corner conditions:
`
`Corner1: Corner2: Corner3: Corner4: Corner 5: Corner 6:
`Noml.
`Fast
`Slow
`FNSP
`SNFP-
`Noml. HT
`
`Parameter
`
`Symbol
`
`Process
`
`nom!
`
`fast
`
`slow
`
`fnsp
`
`snip
`
`nom!
`
`125°C
`25°C
`25°C
`125°C
`orc
`25°C
`Junction Temp.
`TEMPJ
`VDD 1.80V Supply Voltage 1.80V 1.98V 1.62V 1.80V 1.80V
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`e Table 3: DC Operating Requirements
`
`The only exception to meeting the above operating requirements is when “binning” of devices
`(sorting devices by performance) is achievable and acceptable. In that case, the “design-to-
`corners” approach would likely be replaced by Monte Carlo analysis to give a more accurate
`prediction on yield. Nevertheless,
`the new operating requirements, which are usually
`expressed in statistical terms such as mean or variation, should still be clearly stated in the
`design specification.
`
`Electrical and Timing Requirements
`
`The Electrical Requirements table provides the limits for each critical design parameter, over
`all DC operating conditions detailed in the previous section unless otherwise specified. The
`“Min”, “Typ” and “Max” columns of the table are the limits of parameters only and are not
`related in any way to the operating condition.
`
`
`Unit Notes
`Max
`Min
`Parameter
`Symbol
`TIP
`IREFCLKPeriod
`15
`30
`ns
`14
`
`
`Typ
`
`
`FIP
`IREFCLK Frequency
`33
`66
`MHz
`2
`
`TIH
`IREFCLK High Time
`2.0
`ns
`TIL
`IREFCLK Low Time
`2.0
`ns
`
`
`
`TOP
`VCO Output Period
`0.947
`1.89
`ns
`1
`
`FOP
`VCO Output Frequency
`528
`1059 MHz
`3
`
`TODC
`OX1CLK/OX2CLK Duty Cycle
`49
`50
`51
`%
`1,4
`
`FOOS
`VCO Output Frequency Overshoot
`2.5
`%
`5
`
`TJCC
`Cycle-to-Cycle Jitter
`50
`ps
`1,6
`
`TJPP
`Peak-to-PeakJitter
`200
`ps
`1,6
`
`TJLT
`Long Term Jitter (1us after scope trigger)
`1.0
`ns
`1,6
`CMAX
`Maximum Load
`500
`iF
`7
`
`
`
`TSCD
`Skew Control Propagation Delay
`2.8
`ns
`1,8
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
`ATI Ex. 2064
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`

`
`
`
`
`
`Phase-Locked Loop for AGP 8X interface
`
`ATI Technologies Inc.
`Symbol
`Parameter
`
`Min’
`
`Typ
`
`Max
`
`Page 12 of 20
`Unit Notes
`
`
`TERR
`Static Phase Error
`-100
`+100
`ps
`1,9,10
`
`TOSK
`OX2CLK to OX1CLK Skew
`-100
`+100
`ps
`1,9.11
`
`TRST
`Reset Time
`10
`us
`1,12
`
`
`TLOCK
`PLL Lock Time
`50
`us
`1,13
`
`
`TTVM
`Acquisition Time for Maximum VCO Frequency
`10
`us
`1,14
`
`IDDCK
`Average Supply Current at VDDCK
`8.0
`mA
`15
`IPDCK
`Power Down Current at VDDCK
`1.0
`uA
`16
`
`Notes:
`
`1
`
`Time intervals measured at 50% VDDCKthreshold point.
`
`2 FlPisthe reciprocal of TIP.
`
`3
`
`FOP is the reciprocal of TOP.
`
`4 TODClimits should be met over the entire range of FOP.
`
`5
`
`FOOSis valid during lock acquisition only, and is expressed as a fraction of the target steady
`state VCO output frequency.
`
`6 All jitter measurements are performed at OX1CLK. A+50mvVsinusoidal ripple is superimposed on
`VDDCK,with ripple frequency ranging from minimum FIP to maximum FOP.
`
`7 CMAX is the maximum capacitive load seen by any output ports that shall give an output
`transition time (10-90% VDDCk)of less than 800ps.
`
`8 TSCD is the propagation delay of SC when maximum delaysetting is used.
`
`9 Measured at proper SC delay setting, i.e. identical setting at corresponding timing arcs.
`
`10 TERR only applies after phase-locked.
`11 Measured at Load = CMAX
`
`12 Minimum time to keep IRESET remain asserted.
`13 Measured from IRESETis de-asserted.
`
`14 Measured from |ITCPOFF and ITVCOMAX are asserted.
`
`15 Measured under Corner 1 conditions, at minimum FIP and maximum FOP. Current measurement
`averaged over 500ns period.
`
`16 Measured under Corner 1 conditions, based on typical leakage values.
`
`e Table 4: Electrical and Timing Requirements
`
`'
`
`TIP
`
`'
`
`
`
`
`
`IREFCLKffXN
`
`TIH
`
`TIL
`
`e Figure 2: IREFCLK Period, High Time and Low Time
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
`ATI Ex. 2064
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`

`SUL
`° |
`
`ATI Technologies Inc.
`
`Phase-Locked LoopforAGP 8Xinterface
`
`» Figure 3: VCO Output Period
`
`
`
`Page 13 of 20
`
`
`VCO Freq §
`
`
`
`Reset
`
`Acquisition
`
`Stable OCLK
`
`TLOCK
`
`ia1
`
`y
`
`Time
`
`e Figure 4: ¥CO Output Frequency Overshoot (notte scale}
`
`
`
`
`
`
`
`e Figure 5: Peak-to-Peak Jitter (first rising edge after oscilloscopetrigger}
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
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`

`SUL
`° |
`— ATI Technologies Inc.
`
`Phase-Locked LoopforAGP 8Xinterface
`
`Page 14 of 20
`
`TILT
`
`OX1CLK FONei
`
`I
`
`> tus
`
`ie
`
`|
`
`« Figure 6: Long Term Jitler (at least 1Us after oscilloscope trigger)
`
`
`
`TERR
`
`el ‘
`
`IFBCLK
`
`
`
`
`
`
`
`
`e Figure 7: Static Phase Error (positive TERR shown}
`
`
`
`TOSK
`
`ra '
`
`OX1CLKfe\ffN\
`
`I
`
`OX2C0LK
`
`« Figure 8: OX2CLK to OX1CLK Skew (pasitive TOSK shown)
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
`ATI Ex. 2064
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`

`

`SUL
`° |
`
`_
`
`ATI Technologies Inc.
`
`Phase-Locked LoopforAGP 8Xinterface
`
`Page 15 of 20
`
`TRST
`
`¥_
`
`TLOCK
`
`
`
`
`
`a !'
`
`IRESET +
`
`OCLK
`
`Stable VCO Out
`
`e Figure 9: Reset Time and PLL Lock Time
`
`Physical Requirements
`
`The macro shall meet the following layout requirements:
`Feature Size
`0.15um
`
`Complete block out on all metal layers
`Metal Layers Blockages
`
`Silicon Area 0.20mm"
`
`« Table 5: Physical Requirements
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
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`

`SUL
`of}
`~~
`
`
`
`ATI Technologies Inc. Page 16 of 20
`
`Phase-Locked LoopforAGP 8Xinterface
`
`Qualification Plan
`
`Loop Gain Setting
`
`Clock Cycle-to-cycle Jitter
`
`Clock Peak-to-peak Jitter
`
`Clock Long Term Jitter
`
`Skew Control Propagation Delay
`
`Average Supply Current
`
`Power-down Current
`
`Supply and Ground Noise
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
`Printed on Mar 22 2002 4:07:00 PM
`
`ATI Ex. 2064
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`

`

`il
`
`Phase-Locked Loop for AGP 8X interface
`
`— ATI Technologies Inc.
`
`Page 17 of 20
`
`Production Test Plan
`
`Frequency Test
`
`Circuit Design Guideline
`
` ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page. Printed on Mar 22 2002 4:07:00 PM
`
`
`
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`

`

`& |
`
`
`
`
`
`
`Phase-Locked Loop for AGP 8X interface
`
`
`
`ATI Technologies Inc. Page 18 of 20
`
`RTL Design and Behavioral Modeling Guideline
`
`I/O Pad and BGABall Assignment
`
`The following table lists the required |/O pad and pin assignment for the macro. As indicated
`by the variable X on the “Pad #’ column, the whole macro can be shifted around the I/O ring,
`as long as the signal ordering is preserved. Mirroring of the macro is also acceptable. The
`BGAball assignmentfor this macro in Rage128P is also included as an example.
`
`
`Pad #
`x
`
`xX+1*
`
`Pad Name
`PVSS
`
`PVSS
`
`Macro Signal
`VSSCK
`
`VSSCK
`
`Rage128P
`BGABall
`AB2
`
`AB2
`
`X+2
`PVDD
`VDBDCK
`AC2
`
`PVDD VDDCKX+3* AC2
`Note:
`
`
`
`
`
`These pads are optional when shared by two or less
`*
`PLLs(anytype).
`
`e Table 6: I/O Pad and BGA Ball Assignment
`
`The macro requires a total of four I/O pads and two balls. The BGA balls that assigned to the
`macro are located besides together. This shall give them easy access to the voltage
`regulator. The following diagram visually shows howthe balls are assigned in Rage128P.
`
`
`
`
`
`
`
`1
`2
`3
`
`
`
`a
`{| Pyss
`|
`a
`[| PDD |
`
`
`
`aA
`
`B
`AC
`
`e Figure 10: BGA Ball Assignment in Rage128P (Top View)
`
`Note that some assumptions have been made when the arrangement was constructed. The
`pad or ball assignmentshall change if any one ofthe following itemsis violated:
`
`e
`
`Padpitch is exactly 50um, and pad height is no more than 600um.
`
`e Double bonding is technically achievable.
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`Printed on Mar 22 2002 4:07:00 PM
`
`ATI Ex. 2064
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`

`

`SUL
`° |
`
`_
`
`
`ATI Technologies Inc.
`Page 19 of 20
`
`Phase-Locked LoopforAGP 8Xinterface
`
`Place and Route Guideline
`
`Macro Footprint
`
`Power and Ground Routing
`
`The power supply and ground of the macro should be routed to the dedicated I/O pads using
`all layers of metal as allowed by the process.
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
`
`Printed on Mar 22 2002 4:07:00 PM
`
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`

`SUL
`of}
`~~
`
`
`
`ATI Technologies Inc. Page 20 of 20
`
`Phase-Locked LoopforAGP 8Xinterface
`
`Package Design Guideline
`
`PCB Design Guideline
`
`BlOS/Software Programming Guideline
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
`Printed on Mar 22 2002 4:07:00 PM
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`

`

`@|
`
`aplplikhna1
`
`
`
`
`
`ATI Technologies Inc.
`
`PLL Clock Synthesizer
`for High-Speed Digital Circuits
`
`Requirement Specification for 0.1541m Development
`
`KAREN WAN
`
`IC Development Group
`
`Revision 0.2
`
`Last Updated on June 19, 2007
`
`
`
`WARNING
`
`
`
`
`
`This documentcontains confidential information that could be substantially detrimental
`to the interest of ATi Technologies Inc. through unauthorized use or disclosure.
`
`
`
`Copyright © 2000, ATI Technologies Inc. All rights reserved. The material in this document constitutes an unpublished work created
`in 2000. The use of this copyright notice is intended to provide notice that ATI Technologies Inc. owns a copyright
`in this
`unpublished work. The copyright notice is not an admission that publication has occurred. This work contains confidential,
`proprietary information and trade secrets of ATI Technologies Inc. No part of this document may be used, reproduced, or
`transmitted in any form or by any meanswithout the prior written permission of ATI Technologies Inc.
`
`ATI Ex. 2064
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` "iL
`
`|
`Page 2 of 22
`wine §=ATI Technologies Inc.
`
`PLL Clock Synthesizer for High-Speed Digital Circuits
`
`Revision History
`
`Revision
`Date
`Author
`Remark
`
`a2
`June 19,
`Karen Wan
`Changed the minimum input frequency range from 2MHz to 6.7S5MHz
`2001
`
`01
`
`October 25,
`2000
`
`Karen Wan
`
`Added output clock 3 and inverter function for the output clocks. Changed the
`frequency range from 200-400MHz to 300-800MHz
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Gover Page.
`Printed on Feb 28 2001 6:13:00 PM
`
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`

`

`PLL Clock Synthesizer for High-Speed Digital Circuits
`@|
`
`
`
`
`_ ATi TechnologiesInc.
`Page 3 of 22
`
`Table of Contents
`
`INCFOCUCHION. 00. ceeee ceases teeter nee nienii enti nnnneeiieeneeneceneeeeeeeeeeeeeenensessneeees 4
`
`Functional Requirement...........:::cccccccceessseeseeeeeessceesseneeeseeesasnneeeeesssanauess 6
`
`Electrical and Physical Requirements.................2.::::::::::seeeeeeeeeeeeeeeeeeees 13
`
`Qualification Plan .............c.:.ccccccceeeeeeeeeeenessseeeeeeeeeeeeeeeeeenssseneeeeeeeeeeeeeeenees 18
`
`Production Test Plan.............ccccccceeceeeeecceeeceeeeeeeeeeeeeeesseeseeeneeeeeeeeeneeeeeeees 19
`
`Circuit Design Guideline ............ eee ccceeecseeeeeeeeeeeeeeeeeeeesseeeeeeeeeeeeeeeeenees 19
`
`RTL Design and Behavioral Modeling Guideline....................:::ceeee 20
`
`Place and Route Guideline .............ccccccsesecceeeeeeeeeeeeeeeeseeeeeeeeeseeeeeeeneseneees 21
`
`Package DeSign Guideline................c::cceeccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeenseees 22
`
`PCB DeSiQn Guideline..........ccccccceessseeeeeeeeeeeereiieeeeeecceneeieeeeeaneeeeesceneees 22
`
`BIOS/Software Programming Guideline ..........cccesceeseeereeeeeeeeeeeeeeeeeee 22
`
`
`
`ATI TechnologiesInc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Feb 28 2001 6:13:00 PM
`
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`

`@|
`PLL Clock Synthesizer for High-Speed Digital Circuits
`
`
`
`
`ATI Technologies Inc.
`Page 4 of 22
`
`Introduction
`
`is designed to provide the hardware design teams with the technical
`This document
`specifications required by a fully integrated PLL-based clock synthesizer for high-speed
`digital circuits to meet ATI’s future product requirements. The use of standard 0.15um single-
`gate-oxide 1P7M digital CMOS process with 1.8Vig power supply is a stated requirement for
`this class of products. The clocking solution will provide synchronous pipelined logic clock
`frequencies from 300 to 800MHz in minimum steps of 6.75MHz.
`
`This specification is intended to provide circuit designers a well-defined and measurable
`design target that will meet the system-level clocking requirements. While the focus of this
`documentis on functionality and electrical and timing parameters, verification procedures at
`different design stages are also covered in detail to ensure sufficient
`level of testability.
`Finally,
`the design guidelines for other development and qualification groups place the
`documentin a system-level context.
`
`This specification provides a baseline of development for the clocking requirements in future
`ATI products. It is not the only implementation that can be developed; however, this baseline
`functionality is required for most systems.
`
`Note: The PLL specified in this document may not be suitable for video displaycircuitry.
`
`Key Features
`
`e
`
`Input reference frequency ranges from 6.75 to 9MHz
`
`e VCO frequency ranges from 300 to 800MHz
`
`e
`
`e
`
`e
`
`Less than 50ps cycle-to-cycle, and 200ps peak-to-peak jitter with 100mVpp sinusoidal
`supply ripple
`
`Fully integrated with built-in self-biasing circuitry
`
`Less than 8mAaverage current consumption under nominal conditions
`
`e Designed using standard 1.8Vtg, 0.15um single-gate-oxide digital CMOS process
`
`Phase-Locked Loop Overview
`
`Today’s ASIC usually derives its internal clocks from an off-chip discrete component such as
`crystals
`or oscillators
`running
`at
`some standard frequencies
`(common ones
`are
`14.31818MHz and 29.498MHz). In order to meetthe different timing requirements of different
`logic blocks independent of the source frequency, integrated PLL-based clock synthesizers
`are used to generate the frequency-multiplied clocks required by the high-speed digital
`circuitry.
`
`A typical clock synthesizer system is composed of 4 components: a phase-locked loop (PLL)
`and 3 frequency dividers. When connected in a feedback configuration as shown in the
`following diagram, the PLL be used to generate a clock signal that is a rational multiple of the
`source clock.
`
`
`
`ATI Technologies Inc. Confidential. Reference Copyright Notice on Cover Page.
`
`Printed on Feb 28 2001 6:13:00 PM
`
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`

`@|
`PLL Clock Synthesizer for High-Speed Digital Circuits
`
`
`
`
`ATI Technologies Inc.
`Page 5 of 22
`
`
`
`
`Reference
`
`
`Divider
`
`
`
`
`
`Post
`Divider H-— fost
`1/P
`
`
`
`
`
`
`1/M
`
`Feedback
`Divider
`4IN
`
`e Figure 1: Clock Synthesizer System
`
`The front-end of the PLLis a phase/frequency detector (PFD) that continuously monitors and
`compares the phaseof the clock signals appeared at the two input ports, R (for reference)
`and F (for feedback). Upon detecting any difference, it will adjust the frequency