December11, 2002
`
`‘R400 Program Review
`
`ATI Corporate Presentation
`
`AMD1044_0188919
`
`ATI Ex. 2061
`IPR2023-00922
`Page 1 of 11
`
`
`
`‘R400 Program Review
`
`ATI Corporate Presentation
`
`AMD1044_0188919
`
`ATI Ex. 2061
`IPR2023-00922
`Page 1 of 11
`
`
`
`Orlando Hardware Status
`
`@ CP /RBBM/VGT/PA/SC/SC_B 100% coded
`
`@ Gate Level simulations ofall blocks started
`
`@ Synthesis / Timing improvements in process
`
`6/14/2047
`
`@ Real Time Streams implemented
`e@ Status: Passed first RTS and mixed NRTS/RTStest
`
`@ Code Coverage results being reviewedfor feedback to
`Validation team
`
`vd
`CONE|DENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0188920
`
`ATI Ex. 2061
`IPR2023-00922
`Page 2 of 11
`
`
`
`Synthesis Results
`
`BLOCK
`
`PA
`
`VGT
`
`SC
`
`Synth Date
`Code Version
`
`Worst Timing
`#>1.00nS
`
`#>0.50nS
`
`#>0.20nS
`
`#> 0.00 nS
`
`Total Neg Slack
`Wireload
`
`CellArea (sqmm)
`
`Macro Area (sqmm)
`
`Dec 11, 2002
`
`Dec 9, 2002
`
`Dec 10, 2002
`
`NIA
`
`-0.33
`
`0"
`
`o"
`
`62°
`ee/
`
`81.1
`
`N/A
`
`-0.17
`
`0”
`
`0”
`
`0”
`
`440"
`
`25.7
`
`N/A
`
`0.850
`
`0.385
`
`N/A
`
`-0.14
`
`0”
`
`o”
`
`o*
`
`709°
`
`41.0
`
`N/A
`
`3.377
`
`0.899
`
`SC_B
`Dec 4, 2002
`
`N/A
`
`-0.01
`
`cP
`
`Dee 10,2002
`
`Dec 3, 2002
`
`N/A
`
`N/A
`
`-0.09
`
`9.2
`
`N/A
`
`BTS
`
`1.855
`
`N/A
`
`3.600
`
`0.000
`
`0.146
`
`0.124
`
`Total Area (sqmm)
`s¢_b tyumm
`yyt_tsumm
`
`cp Summ
`Timing Summarylink (.tsumm)
`3
`cp
`.
`yat_reflogrhbmreflogs_b_reflog
`CONFIDENTIAL
`Area Summary link (.reflog)
`s¢_.reflog
`6/14/2047
`
`1.235
`
`4.276
`
`3.600
`
`4.580
`
`0.271
`
`0; RBBM
`
`sotswmm pbbm teu
`
`
`
`
`
`
`
`ATI Corporate Presentation
`
`AMD1044_01889271
`
`ATI Ex. 2061
`IPR2023-00922
`Page 3 of 11
`
`
`
`complete by 12/20
`
`Reeeehepabadelieaind
`eee
`
`TT crEC eer
`EERcreed Tocty AitonOm Actos! Testy
`
`Winton
`
`eee eeeTe ety
`Deheeey
`
`@ 80% of the planned
`tests written
`
`Current suite covers
`100% of planned
`features (awaiting
`coverresults)
`
`Remaining tests are
`largely stress test
`... expect to
`
`Test Suite Development(PA,VGT, SC)
`
`ae
`eres
`
`Lied
`i eLDeeea
`ce
`corer
`
`ATI Corporate Presentation
`
`AMD1044_0188922
`
`ATI Ex. 2061
`IPR2023-00922
`Page 4 of 11
`
`
`
`Block Validation
`
`@ Block Level Test Regressions
`
`
`Tests Run|Tests Pass % Pass
`
`VGT
`
`2308
`
`2308
`
`100%
`
`12/09/02
`
`
`
`po
`px|as00|zac|os|varone
`
`@ Block Level Random Testing
`e@ VGT/PA/ SC Block Randoms coded & passing 100%
`@ PA/ SC Chip Randomspassing
`@ VGT/CP Chip Randomsstarted
`
`)
`CONEIDENTIAL
`Janie rd
`
`ATI Corporate Presentation
`
`AMD1044_0188923
`
`ATI Ex. 2061
`IPR2023-00922
`Page 5 of 11
`
`
`
`Issues / Risks
`
`@ Synthesis Timing Closure (CP/RBBM/PA/VGT/SC/SC_B)
`@ Real-time stream validation: Checkers at GC/Full Chip level
`Block level Performance
`
`Janie rd
`
`@ Integrated Performance
`@ SC -> SQ/SP/SX (SP Buffer Size increase potential)
`@ PM4 Packet dumps needed for performancetesting /
`and feature validation
`
`@ 3dMark03, UT03, Doom3
`@ Full chip / GC validation ramping now
`@ Pipe Disable Validation for Quickturn
`@ Configuration Testing (ie ... pipe disable, one Quad/clk,
`walking orderwithin tile, packer optimized, # clip
`controllers, fifo size, linear/tiled, clock gating)
`
`5
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0188924
`
`ATI Ex. 2061
`IPR2023-00922
`Page6 of 11
`
`
`
`Christeen Gray
`
`ull Chip Validation
`
`ATI Corporate Presentation
`
`AMD1044_0188925
`
`ATI Ex. 2061
`IPR2023-00922
`Page7 of 11
`
`
`
`
`
`
`
`
`Chip Validation Status
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`@ GFX (fullchip) and System (chip_vidfull) Simulations
`are now parts of parts_lib release mechanism ...
`stabilizes nightly builds
`@ Toplevel clean up activity underway
`@ Force all interconnecting nets to be driven or removed
`@ Connectall scan, debug, memory test signals
`@ Clean up warnings on size mismatches of connecting signals
`@ Nightly regressions running for chip testing for GFX
`(Orlando) and System (Toronto) blocks
`@ System Test Plan drafted ... describes:
`°
`BASIC SYSTEM TESTS - these are simple initialization tests, register read/write
`tests, testing functionality that must be tested at the chip level (such as power,
`reset, clocks, scan tests, chip id test, etc ...)
`CONCURRENCY-STRESSTESTS - thesetests are enabling multiple engines,
`testing synchronization mechanisms (rts/nrts), stressing arbiters in the design.
`PERFORMANCETESTS -— These tests are measure and predict performance for
`all areas identifiedin the MRD, and any performance measurementsrelative to me
`current industry standard performance applications. (see
`
`doc_lib/verification/PV.doc)
`
`
`
`
`4
`Sans
`
`e
`
`°
`
`ATI Corporate Presentation
`
`AMD1044_0188926
`
`ATI Ex. 2061
`IPR2023-00922
`Page8 of 11
`
`
`
`Chip Validation Status (cont’d)
`
`@ Shifting emphasis from blocklevel validation to GC/Chip
`level testing
`@ Orlando now has 4 engineers running / debugging chip
`level tests
`
`@ Toronto increased numberof chip tests being run
`@ Environment enhancementsstill in works
`
`Janie rd
`
`@ Makefile enhancements to support parameterized tests
`@ Continue to add monitors / checkers at hardware
`interfaces to support faster chip level debugging/
`performanceverification
`Progressis slow but steady
`
`i)
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0188927
`
`ATI Ex. 2061
`IPR2023-00922
`Page 9 of 11
`
`
`
`Chip Validation Status (cont’d)
`
`@ Orlando Full Chip Validation:
`
`
`
`Tests
`
`Tests
`
`#Planned #ExpectedRun #Passing (Passing)
`
`Tests Written|Passing Eripiste
`
`Total
`
`*focus on environment enhancements / build stability / clean up
`@ Toronto Full Chip Validation
`Overall Block Statistics
`Sssssssssssses==
`
`TestBlock
`
`dcp_engine
`
`SIM
`
`10
`CONEIDENTIAL
`Jaret rd
`
`dcp_graphics SIM
`
`dep_overlay SIM
`
`ATI Corporate Presentation
`
`AMD1044_0188928
`
`ATI Ex. 2061
`IPR2023-00922
`Page 10 of 11
`
`
`
`
`
`ATI Corporate Presentation
`
`AMD1044_0188929
`
`ATI Ex. 2061
`IPR2023-00922
`Page 11 of 11
`
`
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