`Block Status
`
`Block
`
`% Feature Complete
`
`Estimated
`completion date
`
`
`
`smn
`
`
`MH
`
`RB
`
`RC
`
`SX
`
`99%
`
`95%
`
`99%
`
`98%
`
`10/18
`
`10/31
`
`10/18
`
`10/18
`
`10/18
`99%
`TP
`
`
`s|
`CONEIDENTIAL
`CIEEvat eg
`
`
`
`CGICGM 100% |DBG/ROM
`
`ATI Corporate Presentation
`
`AMD1044_0186744
`
`ATI Ex. 2043
`IPR2023-00922
`Page 1 of 5
`
`ATI Ex. 2043
`
`IPR2023-00922
`Page 1 of 5
`
`
`
`Marlboro Hardware Design
`Block Status
`
`- All blocks need to add
`— performance counters
`— power
`— debug registers
`— Star memories
`
`- MC
`
`CONEIDENTIAL
`
`
`— Pad Interface
`— At speed sw generated commands
`— Synthesis target ofS|0OOMHz
`- MH
`— Register updates in progress
`— Tiled surfaces in system memory support not started
`
`2
`
`ATI Corporate Presentation
`
`AMD1044_0186745
`
`ATI Ex. 2043
`IPR2023-00922
`Page 2 of 5
`
`ATI Ex. 2043
`
`IPR2023-00922
`Page 2 of 5
`
`
`
`Marlboro Hardware Design
`Block Status
`
`- RB
`
`— Depth and multi-sample logic still in design
`— Resolve and memory export logic not yet started
`- SQ
`
`
`
`
`— Control flow in progress
`+
`(conditionals, loops, jumps, ...)
`- SP/ SX
`
`— Memory export
`
`3
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0186746
`
`ATI Ex. 2043
`IPR2023-00922
`Page 3 of 5
`
`ATI Ex. 2043
`
`IPR2023-00922
`Page 3 of 5
`
`
`
`Marlboro Hardware Design
`Block Status
`
`TP LTS
`
`CONEIDENTIAL
`
`
`— 512 bit AGP requests
`— degamma with DXTC texels
`- CG/CGM/DBG/ ROM /IO
`
`— DFTlogic in progress
`— Temperature sensor logic
`
`ey
`
`ATI Corporate Presentation
`
`AMD1044_0186747
`
`ATI Ex. 2043
`IPR2023-00922
`Page 4 of 5
`
`ATI Ex. 2043
`
`IPR2023-00922
`Page 4 of 5
`
`
`
`Block Synthesis
`
`- Update ...
`
`CIEEvateg
`
`
`i)
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0186748
`
`ATI Ex. 2043
`IPR2023-00922
`Page 5 of 5
`
`ATI Ex. 2043
`
`IPR2023-00922
`Page 5 of 5
`
`
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