`
`I/O Pads
`
`¢ Silicon Valley has committed to creating the pads and the
`pad ring for R400
`- Padswill be based off of RV350 pads
`-- Memory padswill have to be modified to support DDR3
`- R400 has 664 signals and using the 80p X 350 pad pitch yields
`a pad limited die of 13.98 mm
`- This does not include any power, ground,transition, or bonding
`pads that are needed
`
`[DateTime]
`
`€ RADEON ?
`
`AMD1044_0185547
`
`ATI Ex. 2041
`IPR2023-00922
`Page 1 of 8
`
`
`
`I/O Pad Schedule
`
`a,=~Crna ?
`
`Initial verilog delivery for pads and near pad logic - Rv350 based
`model 8/16
`Initial LEF, TLF, Synopsys models - Rv350 based model 8/16
`Initial IKOS and Sunrise models 9/1
`Final verilog delivery for pads and nearpad logic - 11/1 R400
`specific
`Final LEF, TLF, Synopsys models - 12/1
`Final
`IKOS and Sunrise models - 12/1
`
`Clean GDSofindividual cells - 12/21
`Clean GDSofentire ring - 1/1
`Integrate ring into full chip and start full chip DRC/LVS -1/15
`
`AMD1044_0185548
`
`ATI Ex. 2041
`IPR2023-00922
`Page 2 of 8
`
`
`
`Chip Integration
`
`Crna ?
`
`Rom Controller/CG/CGM/Debug Bus:
`Block Testing Completed
`Regression Test Plan Created
`33% of regression test completed
`Eric is in process of bringing up full chip simulation environmentto start
`running regressions on these items
`Pad Out
`
`Initial Ball Out has been created basedoff of the R300 package
`39 X 39 will still be used, but needed to move someinnerball rings to
`outside for signal integrity grounds
`Ball out is being reviewed by various groupsincluding the board group
`Pad out is underway
`
`AMD1044_0185549
`
`ATI Ex. 2041
`IPR2023-00922
`Page 3 of 8
`
`
`
`Chip Integration
`
`¢ Modified the clock gater modules to have
`programmable windows
`¢ Chip ID’s, personality bits, harvesting bits
`will be defined and implemented in the next
`two weeks
`
`7
`
`[DateTime]
`
`RADEON
`
`9
`
`AMD1044_0185550
`
`ATI Ex. 2041
`IPR2023-00922
`Page 4 of 8
`
`€
`
`
`Chip Level Netlist
`
`¢Afull chip initial netlist was delivered 8/3
`* Toronto physical design group place and routedall block
`based on bound boxesand delivered wireloads models.
`
`RADEOM [DateTime]
`
`« This uncovered a numberor processissues and a design
`compiler issues that are being addressed
`¢ Next major release will be at the end of September, however
`incremental release will take place as a result of the physical
`design process
`
`.
`
`9
`
`AMD1044_0185551
`
`ATI Ex. 2041
`IPR2023-00922
`Page 5 of 8
`
`€
`
`
`DFT —- Memory and Repair
`
`a ta pe pet
`
`Virage has continually slipping their deliverables andit
`appears whatthey delivered on 8/14 is not all together.
`Basically we have an assortmentof pieces from various
`process types
`» They are introducing new pieces of the memory test system.
`The Register File Compiler appear to be okay
`The High Density memory is not okay
`The Star Processorandit associated pieces only work LV
`Need to push on masking configurations
`Virage is proposing a 9/23 date to get this sorted out.
`
`*'
`
`AMD1044_0185552
`
`ATI Ex. 2041
`IPR2023-00922
`Page 6 of 8
`
`
`
`Design for Test
`
`RADEOM
`
`Finally starting to move resources to R400
`TetraMax versus FastScan has been completed and
`currently analyzing the data
`¢ Initial Specification for test controller is complete
`Eric is going to work on the RTLforit
`Near Near Padtest logic need to specified next month
`Experiment with ILM scan insertion will take place next
`month.
`
`9
`
`AMD1044_0185553
`
`ATI Ex. 2041
`IPR2023-00922
`Page 7 of 8
`
`€
`
`
`Concerns
`
`- Clocking system
`
`* Virage
`- Pulling together Star System
`- Test Chip problems
`— Memory repair process
`Many issuesare not being addressoronly being givinglip
`service due to the lack of people to work them
`- Memory Controller to Pad interface
`- Analog IP and otherissues
`- DFT scan process development
`- Getting ready for physical design
`
`AMD1044_0185554
`
`ATI Ex. 2041
`IPR2023-00922
`Page 8 of 8
`
`
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