Feb 12, 2003
`
`~ R400 Program Review
`
`AT! Corporate Presentation
`
`AMD1044_0170634
`
`ATI Ex. 2032
`IPR2023-00922
`Page 1 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 1 of 11
`
`
`
`~ R400 Program Review
`
`AT! Corporate Presentation
`
`AMD1044_0170634
`
`ATI Ex. 2032
`IPR2023-00922
`Page 1 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 1 of 11
`
`
`
`
`Target Milestones in Last Month
`
`- Toronto R400 revised milestones
`> Deliver IDCTfinal netlist by Jan 24
`>» Achieve DC 100% passing in chip level regression by
`Jan 30
`
`> IKOS validation on netlist 3.0.
`> Achieve DC timing goals by Jan 30.
`> Deliver DC final netlist by Feb 15.
`> Start Gate level simulation in Jan.
`> Close bif timing & existing tests issues by 1/30.
`> Deliver BIF final netlists by Feb 28
`
`
`
`HY
`
`
`
`
`
`
`
`
`vd
`CONEIDENTIAL
`
`
`
`
`
`AT! Corporate Presentation
`
`AMD1044_0170635
`
`ATI Ex. 2032
`IPR2023-00922
`Page 2 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 2 of 11
`
`
`
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`What Have We Achieved
`
`
`
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`
`
`
`
`
`
`
`
`- Status Summary
`Y Delivered final idct netlist on Feb 5 with meeting timing
`target & validation target. Although there are 4 chip level
`tests failing we believeit is not idct issue.
`v Achieved 84% chip level regression passing.
`Y Register cycles passing on ikos with netlist 3.0 but having
`problems with memory interface.
`¥Y Worked out DC synthesis issues with Rob andthe cell
`count is reduced to 382k from 400k and the worsttiminig
`violation is down to —0.15ns.
`Y 98% existing bif tests passing in emulation with a number
`of 2D related tests failing, while 30% existing bif tests
`passingin chip level simulation
`v Bif new feature related emulation workto follow.
`
`
`
`
`Ki}
`CONEIDENTIAL
`SrAv4 Ya
`
`
`
`
`AT! Corporate Presentation
`
`AMD1044_0170636
`
`ATI Ex. 2032
`IPR2023-00922
`Page 3 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 3 of 11
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`
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`SrAv4 Ya
`
`What Have WeAchieved
`
`(specs: coding, emulation, tests)
`
`Spec is 100% complete in display & idct while bifis 98% complete:
`+ Coding is 100% complete.
`+ Emulation is 100% completed with vga(tiled mem dump) and bif outstanding.
`- Tests are 100% released with 10% bif & system tests outstanding.
`
`RTL
`
`Tests
`
`specs
`100%
`100%
`
`coding Emulation Written
`100%
`100%
`100%
`100%
`
`100%
`
`100%
`100%
`100%
`100%
`100%
`
`100%
`
`100%
`100%
`100%
`100%
`100%
`
`100%
`
`100%
`100%
`
`100%
`
`100%
`
`100%
`
`100%
`
`WocT||100%
`100%
`100%
`4
`CONEIDENTIAL
`
`AT! Corporate Presentation
`
`AMD1044_0170637
`
`ATI Ex. 2032
`IPR2023-00922
`Page 4 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 4 of 11
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`
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`What Have We Achieved
`(block RTL regression)
`
`- All blocks are 100% passing
`
`Block Rregression 1/30
`
`
`
`
`
`
`
`
`numberoftests
`
`
`
`
`
`
`
`@ tests passing
`@ tests written
`B@ tests planned
`
`5
`CONEIDENTIAL
`SrAv4 Ya
`
`
`
`AT! Corporate Presentation
`
`AMD1044_0170638
`
`ATI Ex. 2032
`IPR2023-00922
`Page 5 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 5 of 11
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`
`
`Overall 84% passed on chip level
`Dep, crtc, vip all have above 90% passing. The remainingfailures are mainly
`dueto test issues, networkglitches & environment problems.
`+ Vga is gated by tiled memory dump while bif is gated by mh interface issues
`on 64byte write.
`System tests are to be focused next
`Chip Regression 219/03
`
`HY
`
`What Have WeAchieved
`(Chip regression)
`
`numberoftests
`
`nNoao
`
`450
`
`
`
`tests passing
`tests written
`
`tests planned
`
`SrAv4 Ya
`
`6
`CONEIDENTIAL
`
`System — 10%
`
`Crtc — 95%
`Dep — 93%
`Lb - 63%
`
`Scl — 85%
`- Dispout - 76%
`Tvout — 78%
`- Vga—10%
`Vip — 98%
`Bif — 15%
`
`Idct — 94%
`
`AT! Corporate Presentation
`
`AMD1044_0170639
`
`ATI Ex. 2032
`IPR2023-00922
`Page6 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 6 of 11
`
`
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`
`
`
`
`What Have WeAchieved
`(Chip regression emulation)
`- Most emulations and tests are 100% COMPlEtEMIrrr
`* vga is mainly due to tiled memory dump issue. Weplan to
`resolve emulation issue & start chip regression next week
`- Bif emulation issues remains to be 2D related tests failures &
`
`
`
`
`newfeature implementations. Chip emu Tests
`
`regress
`
`Tests
`Tests
`passing Released Planned
`
`vf
`CONEIDENTIAL
`6/2/2047.
`
`AT! Corporate Presentation
`
`AMD1044_0170640
`
`ATI Ex. 2032
`IPR2023-00922
`Page 7 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 7 of 11
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`
`
`- IDCTis finalized and meet the speed_target. ——
`
`What Have WeAchieved
`(Area & Timing)
`
`
`- DC gate count is down to 380k and the worstviolation is down
`to
`—0.05ns
`- BIF’s timing issue are due to design changes andtheefforts will
`be af place after the validation is completed,ie. within 1 — 2
`
`
`
`
`weeks.
`
`
`
`Speed (ns) Violation (ns)
`2.25
`2.25
`2.25
`2.25
`2.25
`Area (mm2)
`2.25
`Cell Count
`2.25
`Timing
`2.25
`
`2.25 Path Groups|Speed(ns) Violation (ns);
`2.25
`SCLK_G_DCT
`2.25
`0
`2.25
`2.25
`
`nC) |
`
`Speed (ns) Violation (ns)
`-0.58
`
`1.23
`72K
`
`
`
`b]
`CONEIDENTIAL
`SrAv4 Ya
`
`AT! Corporate Presentation
`
`AMD1044_0170641
`
`ATI Ex. 2032
`IPR2023-00922
`Page8 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 8 of 11
`
`
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`Next Set of Goals:
`>» Achieve DC 100% passing in chip level
`regression by Feb 28
`>» Focus on debugging system tests
`> Deliver DCfinal netlist by Feb 28 (need to
`work with mh to achieve the target)
`> Display IKOSvalidation on netlist 4.0 for
`vga, display & tvout features
`> Close bif existing tests issues by 2/28.
`> Closebif timing and newtests issues by Mar
`20 (need to work with mh to achieve the
`target)
`
`
`
`
`
`
`What’s ahead?
`
`
`
`9
`CONEIDENTIAL
`
`AT! Corporate Presentation
`
`AMD1044_0170642
`
`ATI Ex. 2032
`IPR2023-00922
`Page 9 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 9 of 11
`
`
`
`Needall sites to strictly follow release process.
`
`
`
`
`
`
`
`
`
`Issues
`
`
`
`
`
`
`Chip level regression:
`>» DC chip level validationis still mainly gated by mh-dc
`interface related issues, with 3 to 5 daysofthe turn
`around time from bug report to the release ofthefix.
`> BIF chip validation issues:
`» 6 legancytests failing due to 2D functionality,
`need help to debug
`» Overall regression passingrate fell from 50% to
`15% due to
`» bif-mh interface related issues: MH_HI_hdp_clean & agp 64byte
`write.
`
`» a delay insertion somewherelikely in |O that causes data
`missing.
`> Continue to experience disruptions on chip build.
` alt)
`CONEIDENTIAL
`SrAv4 Ya
`
`AT! Corporate Presentation
`
`AMD1044_0170643
`
`ATI Ex. 2032
`IPR2023-00922
`Page 10 of 11
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 10 of 11
`
`
`
`CONEIDENTIAL
`
`ob
`
`Risks
`MH bug fixes has beenthe bottleneck for chip
`regression.
`— Need Marlboro MH team to increasetheir priority in
`resolving these issues
`Marlboro’s RTL code releasing process has been
`ranging from 3 to 5 days before it get released.
`— This is critical in resolving chip issues quickly.
`— Currently, DC & BIF progress is being slow down
`on chip regression.
`The next step is to get IKOS running with display
`— This again require MH/MC issues and bugs to be
`resolved
`Split DC may impact the final delivery schedule of DC
`up to 3 to 4 weeks.
`Continuing updates on Virage memorieswill impact the
`schedule of DC as we need models to be built for lut.
`
`|
`
`AT! Corporate Presentation
`
`AMD1044_0170644
`
`ATI Ex. 2032
`IPR2023-00922
`Page 11 of 14
`
`ATI Ex. 2032
`
`IPR2023-00922
`Page 11 of 11
`
`
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