`
`Added 3 new packets for improved type-0 packet processing:
`
`IncrementalUpdateState/Const/Instr
`
`Change 137750 on 2003/12/16 by fliljero@fl_knarf
`
`Added optimized Event_Write* packets & new opcodes
`
`Change 137101 on 2003/12/12 by fliljero@flfrank
`
`Added Wait_Reg_Eq & Wait_Reg_Gte PM4 packet descriptions
`
`Change 137025 on 2003/12/11 by fliljero@fl_knarf
`
`updated documentation on error checking and removed reference to type-l packet.
`
`Change 136800 on 2003/12/10 by fliljero@fl_knarf
`
`Updated description for MEM_WRITE_CNTR to include how to change the core clock interval
`from 1 <--> 16.
`
`Change 136780 on 2003/12/10 by fliljero@fl_knarf
`
`Updated Me_Init packet for Header Dumps & Error checking...added note about recompiling
`microcode to enable these debug only features.
`
`Change 136762 on 2003/12/10 by fliljero@fl_knarf
`
`Updates related to CPMEQ
`
`Change 136302 on 2003/12/08 by fliljero@fl_frank
`
`Updates to MEQ related registers & busy signals
`
`Change 135746 on 2003/12/05 by fliljero@fl_knarf
`
`Updated CP Interrupt packet for performance
`
`Change 134564 on 2003/12/01 by fliljero@fl_knarf
`
`Max Buffer Size in Indirect Buffer Packets is [19:0]...Spec had [22:0]
`
`Change 130037 on 2003/11/04 by fliljero@fl_knarf
`
`Added registers and PM4 packet changes related to the Software Managed Instruction
`Store...
`
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`Change 124599 on 2003/10/02 by fliljero@fl_knarf
`
`no change
`
`Change 123990 on 2003/09/30 by fliljero@fl_knarf
`
`added changes to setstate and load_constant_context
`
`Change 123315 on 2003/09/25 by fliljero@fl_knarf
`
`Updated Const_Prefetch packet to issue only once per LCC packet. When the LCC ordinals
`
`they also repeat in the Const_Prefetch packet.
`repeat,
`Const_Prefetch packet for each repeat of the ordinals.
`
`Formerly,
`
`there was a new
`
`Change 123064 on 2003/09/24 by fliljero@fl_knarf
`
`Updated SubblkPrefetch packet to send the Header only once,
`each ordinal on a mismatch.
`
`followed optionally by
`
`Change 122800 on 2003/09/23 by fliljero@fl_knarf
`
`made drawing change to reflect changes to SRCO & SRC1 removal of MICROM, MRL & MRM as
`possible sources.
`also removed the BOOLEANs as a possible source for SRCl.
`
`Change 120795 on 2003/09/11 by fliljero@fl_knarf
`
`added zpassdone info to the event_write packet
`
`Change 120303 on 2003/09/09 by fliljero@fl_knarf
`
`added predicated bin test results (RT/nRT)
`
`to State Management register w/index=0xD
`
`Change 120271 on 2003/09/09 by fliljero@fl_knarf
`
`Update Event Write packet for new functionality for the zpassdone event ... clears the
`context valid flag, which in turn will cause the context to be rolled on the next state
`
`packet.
`
`Change 119939 on 2003/09/08 by fliljero@fl_knarf
`
`added 128-bit write enable to the MH field to the CP_DEBUG register.
`
`Change 119726 on 2003/09/05 by fliljero@fl_knarf
`
`added predicatedisable bit to CP_DEBUG
`
`Change 119667 on 2003/09/05 by fliljero@fl_knarf
`
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`removed DATA ordinal from the MEMWRITECNTR packet description
`
`Change 119663 on 2003/09/05 by fliljero@fl_knarf
`
`added MEMWRITE_CNTR opcode
`moved SET_BIN_MASK/SELECT opcodes to unused locations
`
`Change 119301 on 2003/09/03 by fliljero@fl_knarf
`
`made updates to the event write packet and added new associated register:
`
`CP_MECF_EVENT_SRC
`
`Change 119223 on 2003/09/03 by fliljero@fl_knarf
`
`added CP_PROGCOUNTER,
`related update to CPMECNTL,
`
`related update to EVENT_WRITE packet,
`
`&
`
`related new PM4 packet MEMWRITECNTR
`
`Change 118709 on 2003/08/29 by fliljero@fl_fliljeros
`
`added real-time versions of the predicate registers: BINMASK & BINSELECT
`
`Change 118408 on 2003/08/27 by fliljero@fl_knarf
`
`updated/added coherency registers and interface
`
`updated/added predicate registers and description
`
`Change 118362 on 2003/08/27 by fliljero@fl_knarf
`
`added type-3 predicated packet related information
`
`Change 115561 on 2003/08/08 by fliljero@fl_knarf
`
`renamed references from R400 to Crayola
`
`Change 115547 on 2003/08/08 by fliljero@fl_knarf
`
`Removed all references to PIO/Push mode and its associated registers:
`
`CP_CSQ_CNTL
`
`CP_ 'RING |
`
`INDIRECT1L |
`
`INDIRECT2 | REALTIME |
`
`IBST | RT_ST' PUSH
`
`Change 115546 on 2003/08/08 by fliljero@fl_knarf
`
`renamed to use Crayola rather than R400
`
`Change 115463 on 2003/08/07 by fliljero@fl_knarf
`
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`Baseline for the PM4 Spec (after the start of Xenos)
`
`Change 115462 on 2003/08/07 by fliljero@fl_knarf
`
`added note to cover to see PM4 Spec Crayola for the latest PM4 data
`
`Change 115461 on 2003/08/07 by fliljero@fl_knarf
`
`Baseline for Crayola CP Spec (after the start of Xenos)
`
`Change 115460 on 2003/08/07 by fliljero@fl_knarf
`
`added note on cover to see CP Spec Crayola for the latest CP data.
`
`Change 114564 on 2003/08/01 by aashkar@aashkar2_crayola_win
`
`Updated Spec with the addition of bit 19 in the interrupt registers for the software
`
`interrupt
`
`(SW_INT). This interrupt is moving to the CP from the MH.
`
`Change 108824 on 2003/07/02 by jacarey@fl_jcareydesktop
`
`Update Min / Max functions in emulator to match hardware.
`Hardware produces a 32-bit signed extended result of 16-bit comparision value.
`
`Change 108680 on 2003/07/01 by jacarey@fl_jcarey_desktop
`
`Add section documenting CP Idling before writing certain control registers.
`
`Change 104633 on 2003/06/06 by jacarey@fl_jcarey_desktop
`
`Document resetting of read registers to zero on reset.
`
`Change 104324 on 2003/06/05 by jacarey@fl_jcareydesktop
`
`Reset VS & PS De-alloc fifos when ME overwrites the *AvailCount counters
`
`Change 104014 on 2003/06/04 by jacarey@fl_jcareydesktop
`
`Documentation for new debug bit in the CP.
`
`Change 103099 on 2003/05/29 by jacarey@fl_jcareydesktop
`
`Added oper=comp to document.
`
`Change 101923 on 2003/05/21 by jacarey@fl_jcareydesktop
`
`Clarification that Isyne flushing occurs only before the first “draw" packet after the
`transition.
`
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`Change 101800 on 2003/05/20 by jacarey@fl_jcareydesktop
`
`Correction to Gradfill prim type for rectangles.
`
`Change 101625 on 2003/05/19 by jacarey@fl_jcareydesktop
`
`Miscellaneous Corrections to documents w.r.t. 2D Coherency Rectangle Updates.
`
`Change 101380 on 2003/05/16 by jacarey@fl_jcareydesktop
`
`Clarifications to pre-write-timer and pre-write-limit usage.
`
`Change 100945 on 2003/05/14 by jacarey@fl_jcarey_desktop
`
`Clarifications to SetConstant and LCC packets w.r.t. write enables for each CONSTID
`type.
`
`Change 100549 on 2003/05/12 by jacarey@fl_jcareydesktop
`
`Microcode Update for 2D surface coherency
`
`Change 100159 on 2003/05/09 by jacarey@fl_jcareydesktop
`
`Document setting of bit 20 in 2D Booleans as Default_Sel
`
`Change 99510 on 2003/05/07 by jacarey@fl_jcareydesktop
`
`Updates to document for usage of “flush done" flag in the microcode.
`
`Change 99386 on 2003/05/06 by jacarey@fl_jcareydesktop
`
`Update
`
`Change 99380 on 2003/05/06 by jacarey@fl_jcareydesktop
`
`Fix for 2D Coherency (Flushing TC)
`
`Change 98285 on 2003/04/30 by fliljero@fl_frank
`
`latest updates
`
`Change 96875 on 2003/04/22 by fliljero@fl_frank
`
`changed data from one pass to the next to better insure proper validation
`
`Change 96851 on 2003/04/22 by jacarey@fl_jcareydesktop
`
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`
`1. Add detection of Type-0/1 Packets in IBs if Enabled in MEINIT Packet.
`2. Unit-Level Test Added to verify.
`
`3. Update to PM4 Spec to document addition.
`
`Change 96500 on 2003/04/18 by fliljero@fl_frank
`
`latest updates
`
`Change 96403 on 2003/04/18 by jacarey@fl_jcareydesktop
`
`Type 0/1 Error Checking in IBs
`Un-Link Diagrams from PM4 Spec
`
`(ME_INIT, Interrupt Registers)
`
`Change 96286 on 2003/04/17 by jacarey@fl_jcareydesktop
`
`1. Add INVALIDTAG to bit 31 of CPMIUTAGSTAT2 register
`2. Added enumeration for the perfomance counter selects in the CP and RBBM
`
`Change 95964 on 2003/04/16 by jacarey@fl_jcareydesktop
`
`Add new debug registers that record when read tags are outstanding to the CP.
`
`Change 95946 on 2003/04/16 by jacarey@fl_jcarey2
`
`Removed Snooping Connections to DMA Engine from Diagram
`
`Change 95625 on 2003/04/15 by jacarey@fl_jcarey2
`
`Updates to Document
`
`Change 95606 on 2003/04/15 by jacarey@fl_jcarey2
`
`Baseline of Ideas for Pre-emptive Ring Hardware in CP
`
`Change 95512 on 2003/04/14 by jacarey@fl_jcarey2
`
`Miscellaneous Updates
`
`Change 95471 on 2003/04/14 by jacarey@fl_jcarey2
`
`Added some packet restrictions for BitBlt and HostDataBlt:
`
`For HostData_Blt: Never identify a brush even though the ROP code is set to 0xCC
`
`For BitBlt:Never do a simple BitBlt with a mono opaque source, SRC_TYPE=0, or a mono
`
`transparent source, SRC_TYPE=1, and a ROP code set to source copy, OxCC.
`
`Change 95214 on 2003/04/11 by jacarey@fl_jcarey2
`
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`Baseline CP Review Slides
`
`Change 93888 on 2003/04/04 by jacarey@fl_jcareydesktop
`
`Updated Documentation for addition of Pre-Fetch Matching for Loop and Boolean Constants
`
`Change 93664 on 2003/04/03 by fliljero@fl_frank
`
`latest passing updates
`
`Change 93465 on 2003/04/02 by jacarey@fl_jcareydesktop
`
`1. Move RB_CLRCMP_MSK_HI and RB_CLRCMP_DST_HI initialization for 2D to the 2D Indirect
`Buffer
`
`2. Mask for RB_CLRCMPMSKLO is dependant on the pixel type
`3. Updated PM4 Spec Accordingly
`
`4. Updated CP Unit-Level Tests Accordingly
`
`Change 92637 on 2003/03/28 by fliljero@fl_frank
`
`added dummy writes to instruction memory so that it does not return unknowns when read
`
`Change 92381 on 2003/03/27 by dwong@cndwong2
`
`Added CP_RBBM_dma_busy to Bit 2 of the RT discrete signals
`
`Change 92370 on 2003/03/27 by jacarey@fl_jcareydesktop
`
`Fix typo in RBBUFSZ equation in the CP_RBCNTL register
`
`Change 92165 on 2003/03/26 by jacarey@fl_jcareydesktop
`
`Visio Updates to Scratch Register Interrupt Function in the CP
`
`Change 91878 on 2003/03/24 by jacarey@fl_jcareydesktop
`
`Add TestSelect to R400 documentation for the scratch register compare interrupt
`
`Change 91821 on 2003/03/24 by jacarey@fl_jcareydesktop
`
`Scratch Register Interrupt
`
`Change 91540 on 2003/03/21 by jacarey@fl_jcarey2
`
`Scratch Compare Interrupt Diagram for R400
`
`This is the same logic that is being added for R390 as requested
`
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`
`
`by Jeffrey Cheng. The difference from R390 is the location of the
`
`interrupt control and status bits. This is indicated on the diagram.
`
`Change 91474 on 2003/03/21 by jacarey@fl_jcareydesktop
`
`1. Removed PREFETCHDISABLEOVERRIDE from CP_DEBUG register in CP Spec.
`2. Updated PFP pseudocode for IndirectBuffer and IndirectBufferPFD packets.
`
`Change 91209 on 2003/03/20 by jacarey@fl_jcareydesktop
`
`1. Updated bit width of Non-Prefetch counters in the CP_Non_Prefetch_Cntrs register in
`CP Spec.
`
`2. Addition of INDIRECTBUFFER_PFD packet to the PM4 Spec.
`
`Change 90739 on 2003/03/18 by jacarey@fl_jcareydesktop
`
`Add stall conditions for IB2D init w.r.t.
`
`in-flight indirect buffer inits.
`
`Change 90160 on 2003/03/14 by jacarey@fl_jcareydesktop
`
`Another Stall Condition for IndirectBuffer packet
`
`Change 90158 on 2003/03/14 by jacarey@fl_jcarey_desktop
`
`Updated Pseudocode for PREFETCH_DISABLE mode.
`
`Change 90005 on 2003/03/13 by jacarey@fl_jcareydesktop
`
`Updates for Prefetch-Disable Mode to Fetching Indirect Buffers
`
`Change 89739 on 2003/03/12 by jacarey@fl_jcareydesktop
`
`Update to proposal.
`
`Change 89601 on 2003/03/11 by jacarey@fl_jcarey2
`
`Proposal for Pre-Fetch Disabling
`
`Change 89075 on 2003/03/07 by fliljero@fl_frank
`
`latest pass/fail results
`
`Change 88847 on 2003/03/06 by jacarey@fl_jcareydesktop
`
`Fix typo in pm4 spec.
`
`Change 88327 on 2003/03/04 by fliljero@fl_frank
`
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`
`added wait_gfx_idle();
`
`to force synchronization
`
`Change 88312 on 2003/03/04 by fliljero@fl_frank
`
`mem-mapped real-time SQ constant regs moved to a 16 word alignment - from 0x124a0 to
`12500
`
`Change 87776 on 2003/02/28 by fliljero@fl_frank
`
`update
`
`Change 87476 on 2003/02/27 by fliljero@fl_frank
`
`excel spreadsheet to track progress of test run the the ge testbench
`
`Change 86709 on 2003/02/25 by jacarey@fl_jcareydesktop
`
`Initial Baseline
`
`Change 86575 on 2003/02/24 by jacarey@fl_jcarey2
`
`Clarification of write confirm interval as experimental for R400
`
`in the ME_INIT packet.
`
`Change 86415 on 2003/02/24 by jacarey@fl_jcareydesktop
`
`Comment to cpint_cntl register
`
`Change 86390 on 2003/02/24 by jacarey@fl_jcareydesktop
`
`Fix typo in indirect_buffer packet
`
`Change 85294 on 2003/02/19 by fliljero@fl_fliljeros
`
`changed name of regclk_active signal coming from RBBM.
`divided logic cloud into 2 separate clouds for the enables since they do not use the
`
`same logic to generate the enables.
`
`Change 85204 on 2003/02/19 by jacarey@fl_ jcareydesktop
`
`Fix typo for trans_bitblt for clr_cmp_sre fields
`
`Change 85008 on 2003/02/18 by scamlin@scamlin_crayola_win
`
`renamed and added stuff based on PD feedback
`
`Change 83549 on 2003/02/11 by jacarey@fl_jcareydesktop
`
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`
`Allow SRC_H/W != DST_H/W for all AlphaBlend OPs in Microcode
`Updated associated documents.
`
`Change 82508 on 2003/02/06 by jacarey@fljcareydesktop
`
`Update NO Flag for Micro Engine's DMA Engine
`
`Change 82213 on 2003/02/05 by jacarey@fl_jcareydesktop
`
`Correct miscellaneous typo's in the documetn
`
`Change 81860 on 2003/02/04 by jacarey@fl_jcareydesktop
`
`Miscellaneous Documentation Updates
`
`Change 81712 on 2003/02/04 by jacarey@fl jcareydesktop
`
`Update write-only status of microcode read address registers.
`
`Change 81382 on 2003/02/03 by jacarey@fl_jcareydesktop
`
`Add clock gating diagram to spec.
`
`Add note that debug data I/O is asynchronous.
`
`Change 81126 on 2003/01/31 by
`
`fliljero@fl_frank
`
`new drawing for PD team
`
`Change 81080 on 2003/01/31 by
`
`jacarey@fl_jcareydesktop
`
`Fix Typo in ME_INIT packet.
`
`Change 81008 on 2003/01/31 by
`
`jacarey@fl_jcareydesktop
`
`1. Correct Width of Microcode
`
`2. Fix re-ordering queue data
`
`3. Document updates for #1.
`
`RAM read and write registers.
`available determination
`
`Change 80785 on 2003/01/30 by
`
`jacarey@fl jcareydesktop
`
`Clarify that ME_INIT invalidates pointers only if processed in a non-real-time stream.
`This does not happen if it is
`processed in a real-time stream.
`
`Change 80682 on 2003/01/30 by
`
`jacarey@fl_ jcareydesktop
`
`Pseudocode Update #2 for today
`
`Change 80680 on 2003/01/30 by
`
`jacarey@fl_jcareydesktop
`
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`Update MEINIT in Pseudocode Land
`
`Change 80664 on 2003/01/30 by jacarey@fl_jcareydesktop
`
`Reserved bits in CP_DEBUG register are preserved.
`Added default for CP_INTSTAT register.
`
`oOFfWwWMH8eee Update full chip tests for above items.
`
`Add numberdword=0 check for PolyScanLines and HostData_Blt packets.
`Associated documentation updates for above items.
`
`Change 80422 on 2003/01/29 by jacarey@fl_jcareydesktop
`
`Add note to spec regarding the preservation of "reserved" bits in the cp_debug
`register.
`
`Change 79155 on 2003/01/24 by jacarey@fl_jcareydesktop
`
`Clarify update of constant write enables for LCC packet.
`
`Change 78917 on 2003/01/23 by jacarey@fl_jcareydesktop
`
`Fix LCC and Set Constant for incremental register updates.
`
`Change 78658 on 2003/01/22 by jacarey@fl_jcareydesktop
`
`Update for AlphaBlend for ARGB1555 and AlphaSource Blending
`
`Change 78432 on 2003/01/22 by jacarey@fl_jcareydesktop
`
`Fix Typo in Boolean Descriptions
`
`Change 77916 on 2003/01/20 by jacarey@fl_jcareydesktop
`
`Pixel Shader and Microcode to Set B6 for AAFONT packets.
`
`Vertex Shader to ignore B10 for packets with Embedded Source.
`
`mewh‘*6 Associated Documentation for above changes.
`
`- Updated RB_BlendControl Settings for AlphaBlend Packet.
`
`Change 77848 on 2003/01/20 by jacarey@fl_jcareydesktop
`
`Note to PlyNextScan and NextChar packets about required preceeding packets.
`
`Change 77520 on 2003/01/17 by jacarey@fl_jcarey2
`
`Miscellaneous Comments to Registers
`
`Change 77457 on 2003/01/17 by jacarey@fl_jcareydesktop
`
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`1. Updated RB_BlendControl for AlphaBlend Packet
`2. Added Microcode for Source Rotation for 2D.
`
`3. Updated Documentation for Source Rotation and RBBlendControl
`
`Change 76199 on 2003/01/13 by jacarey@fl_jcareydesktop
`
`Documentation for the 2D Endian Mode Programming
`
`Change 75815 on 2003/01/10 by jacarey@fl_ jcareydesktop
`
`Update equation used by micro engine for 1D sources for the SRC_X / Y terms.
`
`Change 75512 on 2003/01/09 by jacarey@fl_jcareydesktop
`
`m=WN
`
`Add level of indirection to the AndMask and OrMask in the RegRMW packet.
`Updated Associated Unit Test.
`
`Updated PM4 Spec Accordingly.
`
`. Added Note to Polyline packet,
`
`that the scan_count needs to be 1 or greater.
`
`Change 75197 on 2003/01/08 by jacarey@fl_ jcareydesktop
`
`1. Reduction of queue sizes in CP for area savings.
`
`Change 74715 on 2003/01/06 by jacarey@fl_jcareydesktop
`
`Clarification of InvalidateState packet w.r.t. use of MemWrite
`
`Change 74684 on 2003/01/06 by jacarey@fl_jcareydesktop
`
`Update width of brush offset to reflect 24 bits supported by the VGT.
`
`Change 72284 on 2002/12/18 by jacarey@fl_jcareydesktop
`
`AlphaBlend PM4 Packet Update
`
`1. Microcode Updates
`
`2. Documentation Updates
`3. Unit Test
`
`Change 72248 on 2002/12/18 by jacarey@fl_jcareydesktop
`
`Add note for holding "event triggered" on the visio diagram.
`
`Change 72164 on 2002/12/18 by jacarey@fl_jcareydesktop
`
`Add register to arm signal to mask false falling/rising edge triggering.
`
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`Change 71667 on 2002/12/17 by jacarey@fl_ jcareydesktop
`
`Add AAFont Micrococode
`Add associated unit-level test
`
`Update PM4 Spec for AA_Font and AlphaBlend PM4 Packets
`
`Change 70929 on 2002/12/13 by jacarey@fl_jcareydesktop
`
`Clarify that "dummy" dwords in the ib_prefetch* packets are set to Oxdeadbeef
`by the Pre-Fetch Parser.
`
`The emulator is being updated to match the RTL.
`
`Change 69066 on 2002/12/06 by jacarey@fl_jcarey2
`
`Clarify Ring Buffer Size in DWORDs.
`
`Change 68428 on 2002/12/04 by jacarey@fl_jcareydesktop
`
`Fix Typo in CondWrite Packet in PM4 Spec.
`
`Change 68327 on 2002/12/04 by jacarey@fl_ jcareydesktop
`
`Update Alignment of the Ring, Indirects, and Real-Time Bases
`
`Change 67940 on 2002/12/02 by mearl@mearl_r400_win
`
`fixed the offset problem
`
`Change 67834 on 2002/12/02 by jacarey@fl_jcareydesktop
`
`Remove ME_HALT and ALU_COUT32 Booleans
`
`Change 66176 on 2002/11/22 by jacarey@fl_jcareydesktop
`
`Update Address Mask for RegRMW PM4 Packet.
`Associated Documentation Updated
`
`Change 66006 on 2002/11/21 by jacarey@fl_jcareydesktop
`
`Update to Reg_RMW Packet...Streamlined Thanks to Harry...
`
`Change 65950 on 2002/11/21 by jacarey@fl_jcareydesktop
`
`Add Reg_RMW (Read/Modify/Write)
`Documentation Update
`Associated Unit-Level Test
`
`to the PM4 Packets
`
`AMD1044_0166392
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`Change 65863 on 2002/11/21 by jacarey@fl_ jcareydesktop
`
`Revert B7 2D Boolean Setting.
`
`It is only set based on the src_type==
`
`- Emulator Update to CP
`
`» Verilog Update to Micro Engine
`- Remove Unit Test
`
`. Update CP Documentation
`
`Change 65588 on 2002/11/20 by jacarey@fl_jcareydesktop
`
`8bpp-to-lébpp TLU Issue for 2D
`
`Change 64857 on 2002/11/18 by jacarey@fl_jcareydesktop
`
`RB_BLENDCONTROL.ColorDitherMode is set to DITHER_LUT for GradFill packets
`
`where the DSTTYPE != 32bpp.
`
`Change 64833 on 2002/11/18 by jacarey@fl_jcareydesktop
`
`Add note for MERTS generation for read operations initiated by the micro engine.
`
`Change 64144 on 2002/11/14 by jacarey@fl_jcareydesktop
`
`1. RTL Update to Set 2D Boolean BO for LUT Color Sources
`
`2. CP Spec Updates for #1
`
`3. CP Spec Update for the CP_DMA_STAT Register
`
`Change 63680 on 2002/11/13 by jacarey@fl_jcareydesktop
`
`Im_Load and Im_Load_Immediate packets write the SQPSPROGRAM register for real-time
`shader code
`
`updates. This is documented in the PM4 spec now.
`
`Change 63490 on 2002/11/12 by jacarey@fl_jcareydesktop
`
`Add Write Confirm Signals to CP_STAT Register
`
`Change 63336 on 2002/11/12 by jacarey@fl_jcareydesktop
`
`Baseline Debug Documents for the CP and RBBM
`
`Change 63155 on 2002/11/11 by jacarey@fl_jcareydesktop
`
`Add CP_RT_STAT register to spec.
`
`Change 63098 on 2002/11/11 by jacarey@fl_jcareydesktop
`
`AMD1044_0166393
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`1. Performance Signals for RTEE
`
`2. Split Busy Signal
`
`from the CSF into a real-time and non-real-time version
`
`Change 63094 on 2002/11/11 by jacarey@fl_jcareydesktop
`
`1. Add register to micro engine guts for timing
`
`2. Add FIFOs for Timing in the Synchronization Logic
`
`3. Update CP's Performance Counter Selects in perfcount.doc
`
`Change 62813 on 2002/11/08 by jacarey@fl_jcareydesktop
`
`1. Update CP Spec for Debug Signals
`
`2. Update One of the 2D Unit Tests to Read Back Debug Information
`
`Change 62444 on 2002/11/07 by jacarey@fl_ jcareydesktop
`
`Updates for the CPSTAT register
`
`Change 62266 on 2002/11/07 by jacarey@fl_jcareydesktop
`
`Updates for Soft Reset to Register Descriptions
`
`Change 61964 on 2002/11/06 by jacarey@fl_jcareydesktop
`
`Update Soft Reset Description
`
`Change 61912 on 2002/11/06 by jacarey@fl_jcareydesktop
`
`Update to GradFill Description in PM4 Spec
`
`Change 61803 on 2002/11/05 by jacarey@fl_jcareydesktop
`
`Update format of the Grad_Fill packet per discussion on 11-05-2002.
`
`Change 61480 on 2002/11/04 by jacarey@fl_jcareydesktop
`
`Fix Typo in MPEGINDEX packet documentation.
`
`Change 61453 on 2002/11/04 by jacarey@fl_jcareydesktop
`
`Update MPEG Index Packet
`
`1. Remove "Dummy" and "Mask" DWORDs
`
`2. RectList primtype is assumed, so CP only outputs 3 indices (Original +2)
`
`Change 61416 on 2002/11/04 by jacarey@fl_jcareydesktop
`
`Update the Microcode RAM Size(s)
`
`AMD1044_0166394
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`Change 61310 on 2002/11/04 by jacarey@fl_jcareydesktop
`
`Update per Lili Sinclair's E-mail.
`
`Change 60910 on 2002/11/01 by jacarey@fl_jcarey2
`
`Update CP's Performance Monitoring Signals.
`
`Change 60768 on 2002/10/31 by jacarey@fl_ jcareydesktop
`
`Fix Name of Signal From the RBBM.
`
`Change 60393 on 2002/10/30 by jacarey@fl_jcarey2
`
`Fix Typo in CP_PERFMONCNTL register description
`
`Change 59994 on 2002/10/29 by jacarey@fl_jcarey2
`
`Add registers for the CP Performance Counter
`
`Change 59904 on 2002/10/29 by jacarey@fl_jcareydesktop
`
`Source clipping is only done by the CP for ROPs that include a source term.
`
`Change 59789 on 2002/10/28 by jacarey@fl_jcarey2
`
`AlphaBlend, AAFONT and LoadExecute marked as "Not Currently Supported"
`
`Change 59693 on 2002/10/28 by jacarey@fl_jcarey2
`
`Swap bits for oper=gmcdecode flags
`
`Change 59677 on 2002/10/28 by jacarey@fl_jcarey2
`
`Add:
`
`1. ROP7:4 != ROP3:0 flag for oper=gqmcdecode
`
`2. Sre_ClipDisable Flag for oper=gmcdecode
`
`Change 59395 on 2002/10/25 by jacarey@fl_jcarey2
`
`Remove CP_CONTEXT_ID register it will be in the VGT
`
`Change 59342 on 2002/10/25 by jacarey@fl_jcareydesktop
`
`Document CP_CONTEXT_ID register.
`
`Change 58801 on 2002/10/23 by jacarey@fl_jcarey2
`
`AMD1044_0166395
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`Add ROP comment to GradFill Packet
`
`Change
`
`58617 on 2002/10/22 by jacarey@fl_ jcarey2
`
`Update
`
`for Clearing the Register Update Flag
`
`Change
`
`58615 on 2002/10/22 by jacarey@fl_jcarey2
`
`Document Updates for Incremental Register Updates
`
`Change
`
`58032 on 2002/10/18 by jacarey@fl_jcarey2
`
`Update
`
`diagram for clock gating
`
`Change
`
`57991 on 2002/10/18 by jacarey@fl_jcarey2
`
`Update
`
`documents for Incremental Register Update
`
`Change
`
`57933 on 2002/10/18 by jacarey@fl_jcarey2
`
`1. Remove legacy versions of packets that were struck through
`2. Add Incremental Register Write Support
`
`Change 57890 on 2002/10/18 by jacarey@fl_jcarey2
`
`Added sredataformat to the alphablend packet.
`
`Change 57784 on 2002/10/17 by jacarey@fl_jcarey2
`
`Refer to the PA register spec for the format of the destination clipping parameters in
`
`the PM4 spec.
`
`Change
`
`57470 on 2002/10/16 by jacarey@fl_jcarey2
`
`Documentation Updates for Programming Max Count while processing.
`
`Change
`
`57382 on 2002/10/16 by jacarey@fl_jcarey2
`
`Update
`
`to transfifo clock
`
`Change
`
`57337 on 2002/10/16 by jacarey@fl_jcarey2
`
`Update
`
`for sclk_reg
`
`Change
`
`57196 on 2002/10/15 by jacarey@fl_jcarey2
`
`Update
`
`for SCLK_REG
`
`AMD1044_0166396
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`Change 57175 on 2002/10/15 by jacarey@fl_jcarey2
`
`1. Add CP_PERFMONCNTL to CP register set
`2. Documentation Updates for Clock Gating
`
`Change 57052 on 2002/10/15 by jacarey@fl_ jcarey2
`
`Clarify the number of DWORDs for ALU and Texture constant updates.
`
`Change 56944 on 2002/10/14 by jacarey@fl_jcarey2
`
`Update Diagram for Dynamic Clocking in the CP
`
`Change 56612 on 2002/10/11 by jacarey@fl_jcarey2
`
`Update for DP_SRC_SOURCE
`
`Change 56593 on 2002/10/11 by jacarey@fl_jcarey2
`
`Make SQ_CP_* eventid buses 5 bits to cover all defined events.
`
`Change 56586 on 2002/10/11 by dwong@cndwong2
`
`changed the real-time signal names wired into CP (from overlay)
`
`bits 5 and 6 of connections to the CP_rtsdiscretes input bus are changed to
`DISPx_CP_flipproceed
`
`Change 56558 on 2002/10/11 by jacarey@fl_jcarey2
`
`B4 and B39 Booleans need to be set for NextChar
`
`Change 56350 on 2002/10/10 by jacarey@fl_jcarey2
`
`Update pseudocode for LCC packet as processed by Real-time
`
`Change 56314 on 2002/10/10 by jacarey@fl_jcarey2
`
`Clarification on ME_INIT for Mask Bit
`
`9
`
`Change 56303 on 2002/10/10 by jacarey@fl_jcarey2
`
`Added Default Reset Control to ME init packet (bit 93 of mask)
`
`Change 56082 on 2002/10/09 by jacarey@fl_jcarey2
`
`Added VIP_CP_eof_ack to list.
`
`AMD1044_0166397
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`Change 56048 on 2002/10/09 by jacarey@fl_jcarey2
`
`Invert polarity of the MHCPwriteclean signal
`
`Change 55935 on 2002/10/08 by jacarey@fl_jcarey2
`
`Update description of the BO 2D Boolean for monochrome sources.
`
`Change 55922 on 2002/10/08 by jacarey@fl_ jcarey2
`
`Only Set BO Boolean for solid brushes if SRC_TYPE != Mono
`
`Change 55816 on 2002/10/08 by jacarey@fl_jcarey2
`
`Update spec for dst clip parameters to be positive only.
`
`Change 55679 on 2002/10/07 by jacarey@fl_jcarey2
`
`Added write confirm function for DMA engine at end of table.
`
`Change 55399 on 2002/10/04 by jacarey@fl_ jcarey2
`
`Miscellaneous Updates for New 2D Packets
`
`Change 55398 on 2002/10/04 by jacarey@fl_jcarey2
`
`1. Removed Width from compound indices
`
`2. Added 2D_Tri_Strip compound indice
`3. Misc. Comments.
`
`Change 55163 on 2002/10/03 by jacarey@fl_jcarey2
`
`Updates to Gradfill packet
`
`Update to comment on setting the 2D B3 Boolean
`
`Change 55162 on 2002/10/03 by jacarey@fl_jcarey2
`
`Boolean B3 should be '0' for SRC_TYPE=0.
`Mark Earl will check-in the emulator update.
`
`Change 54971 on 2002/10/03 by jacarey@fl_jcarey2
`
`Minor updates to register default values and minimal power-up sequence.
`
`Change 54550 on 2002/10/01 by jacarey@fl_jcarey2
`
`Partial updates for new 2D packets
`
`AMD1044_0166398
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`Change 54490 on 2002/10/01 by jacarey@fl_jcareydesktop
`
`Miscellaneous clarifications to the RT event engine diagram.
`
`Change 54370 on 2002/09/30 by jacarey@fl_jcarey2
`
`Added compound index details for Stretch Blit Support.
`
`Change 54347 on 2002/09/30 by jacarey@fl_ jcarey2
`
`Add register to the pollvalid signal to align with data.
`
`Change 54028 on 2002/09/27 by jacarey@fl_jcarey2
`
`Clean Up Spec per actual connections.
`
`Change 53900 on 2002/09/26 by jacarey@fl_jcareydesktop
`
`Make 2D Default registers write only. Readable via the ME_STATMUX
`
`Change 53857 on 2002/09/26 by jacarey@fl_ jcareydesktop
`
`Update EventWrite packet
`
`to include all events
`
`Change 53556 on 2002/09/25 by jacarey@fl_jcareydesktop
`
`Update CP's Buffer Sizes to a 2*20 DWORD limit.
`
`Change 53280 on 2002/09/24 by jacarey@fl_jcareydesktop
`
`Add Fix2Flt_Reg PM4 Packet for Video Folks.
`PM4 Spec Update for Packet
`
`Add Opcode to pm4_it_opcodes
`New Unit Test Included
`
`Change 53167 on 2002/09/23 by jacarey@fl_jcareydesktop
`
`1. Comment Only Correction to the Microcode
`
`2. Update Brush_X and Brush_Y pointers in PM4 spec to be of the range 0.0 to 7.0
`
`Change 53162 on 2002/09/23 by jacarey@fl_jcareydesktop
`
`Clarifications to LCC and SetConstant Packet
`
`Change 53056 on 2002/09/23 by jacarey@fl_jcareydesktop
`
`Documented ROP3's that are supported in R400 for 2D.
`
`AMD1044_0166399
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`Change 53007 on 2002/09/23 by jacarey@fl_jcareydesktop
`
`1. Update for oper=clrrepack function for Dst_Type==2
`2. Update sizes for physical memories.
`
`Change 52324 on 2002/09/18 by jacarey@fl_ jcareydesktop
`
`Intrinsic function for unpacking colors to 8888 format
`
`Change 52265 on 2002/09/18 by jacarey@fl_jcareydesktop
`
`Update for Alpha Color Defaults for RGB565 brush color format.
`
`Change 52230 on 2002/09/18 by jacarey@fl_jcareydesktop
`
`Update to SRC terms for small_text and hostdata_blt* packets (i.e. 32-bit SRC_OFFSET)
`Updated the fixed constants that are in the C7 vertex shader constant.
`
`Change 52229 on 2002/09/18 by jacarey@fl_jcareydesktop
`
`Update for 32-bit SRC_Offset term for SmallText and HostData_Blt* packets
`
`Clarification for Foreground and Background Colors = Dst_Type format
`
`Change 52221 on 2002/09/18 by jacarey@fl_jcareydesktop
`
`Update CP_STQAVAIL register fields
`
`Change 51438 on 2002/09/13 by jacarey@fl_jcareydesktop
`
`Adjust Registers for Visibility
`
`Change 51314 on 2002/09/13 by jacarey@fl_jcareydesktop
`
`Removed ROP=0xCC note from PM4 spec for brush types 0x6 and 0x7
`
`Change 51069 on 2002/09/12 by jacarey@fl_jcareydesktop
`
`Update for oper=gmcdecode: Brush Type 0x6 and Ox? set bit 15 of result
`
`Change 51068 on 2002/09/12 by jacarey@fl_jcareydesktop
`
`32x1 Brush Types are not converted to 32bpp by the CP.
`
`Change 50578 on 2002/09/10 by jacarey@fl_jcareydesktop
`
`Update POLYLINE pseudocode.
`
`AMD1044_0166400
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`Change 50413 on 2002/09/10 by jacarey@fl_jcareydesktop
`
`Added Cache_Flush_and_InvalidateTS to Event_TimeStampWrite packet
`
`Change 50403 on 2002/09/10 by jacarey@fl_jcareydesktop
`
`Add Result Reuse to Diagram
`
`Change 50398 on 2002/09/10 by jacarey@fl_jcareydesktop
`
`Update Indice count for Polyline packet
`
`Change 49994 on 2002/09/06 by jacarey@fl_ jcareydesktop
`
`Correct booleans again for transbitblt
`
`Change 49991 on 2002/09/06 by jacarey@fl_jcareydesktop
`
`Update boolean settings for
`
`Change 49888 on 2002/09/06 by jacarey@fl_jcareydesktop
`
`Document clearing of B4 and C2.x boolean if ROP[7:4]
`
`!= ROP[3:0]
`
`for Blt and Text
`
`packets.
`
`Change 49883 on 2002/09/06 by jacarey@fl_jcareydesktop
`
`Update for Timing
`
`Change 49477 on
`
`2002/09/04 by jacarey@fl_jcarey2
`
`Clarified Brush
`
`Expansion
`
`Change 48962 on
`
`2002/08/30 by jacarey@fl_jcareydesktop
`
`Removed StatMux
`
`The connections
`
`Connections from Visio Diagram
`
`are listed in the CP Spec.
`
`Change 48900 on
`
`2002/08/29 by jacarey@fl_jcareydesktop
`
`Updates for controlling queued vs. non-queued transactions from micro engine.
`
`Change 48888 on 2002/08/29 by jacarey@fl_jcareydesktop
`
`Update sign extension note for the PLY_NEXTSCAN packet.
`
`Change 48832 on 2002/08/29 by jacarey@fl_jcareydesktop
`
`AMD1044_0166401
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`Remove direct access to the Ibl and Ib2 base/size fetchers
`
`Change 48824 on 2002/08/29 by jacarey@fl_jcareydesktop
`
`Clarification for memory usage for Brush and Palette
`
`Change 48786 on 2002/08/29 by jacarey@fl_ jcarey2
`
`Micro Engine Updates for NO Flag
`
`Change 48778 on 2002/08/29 by jacarey@fl_jcarey2
`
`Add NQ Flag Processing....
`
`Change 48623 on 2002/08/28 by jacarey@fl_jcarey2
`
`Mono Brush Unpacking
`
`Change 48463 on 2002/08/28 by jacarey@fl_jcareydesktop
`
`Miscellaneous Spec Updates
`
`Comments in Microcode for 2D Processing.
`
`Change 48462 on 2002/08/28 by jacarey@fl_jcareydesktop
`
`Add B19 Boolean and Remove SRC_SC_BOTTOM_RIGHT_GMC default value
`
`Change 48341 on 2002/08/27 by jacarey@fl_jcarey2
`
`Final Update from Joe
`
`Change 4832