`
` 2400 Executive Review
`
`
`
`
`
`September 16, 2002
`
`ATI Corporate Presentation
`
`AMD1044_0051184
`
`ATI Ex. 2024
`IPR2023-00922
`Page 1 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 1 of 11
`
`
`
`Si2Z/2047,
`WIP.
`
`95% fea 9/23- 9/16
`85% /-95%
`
`a(2nS)
`PIXCLK (2.5nS)
`BCLK ains)
`
`MC.4.46; net 472
`RB: 6.2; RC 25
`Sx 215, SQ°25
`
`CG: 25: CoM ies
`PA: 2 69
`VGT: 2.75
`$C:2.73
`RBBM: 2.95
`
`
`
`
`
`
`Display - CRTC
`Display - DISPOU
`Display - TVOUT.
`VGA
`BCLK: 14.1
`
`4
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0051185
`
`ATI Ex. 2024
`IPR2023-00922
`Page 2 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 2 of 11
`
`
`
`seme
`
`Block Level Test Status
`
`
`
`
`
`
` ||=% Written
`Completeness
`
`a3ES
`:
`40%
`||m% Passing
`20%
`a
`0%
`DWV KIMORA Od VK FP
`RK AD
`Pate? QYO'a.Loe NOKSsOXeS RK&
`CON Gehag sh
`oY
`or VORR On’
`G
`QS
`Functional Block
`
`Ri
`CONEIDENTIAL
`Si2Z/2047,
`
`ATI Corporate Presentation
`
`AMD1044_0051186
`
`ATI Ex. 2024
`IPR2023-00922
`Page 3 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 3 of 11
`
`
`
`LOSI
`
`@ Planned
`@ Written
`O Passing
`
`Test
`
`Count
`
`C3 CONEIDENTIAL
`
`
`
`
`Functional Block
`
`Si2Z/2047,
`
`ATI Corporate Presentation
`
`AMD1044_0051187
`
`ATI Ex. 2024
`IPR2023-00922
`Page 4 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 4 of 11
`
`
`
`synthesis & Physical Design
`
`+ Hardware Emulation
`— Initial |IKOS compilation has begun to attempt R400fit into a Vi5M
`
`- Synthesis continuing...
`— Blocks focusing on feature complete, not timing
`+ Someblocks have madesignificant progress
`— Working top level interconnect issues
`- Working synthesis interface into physical design
`
`- Physical design
`— Working group inter-relationships SiV<>Marlboro
`— Meeting often to synchronize teams
`— Physical Design web page under construction
`
`Floorplan
`— Initial padout done, needs to be reviewed
`— Initial netlist Successfully read into SPC
`- Generated floorplan from SPC (no I/O constraint)
`
`Si2Z/2047,
`
`
`be}
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0051188
`
`ATI Ex. 2024
`IPR2023-00922
`Page 5 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 5 of 11
`
`
`
`First R400 Floorplan - Silicon Perspectives
`(no I/O constraints)
`ONOOREECELERTRESISPOOR,
`
`
`LC) CONEIDENTIAL
`
`DIyAy4t a
`
`ATI Corporate Presentation
`
`AMD1044_0051189
`
`ATI Ex. 2024
`IPR2023-00922
`Page6 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 6 of 11
`
`
`
`Software Status (2D / MM)
`
`RESORT
`
`
`
`
`- Display Driver
`— BIOS: Design scope nearly complete, significant work identified,
`detailed plan is available
`— CAIL: Design scope completed, ~15% implemented
`— DAL/GXO:Design scope completed, significant work identified,
`work underway
`— CMM/QS: Design scope completed, ~5% implemented
`— 2D/NTx: Design scope completed, ~10% implemented
`— 2D/9x: Design scope completed, ~5% implemented
`- Multimedia
`
`— Staffing and re-org complete; development work in progress.
`— Schedule complete; under review.
`— Design specs partially complete.
`— MRD review meeting scheduled on Thursday.
`
`id
`CONEIDENTIAL
`Si2Z/2047,
`
`ATI Corporate Presentation
`
`AMD1044_0051190
`
`ATI Ex. 2024
`IPR2023-00922
`Page 7 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 7 of 11
`
`
`
`
`
`8
`CONEIDENTIAL
`Si2Z/2047,
`
`Software Status (3D)
`
`BLT ~80%implemented
`Abstract state, state cache, surface create and drawing functions
`~60% implemented
`Z/Stencil/Color ~50% implemented
`Texture ~40% implemented
`AA / HOSnot yet begun
`+ OpenGL
`Multiple texture and texture state 80% complete
`IL to R400 binary translator 100% complete
`Z, stencil and alpha operations complete
`Vertex and fragment shaders complete
`- Compiler
`Compiler integrated with SSM and D3D Driver 100%
`Triangle through compiler on emulator 100%
`
`ATI Corporate Presentation
`
`AMD1044_0051191
`
`ATI Ex. 2024
`IPR2023-00922
`Page8 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 8 of 11
`
`
`
`R400 Area Summary
`
`REO Arma Estimate (0.13)
`
`
`
`
`
`
`
` ATLURORA
`
`
`
`
`
`
`
`
` t’7*
`
`
`Si2Z/2047,
`
`
`Pre Route
`Total Unit
`R00
`Rve00
`Post Route Logic|Macro
`LogieAree
`Block
`Utilization Unit Area
`Area
`Are
`Total
`REO Qty RE0D Tow! Oy
`t2i
`287} aan
`210Bes
`126,058
`2.4.28, 988,
`oomaoo
`{Aeneas
`BNP(BuseIntertoce
`4, 170,a4a':
`6
`‘ans, 35
`BS05.377
`5505 377
`DC (Dispiay Controiter)
`744.419
`793,498
`MIP(Video In Porg
` 37813,714
`110,718
`TiO, 744
`0G(Closk Gord
`ROM (ROM anc debug controtiod
`
`TSTO(Test Contotien
`CP(Contre! Process)
`RBGM (Rogiser Backbone Manage)
`MM (Memory Hub)
`wcT
`VOGT (Vertex Group and Tesselate}
`PA (ViewportXform. Clip and Setup)
`SC Sean Converted
`SP (Shader Pipe)
`$2Begrenser)
`TP (Texture Pipe)
`TC (Texture Coste}
`RS (Render Backend)
`RO (Rendur Serra)
`$X Ghager Export?
`MC (Memory Controtiert
`Analog
`
`
`
`‘TotalCare fumi}
`17a 449
`
`
`aaoa,4a40
`
`3
`
`
`4t$f14f
`‘4¢4'4
`ai44
`4i
`
`Current Pad separation (ur)
`Current Pad height(um)
`Seribe
`Core mmisice
`Tota! mralside
`
`a0
`SO
`ota
`
`RV45O in 0.09 (esimated)
`Core mralsice
`Total mmiside
`
`
`
`70.11
`70.99
`
`6.15
`9.or
`
`9
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0051192
`
`ATI Ex. 2024
`IPR2023-00922
`Page 9 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 9 of 11
`
`
`
`« R400 Technology
`— Proceeding with TSMC 0.13 Low-K; need to continue to monitor status
`
`* Chip Integration
`— Virage STAR compiler - functional compiler delivery late
`+
`Impacting completeness of next netlist release
`~ Chip level simulation environmentstabilizing - impacting debug of non-GC blocks
`
`- Physical Design
`— Resourcerollovers from RV350 to R400
`-— Logic Design netlist delivery to the Physical team
`— New flow will be a risk; only partially exercised on RV350
`
`- Software
`— Compiler progressing (slower than planned)
`— Software MRD reviews completing; need review of integrated SW schedules
`
`Si2Z/2047, R400 Risks / lssues Summary
`ongesepsorrnernd
`
`« Overall
`-— Debug progressing slowly in some areas
`— February tapeouttarget.
`
`ah
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0051193
`
`ATI Ex. 2024
`IPR2023-00922
`Page 10 of 11
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 10 of 11
`
`
`
`R400 Program Schedule
`
`Plan
`
`01-18-02
`02-22-02
`03-15-02
`04-16-02
`05-17-02
`06-15-02
`07-12-02
`09-16-02
`10-11-02
`
`11-08-02
`11-11-02
`11-15-02
`01-10-03
`
`Task
`
`Emulator Test template Complete
`GC Emulatorintegration — 1 triangle
`Core Emulator pixel / shader tests run
`Block Testing Begins
`GC/Chip Integration Start
`Simulate 1 Triangle / Emulator ready for SW
`First Syntheses
`Verilog Feature Complete
`IKOS Emulation start
`
`Begin early block delivery
`IKOS Emulation (w/ Software) begins
`RTL Freeze / Final Netlist (Gate level ECO only)
`A111 Base Layers Tapeout
`A11 Metal Layers Tapeout
`First Samples for Engineering
`A12 Tapeout
`A12 Samples for Engineering
`R400 Customer Samples
`Product Delivery
`
`01-24-03
`
`Actual
`
`Forecast
`
`01-18-02
`02-21-02
`03-19-02
`05-01-02
`05-15-02
`07-01-02
`08-03-03
`
`03-14-03
`
`06-28-03
`
`09-30-02
`10-11-02
`11-15-02
`11-11-02
`11-30-02
`02-28-03
`
`05-23-03
`
`07-26-03
`08-02-03
`09-02-03
`
`Si2Z/2047,
`[regen
`
`41
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0051194
`
`ATI Ex. 2024
`IPR2023-00922
`Page 11 of 14
`
`ATI Ex. 2024
`
`IPR2023-00922
`Page 11 of 11
`
`
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