throbber
ATI TECHNOLOGIES INC.
`
`ATI TECHNOLOGIES INC.
`
`R400 I/O
`
`February 12, 2003
`
`May 2, 2017
`
`AMD1044_0051118
`
`ATI Ex. 2019
`IPR2023-00922
`Page 1 of 8
`
`

`

`
`R400 I/O Activities
`
`
`
`
`* Pad ring review with Greg S. on 2/14 in SiV
`*
`JO/NPL review on 2/25 & 2/26 in SiV with team from
`Marlborough
`* Viper program
`
`
`
`
`ATI TECHNOLOGIES INC.
`
`May 2, 2017
`
`AMD1044_0051119
`
`ATI Ex. 2019
`IPR2023-00922
`Page 2 of 8
`
`ATI Ex. 2019
`
`IPR2023-00922
`Page 2 of 8
`
`

`

`
`
`Memory W/O & Clock
`
`
`
`First pass design of the memory I/O is complete.
`* First pass design of the memory clock is complete.
`
`* Layout schedule
`
`* Memory I/O - 2/13
`
`* Memory clock - 2/18
`
`* Memory calibration - 2/20
`* Memory strobe - 2/21
`
`* Library files
`
`* Verilog - complete and checkedinto the tree
`
`* LEF of Memory I/O, clock, calibration, and strobe -- 2/18
`
`* TLF/LIB/DB of memory I/O,clock,calibration, and strobe - 2/21
`
`
`
`
`
`
`
` ATI TECHNOLOGIES INC. [DateTime]
`
`
`
`May 2, 2017
`
`AMD1044_0051120
`
`ATI Ex. 2019
`IPR2023-00922
`Page 3 of 8
`
`ATI Ex. 2019
`
`IPR2023-00922
`Page 3 of 8
`
`

`

`
`Memory Near Pad Logic
`
`
`
`
`
`
`
`RTL-to-schematic implementation
`* ADDR, DATA, DQSM, DQSS and HCLKare done first pass
`* All five pass LEC
`* Started timing simulations (HSPICE)
`* Found bug in IO/NPL which required the NPL to be updated
`* Layout to start on 2/15 and complete on 3/15
`* Library files (LEF, TLF, LIB, and DB) will be deliver on 3/1
`On going memory system timing - complete on 3/15
`
`[DateTime]
`ATI TECHNOLOGIES INC.
`
`
`
`
`May 2, 2017
`
`AMD1044_0051121
`
`ATI Ex. 2019
`IPR2023-00922
`Page 4 of 8
`
`ATI Ex. 2019
`
`IPR2023-00922
`Page 4 of 8
`
`

`

`
`
`Delay Line and misc
`layout
`
`
`
`
`* Design is done
`* Layout is complete
`* Miscellaneouslayout
`* ChrisV/KarenW started layout on the miscellaneouscells
`* PVREF
`* Corners
`* Spacers
`* Breaks
`Complete on 3/1
`
`
`
`
`
`
`ATI TECHNOLOGIES INC. [DateTime]
`
`
`May 2, 2017
`
`AMD1044_0051122
`
`ATI Ex. 2019
`IPR2023-00922
`Page 5 of 8
`
`ATI Ex. 2019
`
`IPR2023-00922
`Page 5 of 8
`
`

`

`
`
`Viper program
`
`
`* What is the Viper program?
`*
`It’s a joint development between ATI and Micron to design
`the bring up vehicle for GDDR3.
`* Viper is a test chip which contains the memory controller
`and supporting logic from Micron.
`* ATI provides the I/Os, analog components (PLL and Delay
`line), and package design.
`*
`|/Os, PLL and Delayline are the same design used for R400.
`* Designed for the TSMC 0.13um cyber shuttle (the process
`is similar to the RV350/R400).
`
`
`
`
`
`
`
`
`
`
`
` ATI TECHNOLOGIES INC. [DateTime]
`
`
`
`May 2, 2017
`
`AMD1044_0051123
`
`ATI Ex. 2019
`IPR2023-00922
`Page 6 of 8
`
`ATI Ex. 2019
`
`IPR2023-00922
`Page 6 of 8
`
`

`

`
`
`
`
`Weekly (Tuesdays) conferencecall with Micron.
`° Deliveredinitial views of all cells to be used in Viper.
`* Delivery of final models to Micron on 2/21.
`* Pad ring spreadsheetis complete.
`* Pad ring DRC/LVS clean to Micron on 2/28.
`°
`If all goes well, Viper tapes out in mid Marchto early
`April (also depends on cyber shuttle schedule).
`Started package design on 2/11.
`
`ATI TECHNOLOGIES INC.
`
`
`
`
`
`Viper Schedule
`
`
`
`
`
`
`May 2, 2017
`
`AMD1044_0051124
`
`ATI Ex. 2019
`IPR2023-00922
`Page7 of 8
`
`ATI Ex. 2019
`
`IPR2023-00922
`Page 7 of 8
`
`

`

` Deliverables
`
`
`
`* Final LEF, TLF, LIB, DB and verilog on 3/1 (ontarget)
`
`* Ring DRC/LVSclean and gds delivery on 4/15 (on target)
`
`
`
` ATI TECHNOLOGIES INC. [DateTime]
`
`
`
`May 2, 2017
`
`AMD1044_0051125
`
`ATI Ex. 2019
`IPR2023-00922
`Page 8 of 8
`
`ATI Ex. 2019
`
`IPR2023-00922
`Page 8 of 8
`
`

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