`
` 400 Program Review
`
`February 12, 2003
`
`ATI Corporate Presentation
`
`AMD1044_0051103
`
`ATI Ex. 2017
`IPR2023-00922
`Page 1 of 6
`
`ATI Ex. 2017
`
`IPR2023-00922
`Page 1 of 6
`
`

`

`R400 Review Action Summary
`Program — Next tentative review date is on March 12‘
`
`Last Month
`— R400 Software
`
`- Plan support for packet dump capture — Complete
`+ Quality goal needed for conformance ofpescadegesolaaa code - Open
`+
`IKOS Meeting with Ron White for SW — Comoaleic
`R400 Hardware
`
`+ SDR 3.3V support on DVO port (requirements) —
`+ RB break-upfor Netlist delivery (NL4.0 vs NLS.oe
`+ Code coverage analysis onall blocks:-[9
`
`+ DC dependency on MH bugs Aen
`
`+ DC instance count — in
`
`+ SQ test coverage review
`Performance
`+ PA performanceregisters — Complete
`GCtestbenchfor better performancedata -
`
`+
`
`+ Contractors to run/analyze tests — Ko Yu, 4
`Chip Integration
`+ Power — ©
`
`
`+ Operations —
`chex
`+ Pad — Revie
`
`Physical Design
`+ Feedback from Netlist 3 needed — Mark Lee began, PD/LD meetings in
`
`
`Si2Z/2047,
`
`
`
`
`4
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0051104
`
`ATI Ex. 2017
`IPR2023-00922
`Page 2 of 6
`
`ATI Ex. 2017
`
`IPR2023-00922
`Page 2 of 6
`
`

`

`R400 Review Action Summary
`
`- This review
`
`Si2Z/2047,
`
`
`+ Quality goal needed for conformance of Sanpeeeedyeteierey code - Open
`
`-
`Is HW testing using Set_state or TypeO packets in tests — Mark Fowler
`— $Wraninto problem recently
`~ Sse Hardware
`RB split for netlist 5 — Frank Hering
`+ AB file dumps — Mike Mantor/ Larry Seiler
`+ Remove degamma from DXTC as a feature ?
`+ Code coverage analysis on blocks — Mark Fowler
`+ TC performance path ~ Steve Morein / Clay Taylor / Andy Gruber
`- DC instance count high — Lili S./Frank H. to close with Mark Lee
`Assist with debug of 2D tests — Mark Earl / John Carey / Harry Wise
`SQ/SX hasrisk, continue to monitor — Peter Pellerite
`+ Review CP code
`— Rewrite of 2D Drivers for derivative area savings — Joe Cox
`— CP code removed, need to review — Andy Gruber/ John Carey
`— Performance
`+ Orlando to work more with playback — Chris ray/ Allen G.
`+ GC testbench for better performance data — Ope
`— Chip Integration
`+ Thermal solution need overall owner
`- Boards group involvementpriority (or window is lost)
`+ Operations — give memory/fuse package to Anita for ASE
`+ Pad — clock distribution in pads needsto befinalized with SiV
`— Physical Design
`+ BIF description for R400 PD — Lili Sinclair
`+ PD to LD communication mostly working (may need to expand/changelist)
`+ Clock insertion methodology — meeting 2/14
`
`K
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0051105
`
`ATI Ex. 2017
`IPR2023-00922
`Page 3 of 6
`
`ATI Ex. 2017
`
`IPR2023-00922
`Page 3 of 6
`
`

`

`Si2Z/2047,
`PREPS RENO
`
`ra
`CONEIDENTIAL
`
`High Level Schedule
`
`Original Last FCTask Current FC
`
`
`
`Emulator Test template Complete
`01-18-02
`01-18-02
`Complete
`GC Emulator integration - 4 triangle
`02-22-02
`02-21-02
`Complete
`Core Emulator pixel / shader tests run
`03-15-02
`03-19-02
`Complete
`Block Testing Begins
`04-16-02
`05-01-02
`Complete
`GCiChip Integration Start
`05-17-02
`05-15-02
`Complete
`Simulate 1 Triangle / Emulator ready for SW
`06-15-02
`07-01-02
`Complete
`First Syntheses (n-1)
`07-12-02
`08-03-02
`Complete
`Verilog Feature Complete
`09-16-02
`10-31-02
`Complete
`Second Synthesis (n)
`09-23-02
`10-04-02
`Complete
`IKOS Emulation start
`10-11-02
`01-13-03
`Complete
`Third Synthesis
`11-01-02
`01-02-03
`Complete
`Early block delivery starts
`11-08-02
`12-16-02
`Complete
`Netlist 4.0
`02-14-03
`02-07-03
`02-12-03
`Netlist 5.0
`03-03-03
`03-03-03
`03-03-03
`IKOS Emulation (w/ Software) begins
`11-11-02
`01-16-02
`03-16-03
`RTL Freeze / Final Netlist (Gate level ECO only)
`11-15-02
`01-31-03
`05-01-03
`A11 Base Layers Tapeout
`01-10-03
`03-28-03
`06-26-03
`A11 Metal Layers Tapeout
`01-24-03
`04-11-03
`07-10-03
`First Samples for Engineering
`06-25-03
`09-12-03
`R400 First Customer Samples
`07-16-03
`10-03-03
`Ai2 Tapeout
`07-31-03
`10-17-03
`A12 Samplesfor Engineering
`09-04-03
`11-28-03
`R400 Customer Samples
`09-11-03
`12-05-03
`ProductDelivery
`10-04-03
`12-29-03
`
`ATI Corporate Presentation
`
`AMD1044_0051106
`
`ATI Ex. 2017
`IPR2023-00922
`Page 4 of 6
`
`ATI Ex. 2017
`
`IPR2023-00922
`Page 4 of 6
`
`

`

`Back-Up Slides
`
`5/2/2047.
`
`
`5
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0051107
`
`ATI Ex. 2017
`IPR2023-00922
`Page 5 of 6
`
`ATI Ex. 2017
`
`IPR2023-00922
`Page 5 of 6
`
`

`

`R400Area Estimate (0.13)
`
`INGLOLOLNRSI ELEVA DIPOOLE MEINEGILESLEGOTOYNR
`
`Pre
`Post Route
`Route
`
`
`togic UuRzatio Logic Unit—Macro Total Unk Rv400 RV400 Symnesis
`
`
`Area
`Area
`Block
`n
`Area
`Area
`R400 Qty R400 Total Qty
`Total
`Date
`1%
`1.00.
`o.70
`0
`BIF (Bus imerface)
`US1DS16
`4,885,023
`4,885,923
`1.
`4,885,023
`1,885,025.
`1/28/2003
`5%
`1.00
`o70
`DC (Display Controlier)
`6.330.003
`9,042,862 2.155,266 11,198,128
`Tt
`44,198,128
`11,198,128...
`2/1/2003
` O%
`1.00
`5.70
`VIP(VideoInPort)
`4
`9
`0.
`..21/2003
`
`
`
`
`
`
`
`
`
`
`SI (Clock Gen, TST, OBG, ROM) 317,242—24/2003222.069 0.70 WF242 9 397,242 4 317,242 1.00 O%
`CP(Contro!Processor)
`0.70
`1
`§,063,748
`1.00
`--§,065,748.
`2/7/2003
`2%
`2,433,753
`3.476.790 1,586,958
`5,083,748
`RBBM(RegisterBackhone Manager)
`146,901
`0.76
`209,988
`162,382
`372,379
`4
`372,278
`1.00
`372,379.
`1/28/2003
`O%
`PAH(Memory Hub)
`5,383,879
`070
`7,705,541 1,270,941
`8,976,482
`1
`8,976,482
`0.75
`6,732,362
`22003
`4%
`IDCT
`1,228,256
`0.70
`1,758,079
`0.
`4,756,079.
`1.
`1,756,079
`1.00
`1,756,079
`1/90/2003
`1%
`VGT(Vertex Group and Tessefate)
`783.077
`0.70
`4,076,824.
`463,907.
`1,639,731
`1
`1,839,731
`1.00
`1,639,731
`1/28/2003
`1%
`PA(Viewport Xform,Clip and Setup)
`3,155,429
`0.70
`4,507,756 1,349,122.
`5,856,878
`1
`5,856,878
`1.00.
`6,656,878
`1/28/2003
`3%
`SC (Scan Converter
`3,281,784
`070
`4,688,263 1,098,714
`5,786,977
`1.
`5,786,977
`1.00
`5,786,977
`1/28/2003
`3%
`SC_B (Scan Converter}
`3.483.305
`070
`4,976,150
`0
`4,976,150
`1.
`4,976,150
`1.00
`4,976,150
`1/28/2003
`2%
`
`
`
`SP(Shader Pipe} 0.70-10,205,230 2,724,647 12,929,8777143,661 4° 51,719,508 2.00 25,859,754 2/2003 24%
`
`
`
`
`SQ (Sequencer
`9,831,763,
`0,70
`2,616,790 3,666,864
`6,283,645,
`1»
`6,283,645
`1.00
`6,283,645
`2/7/2003
`3%
`TP(Texture Pipe)
`2877.46
`070
`4,110,637
`669,007
`4,779,644
`4
`19,118,577
`2.00.
`9,559,289
`25/2003
`9%
`
`
`
`
`TC- TCF(Texture Fetch) 2,263,457©552,6862,067,420 070 3,508,143 1 3,506,143 060 2,103,686 2/7/2003 2%
`
`
`
`
`
`
`TC - TCM(Texture Memory)
`3,359,488
`O76
`4,799,069 2,496,368
`7,295,437
`1
`7,295,437
`060
`4,377,262
`22003
`3%
`TC- TOR (Texture Return)
`3.489.417
`070
`4,985,453. 1,043,284
`6,028,737
`1.
`6,028,737
`0.60
`§=3,617,242
`26/2003
`3%
`RB (Render Backend)
`7,006,140
`0.70
`10,123,058. 1,583,484 11,706,542
`4
`48,826,167
`2.00
`23,413,084
`2/8/2003
`21%
`AB (Alpha Blend)
`1,790,687
`0.70
`2,568,124
`0
`2,558,124
`4.
`10,232,497
`2.00
`5,116,249
`2/7/2003
`S%
`RC (Render Centra)
`185,001
`0.70
`264,287
`9
`264,287
`1
`264,287
`1.00
`264,287
`1/27/2003
`O%
`SX(ShaderExport)
`1,268,629
`0.70
`1,798,042 2,307,229
`4,105,271
`2
`8,210,541
`1.00.
`4,105,271
`26/2003
`4%
`WMC (femory Controtier}
`412.438
`0.70
`$89,197
`$38,583
`1,127,779
`4
`4,511,117
`2.00
`2,255,559
`1/28/2003
`2%
`Analog + DFT
`6,534,500
`7,932,191 12/31/2002
`3%
`
`Totat Core (um2}
`218,259,974
`140,372,214
`
`100%
`
`DIyAy4t a
`
`
`6
`CONEIDENTIAL
`
`Current Pad separation (um)
`Current Pad height (um)
`Scribe
`Core mmiside
`Total mmvside
`
`50
`380
`0.18
`
`14.77
`15.65
`
`11.85
`12.73
`
`ATI Corporate Presentation
`
`AMD1044_0051108
`
`ATI Ex. 2017
`IPR2023-00922
`Page 6 of 6
`
`ATI Ex. 2017
`
`IPR2023-00922
`Page 6 of 6
`
`