Case IPR2015-00325 of
`U.S. Patent No. 7,742,053
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`LG ELECTRONICS, INC.,
`Petitioner
`
`Vv.
`
`ATI TECHNOLOGIES ULC,
`Patent Owner
`
`
`
`Case IPR2015-00325
`Patent 7,742,053
`
`
`DECLARATION OF ANDREW WOLFE
`REGARDING ACTUAL REDUCTION TO PRACTICE OF
`U.S. PATENT NO. 7,742,053
`
`Mail Stop “Patent Board”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`ATI 2106
`
`LGv. ATI
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`IPR2015-00325
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`AMD1044_0010434
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`Case IPR2015-00325 of
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`Table of Contents
`
`INTRODUCTION oooooooccccccccccc ccc cece cece teceesececssesisetecaesenstsesterstecniterteeeeteees 1
`
`BACKGROUND 0oooooooocccccccccc cece cece cece cesses tecesetesesesaetessitesittetsteentteseeensees 1
`
`EXHIBITSocc cccccccccccsecesetecseccvseeeceuseeesseecsseceseeecseesesesessseessteesseeesseesteees 6
`
`REDUCTION TO PRACTICE oo..cccccccccccceccccccccecececneeeesesesseeessssensesesseesneeey 8
`
`I.
`
`I.
`
`IV.
`
`A.—Actual Reduction to Practice 0.0000... ccccccccccccccetececcseeseessseeettatscenseees 8
`
`B.
`
`Constructive Reduction to Practice 2.000000... coc ccecceeccc cece ceetteeeeeeees 9
`
`<
`
`U.S. PATENT NO. 7,742,053 ooccccccccccccccccccseeessececssecnsseessesessesessesenseesues 10
`
`BACKGROUND ON CHIP DESIGN AND ATI’S CHIP DESIGN........... 11
`
`THE CODE FOR ATI’S R400 CHIP ooo. ccccceccsecessesessesesseeenseenues 13
`
`A.
`
`The R400 RTL code corresponding to claims 1, 2, 5,6, and 7 .......... 15
`
`1.
`
`Chain Loic cece cece ccc c cee eseeee cece ceases secesessenesteeeteeesentseeeees 17
`
`The Preamble ..0.....00.cc cc ccccccccc ce ceeceenscsesseeesesesseesseeees 17
`a
`The at Least One MemoryDevice... cece 19
`b
`The Arbiter. .0....000ccc ccc cece cece cece ee cet ee ceteeeeneeeees 23
`C.
`The Arbiter 1s Operable to Select a Command Thread ..28
`d.
`Cha2 eee ccccccccceceecccssececseecseceseseceessessseesesesseseiteeseesss 32
`
`a.
`b.
`
`The Preamble 00000000000 occ cece cece cee cece ee ceteeteceeeee 32
`The Arbiter is Operable to Provide a Command Thread to
`the Command Processing Engine ..........000cc cece cece36
`Chat 5 coc cece cece ce ee bees tebe nese teceeeesensteentieetentseenes 62
`
`Chat6 occ cece cece sees ees eeee este ceases teceseesenssteseiseesentieeeees 68
`
`Cha7 oie ccc ccccccnecccssueeecseecssececeaeceeesesesesseeesseereecseeesas 69
`
`2.
`
`3.
`
`4,
`
`5.
`
`B.
`
`The R400 Emulator Code Describing Claims 1, 2, 5, 6, and 7...........69
`
`1.
`
`Chat bocce ccc ce cece cece cece cece ee ceteseteesensstesetitesentseenes 71
`
`The Preamble 0000000000000 cece cece cece ce sce eeceeseteceeeee 71
`a.
`The at Least One MemoryDevice... cece75
`b.
`The Arbiter... ccccccccecccccsseceenseessseesceesseeessaeeees 78
`C.
`The Arbiter is Operable to Select a Command Thread ..82
`d.
`Chai 2 oie eee cccccccccccecccsssececseeessececeaeceeesesssesesecesseesieeesseeeess 96
`
`2.
`
`a.
`
`The Preamble ..00.0.000 ccc ccccccccccccceeceenceesseeesseeeteeeseeeens 96
`
`-i-
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`The Arbiter is Operable to Provide a Command Thread to
`the Command Processing Engine ..........00.00.000cccceeeee99
`3. 1a 5S oie ccecccccceeccseceseecrsecseeeseeesececseecseesseeeseetsseesseeseenees 101
`
`b.
`
`4.
`
`5.
`
`1a6 oo cccccccccccseccseceseccrseecseeeseeesececseecseesseeeseetsteesseeseenees 110
`
`Cha7 once cece ect c cece tees ee eee cecececesestesentstetteetteteseess 110
`
`VITT. The Claims of the ?053 Patent Are Supported by the Priority
`DOCUMENT... eee ccc cece cee cecetececeecsseereseeeesereeesseecsececsiesesseceiateesseeesireetieess 110
`
`TX.
`
`CONCEPTION 20. cece ceccsseesecseeeesseesseessecsaeceseecsescseesseesseeeeeeseeees 136
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`-ii-
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`Case IPR2015-00325 of
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`I, Andrew Wolfe, declare as follows:
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained by Advanced Micro Devices (“AMD”) as an
`
`expert to evaluate source code related to the development of the “R400”projectat
`
`its state of development on August 5, 2002, and to provide my opinion regarding
`
`whether the functionality of this source code for the R400 chip andthe structureit
`
`describes corresponds to each and every element as set forth in claims 1, 2, 5, 6,
`
`and 7 of the U.S. Patent No. 7,742,053 (‘Lefebvre °053 patent’).
`
`2.
`
`I have also been retained by AMD to reviewU.S. Patent Application
`
`No. 10/673,761 (“the ’761 Application”), filed September 29, 2003, to which the
`
`°053 patent claims priority, and to provide my opinion regarding whether claims1,
`
`2, 5,6, and 7 are supported by the ’761 Application.
`
`3,
`
`And, I have been retained by AMD to review ATI Technologies
`
`ULC.’s “ATY’) R400 chip internal documents from August 24, 2001 to April 19,
`
`2002, and to provide my opinion regarding whether the inventors of the ’053
`
`patent conceived claims 1, 2, 5, 6, and 7.
`
`I.
`
`BACKGROUND
`
`4.
`
`I have more than 30 years of experience as a computerarchitect,
`
`computer system designer, personal computer graphics designer, educator, and
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`-[-
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`executive in the electronics industry. A curriculum vitae is attached as Exhibit
`
`2136 to this report and is summarized below.
`
`5.
`
`In 1985, | earned a B.S.E.E. in Electrical Engineering and Computer
`
`Science from The Johns Hopkins University. In 1987, I received an M.S. degree in
`
`Electrical and Computer Engineering from Carnegie Mellon University. In 1992,I
`
`received a Ph.D. in Computer Engineering from Carnegie Mellon University. My
`
`doctoral dissertation pertained to a newapproach for the architecture of a computer
`
`processor.
`
`6.
`
`In 1983, I began designing touch sensors, microprocessor-based
`
`computer systems, and I/O (input/output) cards for personal computers as a senior
`
`design engineer for Touch Technology, Inc. During the course of mydesign
`
`projects with Touch Technology, I designed I/O cards for PC-compatible computer
`
`systems, including the IBM PC-AT,to interface with interactive touch-based
`
`computer terminals that I designed for use in public information systems. I
`
`continued designing and developing related technology as a consultant to the
`
`Carroll Touch division of AMP,Inc., where in 1986, I designed one ofthefirst
`
`custom touch screen integrated circuits.
`
`7.
`
`While I studied at Carnegie Mellon University for my master’s
`
`degree, from 1986 and through 1987, I designed and built a high-performance
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`AMD1044_0010438
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`computer system. From 1986 through early 1988, I also developed the curriculum,
`
`and supervised the teaching laboratory, for processor design courses.
`
`8.
`
`In the latter part of 1989, | worked as a senior design engineer for
`
`ESL-TRW Advanced Technology Division. While at ESL-TRW,I designed and
`
`built a bus interface and memory controller for a workstation-based computer
`
`system, and also worked on the design of a multiprocessor system.
`
`9,
`
`At the end of 1989, I (along with my partners) reacquired the rights to
`
`the technology I had developed at Touch Technology and at AMP, and founded
`
`The Graphics Technology Company. Over the next seven years, as an officer and
`
`a consultant for The Graphics Technology Company, I managed the company’s
`
`engineering developmentactivities and personally developed dozens of touch
`
`screen sensors, controllers, and interactive touch-based computer systems.
`
`10.
`
`Ihave consulted, formally and informally, for a number of fabless
`
`semiconductor companies. In particular, | have served on the technical advisory
`
`boards for two processor design companies: BOPS, Inc., where I chaired the board,
`
`and Siroyan Ltd., where I served in a similar role for three networking chip
`
`companies—Intellon, Inc., Comsilica, Inc., and Entridia, Inc—and one 3D game
`
`accelerator company, Ageia, Inc.
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`AMD1044_0010439
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`Thavealso served as a technology advisor to Motorola and to several
`
`11.
`
`venture capital funds in the United States and Europe. Currently, I am a director of
`
`Turtle Beach Corporation, providing guidance in its development of premium
`
`audio peripheral devices for a variety of commercial electronic products.
`
`12.
`
`From 1991 through 1997, I served on the Faculty of Princeton
`
`University as an Assistant Professor of Electrical Engineering. At Princeton,I
`
`taught undergraduate and graduate-level courses in Computer Architecture,
`
`Advanced Computer Architecture, Display Technology, and Microprocessor
`
`Systems, and conducted sponsored research in the area of computer systems and
`
`related topics.
`
`I was also a principal investigator for Department of Defense
`
`(“DOD”) research in video technologyanda principal investigator for the New
`
`Jersey Center for Multimedia Research. From 1999 through 2002, I taught the
`
`Computer Architecture course to both undergraduate and graduate students at
`
`Stanford University multiple times as a Consulting Professor. At Princeton,I
`
`received several teaching awards, both from students and from the School of
`
`Engineering. I have also taught advanced microprocessor architecture to industry
`
`professionals in IEEE and ACM sponsored seminars.
`
`I am currently a lecturer at
`
`Santa Clara University teaching graduate courses on Computer Organization and
`
`Architecture and undergraduate courses on electronics and embedded computing.
`
`AMD1044_0010440
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`From 1997 through 2002, I held a variety of executive positionsat a
`
`13.
`
`publicly-held fabless semiconductor company originally called S3, Inc. and later
`
`called SonicBlue Inc. I held the positions of Chief TechnologyOfficer, Vice
`
`President of Systems Integration Products, Senior Vice President of Business
`
`Development, and Director of Technology, among others. At the time I joined S3,
`
`the company supplied graphics accelerators for more than 50%of the PCs sold in
`
`the United States.
`
`14. While at S3/SonicBlue I developed technology for and participated in
`
`the development of products for digital music and digital video including HDTVs,
`
`DVD players and recorders, DVRs, portable video devices, PDAs, andtablets. [
`
`also supervised the video research and developmentteam.
`
`15.
`
`Thave published more than 50 peer-reviewed papers in computer
`
`architecture and computer systems and IC design.
`
`16.
`
`also have chaired [EEE and ACM conferences in microarchitecture
`
`and integrated circuit design and served as an associate editor for IEEE and ACM
`
`journals.
`
`17.
`
`Iam anamed inventor on at least 43 U.S. patents and 27 foreign
`
`patents.
`
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`In 2002, I was the invited keynote speaker at the ACM/TEEE
`
`18.
`
`International Symposium on Microarchitecture and at the International Conference
`
`on Multimedia. From 1990 through 2005, I was also an invited speaker on various
`
`aspects of technology and the PC industry at numerous industry events including
`
`the Intel Developer’s Forum, Microsoft Windows Hardware Engineering
`
`Conference, Microprocessor Forum, Embedded Systems Conference, Comdex, and
`
`Consumer Electronics Show, as well as at the Harvard Business School and the
`
`University of Illinois LawSchool. I have been interviewed on subjects related to
`
`computer graphics and video technology and the electronics industry by
`
`publications such as the Wall Street Journal, New York Times, Los Angeles
`
`Times, Time, Newsweek, Forbes, and Fortune as well as CNN, NPR, and the
`
`BBC. I have also spoken at dozens of universities including MIT, Stanford,
`
`University of Texas, Carnegie Mellon, UCLA, University of Michigan, Rice, and
`
`Duke.
`
`19.
`
`Tam being compensated for my time working onthis case at my
`
`customary rate of $450 per hour for work performed on the case. My compensation
`
`is not in any wayrelated to the outcomeof the case.
`
`Tl. EXHIBITS
`
`20.
`
`In this Declaration, I cite to the following Exhibits.
`
`AMD1044_0010442
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`
`
`
`
`
`United States Patent No. 7,742,053 to Lefebvreet al.
`
`
`
`
`
`
`
`2010
`R400 Sequencer Specification (Version 0.4)
`
`oe2028
`R400Sequencer Specification (Version2.0)
`2041
`R400 Top Level Specification (Version 0.2)
`
`
`2042
`R400 Shader Processor (Version 0.1)
`
`
`2072
`RTL Code File: sq.v
`
`
`2073
`RTL CodeFile: sq_thread_buff.v
`
`
`2074
`RTL CodeFile: sqthreadarb.v
`
`
`2075
`RTL CodeFile: sq_ctl_flow_seq.v
`
`
`2076
`RTL CodeFile: sq_instruction_store.v
`
`
`2077
`RTL CodeFile: sqtargetinstrfetch.v
`
`
`2078
`RTL CodeFile: sq_tex_instr_queue.v
`
`
`2079
`RTL CodeFile: sq_tex_instr_seq.v
`
`
`2080
`RTL CodeFile: sqaisoutput.v
`
`
`2081
`RTL Code File: sq_alu_instr_queue.v
`
`
`2082
`
`2083
`
`RTL CodeFile: sq_alu_instrseq.v
`
`RTL CodeFile: sp.v
`
`2084
`RTL Code File: vector.v
`
`
`RTL Code File: mace_gpr.v
`2085
`
`2086s| RTL CodeFile: mace.v
`
`
`2087
`RTL Code File: tp.v
`
`
`2088
`Emulator Code File: sq_block_model.cpp
`
`
`2089
`Emulator Code File: user_block_model.h
`
`
`2090
`Emulator Code File: arbiter.cpp
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`Emulator Code File: arbiter.h
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`2091
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`AMD1044_0010443
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`EmulatorCodeFile:sqalucpp
`ee2092
`2093
`Emulator Code File: sq_alu.h
`
`
`
`
`
`
`
`
`
`
`2094
`Emulator Code File: gpr_manager.cpp
`
`——2095EmulatorCodeFile:gpr_manager.h_
`2096
`Emulator Code File: instruction_store.cpp
`
`
`2097
`Emulator Code File: instruction_store.h
`
`
`2098
`Emulator Code File: reg_file.cpp
`
`
`2099
`Emulator Code File: reg_file.h
`
`
`2100
`Emulator Code File: tp.cpp
`
`
`2101
`Emulator Code File: tp.h
`
`
`2102
`Emulator Code File: sq_tp-h
`
`
`2103
`Emulator Code File: tp_block model.cpp
`
`
`2104
`Emulator Code File: user_block_model.h(tp)
`
`
`2108
`RTL CodeFile: tp_input.v
`
`
`2119
`United States Patent Application No. 10/673,761 to Lefebvre et
`al.
`
`
`2136
`
`Curriculum Vitae of Dr. Andrew Wolfe
`
`IV. REDUCTION TO PRACTICE
`
`21.
`
`JT understand there are two types of reduction to practice — actual
`
`reduction to practice and constructive reduction to practice. My understanding of
`
`each, I describe below.
`
`A,
`
`Actual Reduction to Practice
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`lunderstand that actual reduction to practice requires proofofeither
`
`22.
`
`(i) an embodiment of a claimed invention or (i1) performanceof a processthat
`
`includesall limitations of the claimed invention.
`
`23. Here, I have examined twotypes of source code: the R400 RTL code
`
`for an early version of the R400 written in Verilog and the corresponding Emulator
`
`Code written in C++. Verilog RTL codeis a structural and functional embodiment
`
`of a design that in the development of 3D graphics chips is generally used to
`
`model, define, and instantiate a hardware design. The C++ Emulator codeis
`
`generally used in the development of 3D graphics chips to model, validate, and test
`
`the functionality and certain structural features of a hardware design. Below,I will
`
`identify the specific files, objects, input/output interfaces, and functions that
`
`describe each element of claims 1, 2, 5, 6, and 7 of the ’053 patent.
`
`B.
`
`Constructive Reduction to Practice
`
`24.
`
`[understand that constructive reduction to practice occurs when the
`
`patent application discussing the subject matter of the claims is filed. In this case,
`
`the constructive reduction to practice occurred on September9, 2003, with the
`
`filing of the °761 Application. I understand that the °053 patent claimspriority to
`
`the °761 Application, because, U.S. Patent Application No. 11/764,453 from which
`
`the ’053 patent issued, is a continuation of the °761 Application. Below, I include a
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`AMD1044_0010445
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`claim chart where I identify support for each element of claims 1, 2, 5, 6, and 7 of
`
`the °053 Patent in the °761 Application.
`
`Vv.
`
`U.S. PATENT NO. 7,742,053
`
`25.
`
`The ’053 patent is directed to a graphics-processing system having a
`
`unified shader. The unified shader can perform both pixel and vertex calculations.
`
`To do this, the °053 patent includes at least one memory device designed to store a
`
`plurality of pixel commandthreads and a plurality of vertex command threads.
`
`(053 patent, Abstract.)
`
`26.
`
`The first reservation station 302 and the second reservationstation
`
`304 ofthe °053 patent represent the “at least one memory device” of independent
`
`claims 1 and 5. (053 patent, 3:63-64.) The first reservation station 302 is a pixel
`
`reservation station and stores pixel commandthreads (including 312, 314, and
`
`316), while the second reservation station is a vertex reservation station and stores
`
`vertex command threads (including 318, 320, and 322). Ud., 3:66-4:4.)
`
`27.
`
`The pixel commandthreads 312, 314, and 316 and the vertex
`
`commandthreads 318, 320, and 322, exemplify the commandthreads of the
`
`claimed inventions.
`
`28.
`
`The claims of the °053 patent also include an arbiter. The arbiter in a
`
`preferred embodimentis operable to select a command thread from the vertex and
`
`-10-
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`pixel reservation stations by picking the first commandthread ready to execute.
`
`(/d., 3:49-51.) The arbiter’s selection is based on a priority scheme, which may
`
`depend on which commands have alreadybeen or are to be executed within a
`
`commandthread and/or the age of the commandthread in the reservation station.
`
`(1d., 3:31-36.)
`
`29.
`
`The arbiter provides the selected command thread to a command
`
`processing engine. (/d., 3:8-11.)
`
`30.
`
`The ’053 patent specification recites two types of exemplary
`
`command processing engines: the ALU processing engine referred to as ALU 308
`
`and a texture processing engine, such as a graphics-processing engine 310. (/d.,
`
`4:30-33.)
`
`VI. BACKGROUND ON CHIP DESIGN AND AT?S CHIP DESIGN
`
`31.
`
`Inmy experience, modern graphics chip production is a two-step
`
`process. First, the integrated-circuit designers design a chip almostentirely on a
`
`computer using computer-aided—design (“CAD”) tools. The integrated-circuit
`
`designers depend on software-based design, simulation, verification, and layout
`
`tools. These tools ensure that production integrated circuits function and work as
`
`intended. This process can take several months or years. These CAD tools are used
`
`to create a chip specification, generally at multiple levels of abstraction, that serve
`
`-1ll-
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`as both a detailed specification of the chip and as a modelofits structure and
`
`function. This has been the predominant design methodology for graphics chips
`
`since at least 1990.
`
`32.
`
`The CAD tools are used to model and validate the chip design. While
`
`the design representation at this stage may resemble software, its primary purpose
`
`is to be an accurate representation of a hardware chip design. In the case of
`
`hardware description languages like Very High Speed Integrated Circuit Hardware
`
`Description Language (“VHDL”) or Verilog, the design languageis generally the
`
`
`most accurate formal specification of the structure and function of the chip that the
`
`design engineer will prepare. It is used to directly create the manufacturing
`
`tooling. Only after the integrated-circuit designers are confident that the design
`
`will function properly, and the chip design passes commercial specifications, the
`
`layoutfile created by the CAD tools from the design languageis sent to a chip-
`
`manufacturing facility for fabrication. Since layout files were historically provided
`
`on a magnetic tape, this is often called a “tape-out.” At this point the design
`
`process has been completed and the manufacturing step is intended to simply
`
`reproduce an exact copy of what is described in the layout file. The layoutfile
`
`represents the manufacturing tooling for the chip-manufacturing facility. The chip-
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`manufacturing facility uses this tooling to fabricate a physical integrated circuit,
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`commonly referred to as a “chip.”
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` Inmy experience, although both circuit design and circuit fabrication
`
`33.
`
`are both necessary components of chip production, in reality they are separate and
`
`distinct activities. Typically, chip design and chip fabrication are performed by
`
`different entities, particularly with respect to graphics chips. Ordinarily, circuit
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`designers do not fabricate chips, and chip fabricators do not design circuits.
`
`34.
`
`Itis my understandingthat, the patent owner here, ATLis a chip-
`
`design company. This means that ATI designs integrated circuits, such as chips.
`
`ATI does not fabricate chips. Instead, ATI uses software-based CAD tools to
`
`design and reduce to practice the chip components claimed in the 7053 patent. Only
`
`after the components claimed in the °053 patent (along with other chip
`
`components) worked for their intended purpose, would ATI generate the tooling
`
`and send it for fabrication. Because the ’053 patent pertains to the chip-circuit
`
`design, the actual reduction to practice of the claims of the 053 patent would have
`
`occurred when the RTL code or the Emulator Code performedall limitations of the
`
`claims.
`
`VIL THE CODE FOR ATI’S R400 CHIP
`
`35.
`
`[have been asked to reviewthe source code for ATI’s R400 chip. I
`
`will cite to the source code using the following format: (sq.v, 1:1-10). This
`
`example citation points to exhibit sq.v, at page 1, lines 1-10.
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`There are two corresponding design databases that comprise the
`
`36.
`
`source code: R400 RTL code and Emulator Code. The R400 RTL codeis
`
`implemented in a hardware-description language (HDL), called Verilog. Verilog is
`
`used to design and verify digital circuits at register-transfer level of abstraction
`
`which can include both structure and function. For example, in the R400 program,
`
`Verilog was used to validate the integrated-circuit version of the graphics-
`
`processing system recited in claims 1, 2, 5, 6, and 7.
`
`37.
`
`The R400 Emulator Codeis written in a well-known C++
`
`programming language. The R400 Emulator Code includes source code that, when
`
`executed, emulates the behavior of the graphics-processing system recited in
`
`claims 1, 2, 5, 6, and 7 using software that executes on a computer. C++ is
`
`commonly used to specify the function of a software system, but chip designers
`
`often also use it to specify and emulate structural aspects of hardware systems,
`
`such as, chips.
`
`38.
`
`In my experience having both RTL code and C++ code
`
`implementation is commonin the chip design industry. The C++ codeis faster to
`
`write and easier to debug by the chip designers. It runs faster, so larger examples of
`
`user input can be tested. The chip designers often first write and test the chip
`
`design in C++ or another software language. The test results from the chip code in
`
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`C++ are saved. Next the RTL codeis written in Verilog or another hardware-
`
`description language and is compared against the test results generated using the
`
`C++ code. By comparing two different descriptions of the hardware
`
`implementation, it is more likely that errors can be found and removed.
`
`39.
`
`[have compared each element of claims 1, 2,5, 6, and 7 to the R400
`
`R400 RTL code and the Emulator Code. Below, I will discuss each element of
`
`claims 1, 2, 5, 6, and 7, and the correspondingfiles, functions, and interfaces along
`
`with the pages and line numbers in the RTL and/or Emulator Code that disclose the
`
`same element. In my opinion, both the R400 RTL code and the R400 Emulator
`
`Code each disclose all elements of claims 1, 2, 5, 6, and 7.
`
`40. Atleast one version of the R400 RTL code whichdiscloses all
`
`elements of claims 1, 2,5, 6, and 7 includesthe files generated before or on August
`
`5, 2002, and are attached as Exhibits 2072-2087.
`
`41. Atleast one version of the R400 Emulator Code which disclosesall
`
`elements of claims 1, 2, 5, 6, and 7 includes the files generated before or on August
`
`5, 2002, and are attached as Exhibits 2088-2104.
`
`A,
`
`The R400 RTL code corresponding to claims I, 2, 5, 6, and 7
`
`42.
`
`AsIT mentioned above, the R400 RTL Code is written in Verilog
`
`language. Verilog is a hardware-description language used to design and specify
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`hardware systems. That 1s, Verilog describes behavior of a hardware circuit in
`
`terms of inputs, outputs, state machines, logic equations, and modules. When a
`
`module is declared in Verilog, the declaration is definitional. This serves as a
`
`specification of function and structure. Copies of that module can then be
`
`instantiated by specifying the inputs and outputs that carry information to and from
`
`a particular copy of the module. This instructs the CAD tools to create a copy of
`
`the specified circuits in each final product. It is possible to have multiple copies of
`
`a module, with the inputs and outputs of each copy separately specified in the
`
`design. The logic equations for the module, which describe howthe module
`
`operates based on different inputs, are also specified. This logic can be
`
`combinational, representing a set of basic logic gates, or sequential, which can
`
`include a state machine that controls the operation over time. There are many
`
`different ways to write these logic equations, but each is converted to a set of basic
`
`logic gates by the CAD tools. From the files produced by the R400 RTL code, a
`
`chip manufacturer is able to manufacture a hardware circuit that includes structure
`
`and behavior described in the R400 RTL code. This is a standard practice in any
`
`modern graphics integrated circuit design.
`
`43.
`
`The R400 RTL code includes the sq.v, sp.v, tp.vfiles and their
`
`corresponding sub-files and referenced modules that specify and generate a
`
`hardware circuit which is a graphics-processing system as recited in claims1, 2,5,
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`6, and 7. In particular, the sq.v file specifies and generates a sequencer which
`
`includes an arbiter and the at least one memory recited in the claims. The sp.v and
`
`tp.v files each specify and generate a command processing engine — the ALU
`
`processing engine (sp.v) and a texture processing engine(tp.v). I will discuss each
`
`of these components below.
`
`I.
`
`Claim I
`
`a.
`
`‘The Preamble
`
`44.
`
`The preamble of claim | recites “4 graphics processing system.” The
`
`R400 RTLcode included in the files attached as Exhibits 2072-2087 generates
`
`components of the graphics-processing system of claim 1. The file, sq.v, defines
`
`the hardware blocks of the graphics-processing system componentcalled a
`
`sequencer. In particular, sq.v instantiates a texture thread arbiter
`
`u_sqtexthread_arb (sq.v, 43:3-44-21), an ALU thread arbiter
`
`u_sqalu_thread_arb (sq.v, 47:6-48-24), a memory buffer that stores pixel
`
`commandthreads usqpixthreadbuff(sq.v, 38:27-42:29), and a memory buffer
`
`that stores vertex command threads u_sq_vtx_thread_buff(sq.v, 34:22-38:24). The
`
`memory buffers are what the ’053 patent refers to as the pixel reservation station
`
`and the vertex reservation station.
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`Thave generated a visual representation of these components, as I
`
`45.
`
`understand them, based on the R400 RTL code,
`
`in a figure below. The figure
`
`includes the names of the components as they are instantiated in sq.v.
`
`
`
`Pixel Reservation Station |
`
`| Vertex Reservation Station. |
`
`| u_sqpix thread_buff|
`(sq.v)
`
`
`/u_sq_vtx_thread_buff|
`(sq.v)
`
`
`
`
`
`
`ALU Thread Arbiter
`
`Texture Thread Arbiter
`
`
`
`| u_sqalu_threadarb |
`u_sq texthread_arb |
`(sq.¥)
`
`sq.v
`
`AAACOAAAAAOEOOAAAROMRRNRRR
`
`46.
`
`The texture thread arbiter (u_sq_texthreadarb) and the ALU thread
`
`arbiter (uw_sq_alu_thread_arb) are arbiterof the °053 patent that I described above,
`
`and that is recited in claim 1.
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`A7. Also, the u_sq_pix_thread_buffis amemorybufferfor a pixel
`
`reservation station, while the usq_vix_thread_buffis a memory buffer for a vertex
`
`reservation station, which I also described above. The u_sq_pix_thread_buffand
`
`the wusq_vixthread_buff structures are componentsofthe at least one memory
`
`device recited in claim 1.
`
`b.
`
`The at Least One Memory Device
`
`48.
`
`Thefirst element of claim | recites “ut /eust one memorydevice
`
`comprising afirst portion operative to store a plurality ofpixel commandthreads
`
`and a secondportion operative to store a plurality ofvertex command threads.”
`
`49. As I discussed above, the sq.vfile instantiates a memory buffer for
`
`pixel commandthreads called u_sq_pix_thread_buffmodule (sq.v, 38:27- 42-29)
`
`and a memorybuffer for vertex command threads called au_sq_vix_threadbuff
`
`module (sq.v, 34:22-38-24). The sqthreadbuffmodule defined in
`
`sq_thread_buff.v generates usqpixthreadbuffandu_sq_vtx_thread_buff.
`
`Module uwsqpixthreadbuffis the pixel reservationstation and
`
`u_sqvtxthreadbuffis the vertex reservation station of the °053 patent. I have
`
`generated a visual representation of the pixel reservation station and the vertex
`
`reservation station, as I understand it, based on the R400 RTL cade,in a figure
`
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`below. The figure includes the names of the components as they are instantiated in
`
`files that describe the structure and behavior of the components.
`
`Vertex Reservation Station
`
`u_eg pixthread:butt
`
`Pixel Reservation Station u_sqvtx_thread_buft
`
`
`(sq.v)
`(eq) aqthread.butt. eq.threadbuftt.v
`
`50. With respect to the pixel command threads and vertex command
`
`threads, each of sq_pix_thread_buffand sq_vix_thread_buffincludes 16 registers,
`
`referred to as u0_sq_statusregtoul5sqstatus_reg. (sq_thread_buff.v, 37:16-
`
`54:16.) Each register stores a command thread, including the command thread’s
`
`state and status information. The hardware code that generates a second register
`
`that stores a commandthread1s replicated below:
`
`sqstatusreg #e TIDWIDTH, STATUSWIDTH )
`uisqstatusreg (
`.tChread_typestrap (thread_type_strap),
`-ismload(ism_ status_selfi]),
`.ism_ thread_id(statetailptrgq),
`.ism_resource (ism resource),
`-ism_first_thread(ism_ firstthread),
`.cfsupdate(cfsupdate),
`Q
`fsthread_id(cfsthread_id),
`.cfsalu_instr_pending(cfs_alu_instr_pending),
`.cfspulse sx(cfspulsesx),
`.cf£slastinstr(cfslast_instr),
`.cf&sposailocated(cfsposaliocated),
`.cfsalice_type(cfs alloctype),
`.cfsaliocsize(cfs alioc_ size),
`‘fstex readpending(cfs_ tex_read_pending),
`-C£s_ seriai(cfsserial),
`.cfsresource(cfsresource),
`
`-~20-
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`.cfsthread valid(cfs_ threadvalid),
`-SXposavail (posavaii_q),
`.sx_buf_avail(buf_avail_gq),
`-baram cache wptrq(p